2015-10-30 07:25:05 -06:00
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Allwinner A10 Display Pipeline
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==============================
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The Allwinner A10 Display pipeline is composed of several components
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that are going to be documented below:
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2017-07-17 22:02:01 -06:00
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For all connections between components up to the TCONs in the display
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pipeline, when there are multiple components of the same type at the
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same depth, the local endpoint ID must be the same as the remote
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component's index. For example, if the remote endpoint is Frontend 1,
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then the local endpoint ID must be 1.
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Frontend 0 [0] ------- [0] Backend 0 [0] ------- [0] TCON 0
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[1] -- -- [1] [1] -- -- [1]
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\ / \ /
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X X
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/ \ / \
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[0] -- -- [0] [0] -- -- [0]
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Frontend 1 [1] ------- [1] Backend 1 [1] ------- [1] TCON 1
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For a two pipeline system such as the one depicted above, the lines
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represent the connections between the components, while the numbers
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within the square brackets corresponds to the ID of the local endpoint.
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The same rule also applies to DE 2.0 mixer-TCON connections:
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Mixer 0 [0] ----------- [0] TCON 0
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[1] ---- ---- [1]
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\ /
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X
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/ \
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[0] ---- ---- [0]
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Mixer 1 [1] ----------- [1] TCON 1
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2017-04-21 02:38:49 -06:00
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2017-05-27 10:09:33 -06:00
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HDMI Encoder
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------------
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The HDMI Encoder supports the HDMI video and audio outputs, and does
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CEC. It is one end of the pipeline.
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Required properties:
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- compatible: value must be one of:
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2017-10-17 06:18:00 -06:00
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* allwinner,sun4i-a10-hdmi
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2017-05-27 10:09:33 -06:00
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* allwinner,sun5i-a10s-hdmi
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2017-10-09 21:20:03 -06:00
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* allwinner,sun6i-a31-hdmi
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2017-05-27 10:09:33 -06:00
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- reg: base address and size of memory-mapped region
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- interrupts: interrupt associated to this IP
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- clocks: phandles to the clocks feeding the HDMI encoder
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* ahb: the HDMI interface clock
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* mod: the HDMI module clock
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2017-10-09 21:20:03 -06:00
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* ddc: the HDMI ddc clock (A31 only)
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2017-05-27 10:09:33 -06:00
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* pll-0: the first video PLL
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* pll-1: the second video PLL
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- clock-names: the clock names mentioned above
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2017-10-09 21:20:03 -06:00
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- resets: phandle to the reset control for the HDMI encoder (A31 only)
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2017-05-27 10:09:33 -06:00
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- dmas: phandles to the DMA channels used by the HDMI encoder
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* ddc-tx: The channel for DDC transmission
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* ddc-rx: The channel for DDC reception
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* audio-tx: The channel used for audio transmission
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- dma-names: the channel names mentioned above
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- ports: A ports node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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first port should be the input endpoint. The second should be the
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output, usually to an HDMI connector.
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2018-02-14 13:09:00 -07:00
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DWC HDMI TX Encoder
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-------------------
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The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
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with Allwinner's own PHY IP. It supports audio and video outputs and CEC.
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These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
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Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
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following device-specific properties.
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Required properties:
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- compatible: value must be one of:
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* "allwinner,sun8i-a83t-dw-hdmi"
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- reg: base address and size of memory-mapped region
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- reg-io-width: See dw_hdmi.txt. Shall be 1.
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- interrupts: HDMI interrupt number
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- clocks: phandles to the clocks feeding the HDMI encoder
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* iahb: the HDMI bus clock
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* isfr: the HDMI register clock
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* tmds: TMDS clock
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- clock-names: the clock names mentioned above
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- resets: phandle to the reset controller
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- reset-names: must be "ctrl"
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- phys: phandle to the DWC HDMI PHY
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- phy-names: must be "phy"
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- ports: A ports node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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first port should be the input endpoint. The second should be the
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output, usually to an HDMI connector.
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DWC HDMI PHY
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------------
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Required properties:
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- compatible: value must be one of:
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* allwinner,sun8i-a83t-hdmi-phy
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2018-03-01 14:34:31 -07:00
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* allwinner,sun8i-h3-hdmi-phy
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2018-07-10 14:35:11 -06:00
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* allwinner,sun50i-a64-hdmi-phy
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2018-02-14 13:09:00 -07:00
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- reg: base address and size of memory-mapped region
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- clocks: phandles to the clocks feeding the HDMI PHY
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* bus: the HDMI PHY interface clock
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* mod: the HDMI PHY module clock
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- clock-names: the clock names mentioned above
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- resets: phandle to the reset controller driving the PHY
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- reset-names: must be "phy"
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2018-06-25 06:02:55 -06:00
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H3 and A64 HDMI PHY require additional clocks:
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2018-03-01 14:34:31 -07:00
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- pll-0: parent of phy clock
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2018-06-25 06:02:55 -06:00
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- pll-1: second possible phy clock parent (A64 only)
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2018-03-01 14:34:31 -07:00
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2015-10-30 07:25:05 -06:00
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TV Encoder
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----------
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The TV Encoder supports the composite and VGA output. It is one end of
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the pipeline.
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Required properties:
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- compatible: value should be "allwinner,sun4i-a10-tv-encoder".
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- reg: base address and size of memory-mapped region
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- clocks: the clocks driving the TV encoder
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- resets: phandle to the reset controller driving the encoder
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- ports: A ports node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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first port should be the input endpoint.
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TCON
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----
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The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
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Required properties:
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2016-01-07 04:32:25 -07:00
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- compatible: value must be either:
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2017-10-17 06:17:59 -06:00
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* allwinner,sun4i-a10-tcon
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2016-01-07 04:32:25 -07:00
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* allwinner,sun5i-a13-tcon
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2016-10-19 21:43:40 -06:00
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* allwinner,sun6i-a31-tcon
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* allwinner,sun6i-a31s-tcon
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2017-10-17 06:18:02 -06:00
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* allwinner,sun7i-a20-tcon
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2016-01-07 04:32:25 -07:00
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* allwinner,sun8i-a33-tcon
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dt-bindings: display: sun4i-drm: Add A83T pipeline
The A83T has two video pipelines in parallel that looks quite similar to
the other SoCs.
The video planes are handled through a controller called the mixer, and the
video signal is then passed to the timing controller (TCON).
And while there is two instances of the mixers and TCONs, they have a
significant number of differences. The TCONs are quite easy to deal with,
one is supposed to generate TV (in the broader term, so including things
like HDMI) signals, the other one LCD (so RGB, LVDS, DSI) signals. And
while they are called TCON0 and TCON1 in the A83t datasheet, newer SoCs
call them TCON-TV and TCON-LCD, which seems more appropriate.
However, the mixers differ mostly by their capabilities, with some features
being available only in the first one, or the number of planes they expose,
but also through their register layout. And while the capabilities could be
represented as properties, the register layout differences would need to
express all the registers offsets as properties, which is usually quite
bad. Especially since documentation on that hardware block is close to
non-existent and we don't even have the list of all those registers in the
first place.
So let's call them mixer 0 and 1 in our compatibles, even though the name
is pretty bad...
At the moment, we only have tested the code on a board that has a single
display output, so we're leaving the tcon-tv and mixer1 out.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2702a5c1d224af1c51743492ad1b917966f2ad43.1513854122.git-series.maxime.ripard@free-electrons.com
2017-12-21 04:02:30 -07:00
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* allwinner,sun8i-a83t-tcon-lcd
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2018-02-14 13:09:00 -07:00
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* allwinner,sun8i-a83t-tcon-tv
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2018-07-10 14:34:59 -06:00
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* allwinner,sun8i-r40-tcon-tv
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2017-05-14 10:30:35 -06:00
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* allwinner,sun8i-v3s-tcon
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2018-03-15 05:41:29 -06:00
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* allwinner,sun9i-a80-tcon-lcd
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* allwinner,sun9i-a80-tcon-tv
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2015-10-30 07:25:05 -06:00
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- reg: base address and size of memory-mapped region
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- interrupts: interrupt associated to this IP
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2018-02-14 13:09:00 -07:00
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- clocks: phandles to the clocks feeding the TCON.
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2015-10-30 07:25:05 -06:00
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- 'ahb': the interface clocks
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2018-03-15 05:41:29 -06:00
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- 'tcon-ch0': The clock driving the TCON channel 0, if supported
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2015-10-30 07:25:05 -06:00
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- resets: phandles to the reset controllers driving the encoder
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2018-03-15 05:41:29 -06:00
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- "lcd": the reset line for the TCON
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- "edp": the reset line for the eDP block (A80 only)
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2015-10-30 07:25:05 -06:00
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- clock-names: the clock names mentioned above
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- reset-names: the reset names mentioned above
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2018-02-14 13:09:00 -07:00
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- clock-output-names: Name of the pixel clock created, if TCON supports
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channel 0.
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2015-10-30 07:25:05 -06:00
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- ports: A ports node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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first port should be the input endpoint, the second one the output
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2018-02-14 13:09:00 -07:00
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The output may have multiple endpoints. TCON can have 1 or 2 channels,
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dt-bindings: display: sun4i: Add allwinner,tcon-channel property
The Allwinner Timings Controller has two, mutually exclusive, channels.
When the binding has been introduced, it was assumed that there would be
only a single user per channel in the system.
While this is likely for the channel 0 which only connects to LCD displays,
it turns out that the channel 1 can be connected to multiple controllers in
the SoC (HDMI and TV encoders for example). And while the simultaneous use
of HDMI and TV outputs cannot be achieved, switching from one to the other
at runtime definitely sounds plausible.
Add an extra property, allwinner,tcon-channel, to specify for a given
endpoint which TCON channel it is connected to, while falling back to the
previous mechanism if that property is missing.
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-05-27 10:09:34 -06:00
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usually with the first channel being used for the panels interfaces
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(RGB, LVDS, etc.), and the second being used for the outputs that
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require another controller (TV Encoder, HDMI, etc.). The endpoints
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will take an extra property, allwinner,tcon-channel, to specify the
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channel the endpoint is associated to. If that property is not
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present, the endpoint number will be used as the channel number.
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2015-10-30 07:25:05 -06:00
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2018-03-15 05:41:29 -06:00
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For TCONs with channel 0, there is one more clock required:
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- 'tcon-ch0': The clock driving the TCON channel 0
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For TCONs with channel 1, there is one more clock required:
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2016-01-07 04:32:25 -07:00
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- 'tcon-ch1': The clock driving the TCON channel 1
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2018-07-10 14:34:59 -06:00
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When TCON support LVDS (all TCONs except TV TCONs on A83T, R40 and those found
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2018-02-14 13:09:00 -07:00
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in A13, H3, H5 and V3s SoCs), you need one more reset line:
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2017-12-21 04:02:29 -07:00
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- 'lvds': The reset line driving the LVDS logic
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And on the A23, A31, A31s and A33, you need one more clock line:
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- 'lvds-alt': An alternative clock source, separate from the TCON channel 0
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clock, that can be used to drive the LVDS clock
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2018-06-25 06:02:44 -06:00
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TCON TOP
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--------
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TCON TOPs main purpose is to configure whole display pipeline. It determines
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relationships between mixers and TCONs, selects source TCON for HDMI, muxes
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LCD and TV encoder GPIO output, selects TV encoder clock source and contains
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additional TV TCON and DSI gates.
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It allows display pipeline to be configured in very different ways:
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/ LCD0/LVDS0
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/ [0] TCON-LCD0
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| \ MIPI DSI
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mixer0 |
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\ / [1] TCON-LCD1 - LCD1/LVDS1
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TCON-TOP
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/ \ [2] TCON-TV0 [0] - TVE0/RGB
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mixer1 | \
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| TCON-TOP - HDMI
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\ [3] TCON-TV1 [1] - TVE1/RGB
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Note that both TCON TOP references same physical unit. Both mixers can be
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connected to any TCON.
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Required properties:
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- compatible: value must be one of:
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* allwinner,sun8i-r40-tcon-top
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- reg: base address and size of the memory-mapped region.
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- clocks: phandle to the clocks feeding the TCON TOP
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* bus: TCON TOP interface clock
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* tcon-tv0: TCON TV0 clock
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* tve0: TVE0 clock
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* tcon-tv1: TCON TV1 clock
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* tve1: TVE0 clock
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* dsi: MIPI DSI clock
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- clock-names: clock name mentioned above
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- resets: phandle to the reset line driving the TCON TOP
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- #clock-cells : must contain 1
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- clock-output-names: Names of clocks created for TCON TV0 channel clock,
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TCON TV1 channel clock and DSI channel clock, in that order.
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- ports: A ports node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. 6 ports should
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be defined:
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* port 0 is input for mixer0 mux
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* port 1 is output for mixer0 mux
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* port 2 is input for mixer1 mux
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* port 3 is output for mixer1 mux
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* port 4 is input for HDMI mux
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* port 5 is output for HDMI mux
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All output endpoints for mixer muxes and input endpoints for HDMI mux should
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have reg property with the id of the target TCON, as shown in above graph
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(0-3 for mixer muxes and 0-1 for HDMI mux). All ports should have only one
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endpoint connected to remote endpoint.
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2016-06-09 06:01:58 -06:00
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DRC
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---
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The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs
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2018-03-15 05:41:32 -06:00
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(A31, A23, A33, A80), allows to dynamically adjust pixel
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2016-06-09 06:01:58 -06:00
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brightness/contrast based on histogram measurements for LCD content
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adaptive backlight control.
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Required properties:
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- compatible: value must be one of:
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2016-10-19 21:43:38 -06:00
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* allwinner,sun6i-a31-drc
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* allwinner,sun6i-a31s-drc
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2016-06-09 06:01:58 -06:00
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* allwinner,sun8i-a33-drc
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2018-03-15 05:41:32 -06:00
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* allwinner,sun9i-a80-drc
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2016-06-09 06:01:58 -06:00
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- reg: base address and size of the memory-mapped region.
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- interrupts: interrupt associated to this IP
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- clocks: phandles to the clocks feeding the DRC
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* ahb: the DRC interface clock
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* mod: the DRC module clock
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* ram: the DRC DRAM clock
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- clock-names: the clock names mentioned above
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- resets: phandles to the reset line driving the DRC
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- ports: A ports node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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first port should be the input endpoints, the second one the outputs
|
2015-10-30 07:25:05 -06:00
|
|
|
|
|
|
|
Display Engine Backend
|
|
|
|
----------------------
|
|
|
|
|
|
|
|
The display engine backend exposes layers and sprites to the
|
|
|
|
system.
|
|
|
|
|
|
|
|
Required properties:
|
|
|
|
- compatible: value must be one of:
|
2017-10-17 06:18:01 -06:00
|
|
|
* allwinner,sun4i-a10-display-backend
|
2015-10-30 07:25:05 -06:00
|
|
|
* allwinner,sun5i-a13-display-backend
|
2016-10-19 21:43:41 -06:00
|
|
|
* allwinner,sun6i-a31-display-backend
|
2017-10-17 06:18:02 -06:00
|
|
|
* allwinner,sun7i-a20-display-backend
|
2016-01-07 04:32:25 -07:00
|
|
|
* allwinner,sun8i-a33-display-backend
|
2018-03-15 05:41:32 -06:00
|
|
|
* allwinner,sun9i-a80-display-backend
|
2015-10-30 07:25:05 -06:00
|
|
|
- reg: base address and size of the memory-mapped region.
|
2017-03-27 08:38:46 -06:00
|
|
|
- interrupts: interrupt associated to this IP
|
2015-10-30 07:25:05 -06:00
|
|
|
- clocks: phandles to the clocks feeding the frontend and backend
|
|
|
|
* ahb: the backend interface clock
|
|
|
|
* mod: the backend module clock
|
|
|
|
* ram: the backend DRAM clock
|
|
|
|
- clock-names: the clock names mentioned above
|
|
|
|
- resets: phandles to the reset controllers driving the backend
|
|
|
|
|
|
|
|
- ports: A ports node with endpoint definitions as defined in
|
|
|
|
Documentation/devicetree/bindings/media/video-interfaces.txt. The
|
|
|
|
first port should be the input endpoints, the second one the output
|
|
|
|
|
2016-09-06 07:23:03 -06:00
|
|
|
On the A33, some additional properties are required:
|
|
|
|
- reg needs to have an additional region corresponding to the SAT
|
|
|
|
- reg-names need to be set, with "be" and "sat"
|
|
|
|
- clocks and clock-names need to have a phandle to the SAT bus
|
|
|
|
clocks, whose name will be "sat"
|
|
|
|
- resets and reset-names need to have a phandle to the SAT bus
|
|
|
|
resets, whose name will be "sat"
|
|
|
|
|
2018-03-15 05:41:30 -06:00
|
|
|
DEU
|
|
|
|
---
|
|
|
|
|
|
|
|
The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC,
|
|
|
|
can sharpen the display content in both luma and chroma channels.
|
|
|
|
|
|
|
|
Required properties:
|
|
|
|
- compatible: value must be one of:
|
|
|
|
* allwinner,sun9i-a80-deu
|
|
|
|
- reg: base address and size of the memory-mapped region.
|
|
|
|
- interrupts: interrupt associated to this IP
|
|
|
|
- clocks: phandles to the clocks feeding the DEU
|
|
|
|
* ahb: the DEU interface clock
|
|
|
|
* mod: the DEU module clock
|
|
|
|
* ram: the DEU DRAM clock
|
|
|
|
- clock-names: the clock names mentioned above
|
|
|
|
- resets: phandles to the reset line driving the DEU
|
|
|
|
|
|
|
|
- ports: A ports node with endpoint definitions as defined in
|
|
|
|
Documentation/devicetree/bindings/media/video-interfaces.txt. The
|
|
|
|
first port should be the input endpoints, the second one the outputs
|
|
|
|
|
2015-10-30 07:25:05 -06:00
|
|
|
Display Engine Frontend
|
|
|
|
-----------------------
|
|
|
|
|
|
|
|
The display engine frontend does formats conversion, scaling,
|
|
|
|
deinterlacing and color space conversion.
|
|
|
|
|
|
|
|
Required properties:
|
|
|
|
- compatible: value must be one of:
|
2017-10-17 06:18:01 -06:00
|
|
|
* allwinner,sun4i-a10-display-frontend
|
2015-10-30 07:25:05 -06:00
|
|
|
* allwinner,sun5i-a13-display-frontend
|
2016-10-19 21:43:41 -06:00
|
|
|
* allwinner,sun6i-a31-display-frontend
|
2017-10-17 06:18:02 -06:00
|
|
|
* allwinner,sun7i-a20-display-frontend
|
2016-01-07 04:32:25 -07:00
|
|
|
* allwinner,sun8i-a33-display-frontend
|
2018-03-15 05:41:32 -06:00
|
|
|
* allwinner,sun9i-a80-display-frontend
|
2015-10-30 07:25:05 -06:00
|
|
|
- reg: base address and size of the memory-mapped region.
|
|
|
|
- interrupts: interrupt associated to this IP
|
|
|
|
- clocks: phandles to the clocks feeding the frontend and backend
|
|
|
|
* ahb: the backend interface clock
|
|
|
|
* mod: the backend module clock
|
|
|
|
* ram: the backend DRAM clock
|
|
|
|
- clock-names: the clock names mentioned above
|
|
|
|
- resets: phandles to the reset controllers driving the backend
|
|
|
|
|
|
|
|
- ports: A ports node with endpoint definitions as defined in
|
|
|
|
Documentation/devicetree/bindings/media/video-interfaces.txt. The
|
|
|
|
first port should be the input endpoints, the second one the outputs
|
|
|
|
|
2017-05-14 10:30:35 -06:00
|
|
|
Display Engine 2.0 Mixer
|
|
|
|
------------------------
|
|
|
|
|
|
|
|
The DE2 mixer have many functionalities, currently only layer blending is
|
|
|
|
supported.
|
|
|
|
|
|
|
|
Required properties:
|
|
|
|
- compatible: value must be one of:
|
dt-bindings: display: sun4i-drm: Add A83T pipeline
The A83T has two video pipelines in parallel that looks quite similar to
the other SoCs.
The video planes are handled through a controller called the mixer, and the
video signal is then passed to the timing controller (TCON).
And while there is two instances of the mixers and TCONs, they have a
significant number of differences. The TCONs are quite easy to deal with,
one is supposed to generate TV (in the broader term, so including things
like HDMI) signals, the other one LCD (so RGB, LVDS, DSI) signals. And
while they are called TCON0 and TCON1 in the A83t datasheet, newer SoCs
call them TCON-TV and TCON-LCD, which seems more appropriate.
However, the mixers differ mostly by their capabilities, with some features
being available only in the first one, or the number of planes they expose,
but also through their register layout. And while the capabilities could be
represented as properties, the register layout differences would need to
express all the registers offsets as properties, which is usually quite
bad. Especially since documentation on that hardware block is close to
non-existent and we don't even have the list of all those registers in the
first place.
So let's call them mixer 0 and 1 in our compatibles, even though the name
is pretty bad...
At the moment, we only have tested the code on a board that has a single
display output, so we're leaving the tcon-tv and mixer1 out.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2702a5c1d224af1c51743492ad1b917966f2ad43.1513854122.git-series.maxime.ripard@free-electrons.com
2017-12-21 04:02:30 -07:00
|
|
|
* allwinner,sun8i-a83t-de2-mixer-0
|
2018-02-14 13:09:00 -07:00
|
|
|
* allwinner,sun8i-a83t-de2-mixer-1
|
2018-03-01 14:34:31 -07:00
|
|
|
* allwinner,sun8i-h3-de2-mixer-0
|
2017-05-14 10:30:35 -06:00
|
|
|
* allwinner,sun8i-v3s-de2-mixer
|
|
|
|
- reg: base address and size of the memory-mapped region.
|
|
|
|
- clocks: phandles to the clocks feeding the mixer
|
|
|
|
* bus: the mixer interface clock
|
|
|
|
* mod: the mixer module clock
|
|
|
|
- clock-names: the clock names mentioned above
|
|
|
|
- resets: phandles to the reset controllers driving the mixer
|
|
|
|
|
|
|
|
- ports: A ports node with endpoint definitions as defined in
|
|
|
|
Documentation/devicetree/bindings/media/video-interfaces.txt. The
|
|
|
|
first port should be the input endpoints, the second one the output
|
|
|
|
|
2015-10-30 07:25:05 -06:00
|
|
|
|
|
|
|
Display Engine Pipeline
|
|
|
|
-----------------------
|
|
|
|
|
|
|
|
The display engine pipeline (and its entry point, since it can be
|
|
|
|
either directly the backend or the frontend) is represented as an
|
|
|
|
extra node.
|
|
|
|
|
|
|
|
Required properties:
|
|
|
|
- compatible: value must be one of:
|
2017-10-17 06:18:01 -06:00
|
|
|
* allwinner,sun4i-a10-display-engine
|
2017-05-27 10:09:36 -06:00
|
|
|
* allwinner,sun5i-a10s-display-engine
|
2015-10-30 07:25:05 -06:00
|
|
|
* allwinner,sun5i-a13-display-engine
|
2016-10-19 21:43:41 -06:00
|
|
|
* allwinner,sun6i-a31-display-engine
|
|
|
|
* allwinner,sun6i-a31s-display-engine
|
2017-10-17 06:18:02 -06:00
|
|
|
* allwinner,sun7i-a20-display-engine
|
2016-01-07 04:32:25 -07:00
|
|
|
* allwinner,sun8i-a33-display-engine
|
dt-bindings: display: sun4i-drm: Add A83T pipeline
The A83T has two video pipelines in parallel that looks quite similar to
the other SoCs.
The video planes are handled through a controller called the mixer, and the
video signal is then passed to the timing controller (TCON).
And while there is two instances of the mixers and TCONs, they have a
significant number of differences. The TCONs are quite easy to deal with,
one is supposed to generate TV (in the broader term, so including things
like HDMI) signals, the other one LCD (so RGB, LVDS, DSI) signals. And
while they are called TCON0 and TCON1 in the A83t datasheet, newer SoCs
call them TCON-TV and TCON-LCD, which seems more appropriate.
However, the mixers differ mostly by their capabilities, with some features
being available only in the first one, or the number of planes they expose,
but also through their register layout. And while the capabilities could be
represented as properties, the register layout differences would need to
express all the registers offsets as properties, which is usually quite
bad. Especially since documentation on that hardware block is close to
non-existent and we don't even have the list of all those registers in the
first place.
So let's call them mixer 0 and 1 in our compatibles, even though the name
is pretty bad...
At the moment, we only have tested the code on a board that has a single
display output, so we're leaving the tcon-tv and mixer1 out.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2702a5c1d224af1c51743492ad1b917966f2ad43.1513854122.git-series.maxime.ripard@free-electrons.com
2017-12-21 04:02:30 -07:00
|
|
|
* allwinner,sun8i-a83t-display-engine
|
2018-03-01 14:34:31 -07:00
|
|
|
* allwinner,sun8i-h3-display-engine
|
2018-07-10 14:34:54 -06:00
|
|
|
* allwinner,sun8i-r40-display-engine
|
2017-05-14 10:30:35 -06:00
|
|
|
* allwinner,sun8i-v3s-display-engine
|
2018-03-15 05:41:32 -06:00
|
|
|
* allwinner,sun9i-a80-display-engine
|
2015-10-30 07:25:05 -06:00
|
|
|
|
|
|
|
- allwinner,pipelines: list of phandle to the display engine
|
2017-05-14 10:30:35 -06:00
|
|
|
frontends (DE 1.0) or mixers (DE 2.0) available.
|
2015-10-30 07:25:05 -06:00
|
|
|
|
|
|
|
Example:
|
|
|
|
|
|
|
|
panel: panel {
|
|
|
|
compatible = "olimex,lcd-olinuxino-43-ts";
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
port {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
panel_input: endpoint {
|
|
|
|
remote-endpoint = <&tcon0_out_panel>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2017-05-27 10:09:33 -06:00
|
|
|
connector {
|
|
|
|
compatible = "hdmi-connector";
|
|
|
|
type = "a";
|
|
|
|
|
|
|
|
port {
|
|
|
|
hdmi_con_in: endpoint {
|
|
|
|
remote-endpoint = <&hdmi_out_con>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2017-11-08 09:27:48 -07:00
|
|
|
hdmi: hdmi@1c16000 {
|
2017-05-27 10:09:33 -06:00
|
|
|
compatible = "allwinner,sun5i-a10s-hdmi";
|
|
|
|
reg = <0x01c16000 0x1000>;
|
|
|
|
interrupts = <58>;
|
|
|
|
clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
|
|
|
|
<&ccu CLK_PLL_VIDEO0_2X>,
|
|
|
|
<&ccu CLK_PLL_VIDEO1_2X>;
|
|
|
|
clock-names = "ahb", "mod", "pll-0", "pll-1";
|
|
|
|
dmas = <&dma SUN4I_DMA_NORMAL 16>,
|
|
|
|
<&dma SUN4I_DMA_NORMAL 16>,
|
|
|
|
<&dma SUN4I_DMA_DEDICATED 24>;
|
|
|
|
dma-names = "ddc-tx", "ddc-rx", "audio-tx";
|
|
|
|
|
|
|
|
ports {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
port@0 {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <0>;
|
|
|
|
|
|
|
|
hdmi_in_tcon0: endpoint {
|
|
|
|
remote-endpoint = <&tcon0_out_hdmi>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
port@1 {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <1>;
|
|
|
|
|
|
|
|
hdmi_out_con: endpoint {
|
|
|
|
remote-endpoint = <&hdmi_con_in>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2017-11-08 09:27:48 -07:00
|
|
|
tve0: tv-encoder@1c0a000 {
|
2015-10-30 07:25:05 -06:00
|
|
|
compatible = "allwinner,sun4i-a10-tv-encoder";
|
|
|
|
reg = <0x01c0a000 0x1000>;
|
|
|
|
clocks = <&ahb_gates 34>;
|
|
|
|
resets = <&tcon_ch0_clk 0>;
|
|
|
|
|
|
|
|
port {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
tve0_in_tcon0: endpoint@0 {
|
|
|
|
reg = <0>;
|
|
|
|
remote-endpoint = <&tcon0_out_tve0>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
tcon0: lcd-controller@1c0c000 {
|
|
|
|
compatible = "allwinner,sun5i-a13-tcon";
|
|
|
|
reg = <0x01c0c000 0x1000>;
|
|
|
|
interrupts = <44>;
|
|
|
|
resets = <&tcon_ch0_clk 1>;
|
|
|
|
reset-names = "lcd";
|
|
|
|
clocks = <&ahb_gates 36>,
|
|
|
|
<&tcon_ch0_clk>,
|
|
|
|
<&tcon_ch1_clk>;
|
|
|
|
clock-names = "ahb",
|
|
|
|
"tcon-ch0",
|
|
|
|
"tcon-ch1";
|
|
|
|
clock-output-names = "tcon-pixel-clock";
|
|
|
|
|
|
|
|
ports {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
tcon0_in: port@0 {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <0>;
|
|
|
|
|
|
|
|
tcon0_in_be0: endpoint@0 {
|
|
|
|
reg = <0>;
|
|
|
|
remote-endpoint = <&be0_out_tcon0>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
tcon0_out: port@1 {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <1>;
|
|
|
|
|
|
|
|
tcon0_out_panel: endpoint@0 {
|
|
|
|
reg = <0>;
|
|
|
|
remote-endpoint = <&panel_input>;
|
|
|
|
};
|
|
|
|
|
|
|
|
tcon0_out_tve0: endpoint@1 {
|
|
|
|
reg = <1>;
|
|
|
|
remote-endpoint = <&tve0_in_tcon0>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
fe0: display-frontend@1e00000 {
|
|
|
|
compatible = "allwinner,sun5i-a13-display-frontend";
|
|
|
|
reg = <0x01e00000 0x20000>;
|
|
|
|
interrupts = <47>;
|
|
|
|
clocks = <&ahb_gates 46>, <&de_fe_clk>,
|
|
|
|
<&dram_gates 25>;
|
|
|
|
clock-names = "ahb", "mod",
|
|
|
|
"ram";
|
|
|
|
resets = <&de_fe_clk>;
|
|
|
|
|
|
|
|
ports {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
fe0_out: port@1 {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <1>;
|
|
|
|
|
|
|
|
fe0_out_be0: endpoint {
|
|
|
|
remote-endpoint = <&be0_in_fe0>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
be0: display-backend@1e60000 {
|
|
|
|
compatible = "allwinner,sun5i-a13-display-backend";
|
|
|
|
reg = <0x01e60000 0x10000>;
|
2017-03-27 08:38:46 -06:00
|
|
|
interrupts = <47>;
|
2015-10-30 07:25:05 -06:00
|
|
|
clocks = <&ahb_gates 44>, <&de_be_clk>,
|
|
|
|
<&dram_gates 26>;
|
|
|
|
clock-names = "ahb", "mod",
|
|
|
|
"ram";
|
|
|
|
resets = <&de_be_clk>;
|
|
|
|
|
|
|
|
ports {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
be0_in: port@0 {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <0>;
|
|
|
|
|
|
|
|
be0_in_fe0: endpoint@0 {
|
|
|
|
reg = <0>;
|
|
|
|
remote-endpoint = <&fe0_out_be0>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
be0_out: port@1 {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <1>;
|
|
|
|
|
|
|
|
be0_out_tcon0: endpoint@0 {
|
|
|
|
reg = <0>;
|
|
|
|
remote-endpoint = <&tcon0_in_be0>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
display-engine {
|
|
|
|
compatible = "allwinner,sun5i-a13-display-engine";
|
|
|
|
allwinner,pipelines = <&fe0>;
|
|
|
|
};
|