2019-05-19 07:51:31 -06:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2013-03-22 08:34:03 -06:00
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/*
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* Copyright (c) 2009-2013, NVIDIA Corporation. All rights reserved.
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*/
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#ifndef __LINUX_HOST1X_H
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#define __LINUX_HOST1X_H
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2013-10-14 06:43:22 -06:00
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#include <linux/device.h>
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2013-09-24 08:30:32 -06:00
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#include <linux/types.h>
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2013-03-22 08:34:03 -06:00
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enum host1x_class {
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2013-09-24 05:59:01 -06:00
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HOST1X_CLASS_HOST1X = 0x1,
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HOST1X_CLASS_GR2D = 0x51,
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HOST1X_CLASS_GR2D_SB = 0x52,
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2016-12-14 04:16:13 -07:00
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HOST1X_CLASS_VIC = 0x5D,
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2013-02-28 00:08:01 -07:00
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HOST1X_CLASS_GR3D = 0x60,
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2013-03-22 08:34:03 -06:00
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};
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2020-03-25 14:16:03 -06:00
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struct host1x;
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2013-09-24 07:35:40 -06:00
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struct host1x_client;
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2019-02-08 06:35:13 -07:00
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struct iommu_group;
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2013-09-24 07:35:40 -06:00
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2020-03-25 14:16:03 -06:00
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u64 host1x_get_dma_mask(struct host1x *host1x);
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2017-04-10 04:27:01 -06:00
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/**
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* struct host1x_client_ops - host1x client operations
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* @init: host1x client initialization code
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* @exit: host1x client tear down code
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2019-12-02 07:29:03 -07:00
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* @suspend: host1x client suspend code
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* @resume: host1x client resume code
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2017-04-10 04:27:01 -06:00
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*/
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2013-09-24 07:35:40 -06:00
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struct host1x_client_ops {
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int (*init)(struct host1x_client *client);
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int (*exit)(struct host1x_client *client);
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2019-12-02 07:29:03 -07:00
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int (*suspend)(struct host1x_client *client);
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int (*resume)(struct host1x_client *client);
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2013-09-24 07:35:40 -06:00
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};
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2017-04-10 04:27:01 -06:00
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/**
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* struct host1x_client - host1x client structure
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* @list: list node for the host1x client
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2019-12-02 02:51:58 -07:00
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* @host: pointer to struct device representing the host1x controller
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2017-04-10 04:27:01 -06:00
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* @dev: pointer to struct device backing this host1x client
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2019-02-08 06:35:13 -07:00
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* @group: IOMMU group that this client is a member of
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2017-04-10 04:27:01 -06:00
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* @ops: host1x client operations
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* @class: host1x class represented by this client
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* @channel: host1x channel associated with this client
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* @syncpts: array of syncpoints requested for this client
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* @num_syncpts: number of syncpoints requested for this client
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2020-06-13 22:08:04 -06:00
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* @parent: pointer to parent structure
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* @usecount: reference count for this structure
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* @lock: mutex for mutually exclusive concurrency
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2017-04-10 04:27:01 -06:00
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*/
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2013-09-24 07:35:40 -06:00
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struct host1x_client {
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struct list_head list;
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2019-12-02 02:51:58 -07:00
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struct device *host;
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2013-09-24 07:35:40 -06:00
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struct device *dev;
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2019-02-08 06:35:13 -07:00
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struct iommu_group *group;
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2013-09-24 07:35:40 -06:00
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const struct host1x_client_ops *ops;
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enum host1x_class class;
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struct host1x_channel *channel;
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struct host1x_syncpt **syncpts;
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unsigned int num_syncpts;
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2019-12-02 07:29:03 -07:00
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struct host1x_client *parent;
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unsigned int usecount;
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struct mutex lock;
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2013-09-24 07:35:40 -06:00
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};
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2013-09-24 08:30:32 -06:00
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/*
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* host1x buffer objects
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*/
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struct host1x_bo;
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struct sg_table;
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struct host1x_bo_ops {
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struct host1x_bo *(*get)(struct host1x_bo *bo);
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void (*put)(struct host1x_bo *bo);
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gpu: host1x: Overhaul host1x_bo_{pin,unpin}() API
The host1x_bo_pin() and host1x_bo_unpin() APIs are used to pin and unpin
buffers during host1x job submission. Pinning currently returns the SG
table and the DMA address (an IOVA if an IOMMU is used or a physical
address if no IOMMU is used) of the buffer. The DMA address is only used
for buffers that are relocated, whereas the host1x driver will map
gather buffers into its own IOVA space so that they can be processed by
the CDMA engine.
This approach has a couple of issues. On one hand it's not very useful
to return a DMA address for the buffer if host1x doesn't need it. On the
other hand, returning the SG table of the buffer is suboptimal because a
single SG table cannot be shared for multiple mappings, because the DMA
address is stored within the SG table, and the DMA address may be
different for different devices.
Subsequent patches will move the host1x driver over to the DMA API which
doesn't work with a single shared SG table. Fix this by returning a new
SG table each time a buffer is pinned. This allows the buffer to be
referenced by multiple jobs for different engines.
Change the prototypes of host1x_bo_pin() and host1x_bo_unpin() to take a
struct device *, specifying the device for which the buffer should be
pinned. This is required in order to be able to properly construct the
SG table. While at it, make host1x_bo_pin() return the SG table because
that allows us to return an ERR_PTR()-encoded error code if we need to,
or return NULL to signal that we don't need the SG table to be remapped
and can simply use the DMA address as-is. At the same time, returning
the DMA address is made optional because in the example of command
buffers, host1x doesn't need to know the DMA address since it will have
to create its own mapping anyway.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 06:37:09 -06:00
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struct sg_table *(*pin)(struct device *dev, struct host1x_bo *bo,
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dma_addr_t *phys);
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void (*unpin)(struct device *dev, struct sg_table *sgt);
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2013-09-24 08:30:32 -06:00
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void *(*mmap)(struct host1x_bo *bo);
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void (*munmap)(struct host1x_bo *bo, void *addr);
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};
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struct host1x_bo {
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const struct host1x_bo_ops *ops;
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};
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static inline void host1x_bo_init(struct host1x_bo *bo,
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const struct host1x_bo_ops *ops)
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{
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bo->ops = ops;
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}
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static inline struct host1x_bo *host1x_bo_get(struct host1x_bo *bo)
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{
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return bo->ops->get(bo);
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}
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static inline void host1x_bo_put(struct host1x_bo *bo)
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{
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bo->ops->put(bo);
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}
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gpu: host1x: Overhaul host1x_bo_{pin,unpin}() API
The host1x_bo_pin() and host1x_bo_unpin() APIs are used to pin and unpin
buffers during host1x job submission. Pinning currently returns the SG
table and the DMA address (an IOVA if an IOMMU is used or a physical
address if no IOMMU is used) of the buffer. The DMA address is only used
for buffers that are relocated, whereas the host1x driver will map
gather buffers into its own IOVA space so that they can be processed by
the CDMA engine.
This approach has a couple of issues. On one hand it's not very useful
to return a DMA address for the buffer if host1x doesn't need it. On the
other hand, returning the SG table of the buffer is suboptimal because a
single SG table cannot be shared for multiple mappings, because the DMA
address is stored within the SG table, and the DMA address may be
different for different devices.
Subsequent patches will move the host1x driver over to the DMA API which
doesn't work with a single shared SG table. Fix this by returning a new
SG table each time a buffer is pinned. This allows the buffer to be
referenced by multiple jobs for different engines.
Change the prototypes of host1x_bo_pin() and host1x_bo_unpin() to take a
struct device *, specifying the device for which the buffer should be
pinned. This is required in order to be able to properly construct the
SG table. While at it, make host1x_bo_pin() return the SG table because
that allows us to return an ERR_PTR()-encoded error code if we need to,
or return NULL to signal that we don't need the SG table to be remapped
and can simply use the DMA address as-is. At the same time, returning
the DMA address is made optional because in the example of command
buffers, host1x doesn't need to know the DMA address since it will have
to create its own mapping anyway.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 06:37:09 -06:00
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static inline struct sg_table *host1x_bo_pin(struct device *dev,
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struct host1x_bo *bo,
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dma_addr_t *phys)
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2013-09-24 08:30:32 -06:00
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{
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gpu: host1x: Overhaul host1x_bo_{pin,unpin}() API
The host1x_bo_pin() and host1x_bo_unpin() APIs are used to pin and unpin
buffers during host1x job submission. Pinning currently returns the SG
table and the DMA address (an IOVA if an IOMMU is used or a physical
address if no IOMMU is used) of the buffer. The DMA address is only used
for buffers that are relocated, whereas the host1x driver will map
gather buffers into its own IOVA space so that they can be processed by
the CDMA engine.
This approach has a couple of issues. On one hand it's not very useful
to return a DMA address for the buffer if host1x doesn't need it. On the
other hand, returning the SG table of the buffer is suboptimal because a
single SG table cannot be shared for multiple mappings, because the DMA
address is stored within the SG table, and the DMA address may be
different for different devices.
Subsequent patches will move the host1x driver over to the DMA API which
doesn't work with a single shared SG table. Fix this by returning a new
SG table each time a buffer is pinned. This allows the buffer to be
referenced by multiple jobs for different engines.
Change the prototypes of host1x_bo_pin() and host1x_bo_unpin() to take a
struct device *, specifying the device for which the buffer should be
pinned. This is required in order to be able to properly construct the
SG table. While at it, make host1x_bo_pin() return the SG table because
that allows us to return an ERR_PTR()-encoded error code if we need to,
or return NULL to signal that we don't need the SG table to be remapped
and can simply use the DMA address as-is. At the same time, returning
the DMA address is made optional because in the example of command
buffers, host1x doesn't need to know the DMA address since it will have
to create its own mapping anyway.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 06:37:09 -06:00
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return bo->ops->pin(dev, bo, phys);
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2013-09-24 08:30:32 -06:00
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}
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gpu: host1x: Overhaul host1x_bo_{pin,unpin}() API
The host1x_bo_pin() and host1x_bo_unpin() APIs are used to pin and unpin
buffers during host1x job submission. Pinning currently returns the SG
table and the DMA address (an IOVA if an IOMMU is used or a physical
address if no IOMMU is used) of the buffer. The DMA address is only used
for buffers that are relocated, whereas the host1x driver will map
gather buffers into its own IOVA space so that they can be processed by
the CDMA engine.
This approach has a couple of issues. On one hand it's not very useful
to return a DMA address for the buffer if host1x doesn't need it. On the
other hand, returning the SG table of the buffer is suboptimal because a
single SG table cannot be shared for multiple mappings, because the DMA
address is stored within the SG table, and the DMA address may be
different for different devices.
Subsequent patches will move the host1x driver over to the DMA API which
doesn't work with a single shared SG table. Fix this by returning a new
SG table each time a buffer is pinned. This allows the buffer to be
referenced by multiple jobs for different engines.
Change the prototypes of host1x_bo_pin() and host1x_bo_unpin() to take a
struct device *, specifying the device for which the buffer should be
pinned. This is required in order to be able to properly construct the
SG table. While at it, make host1x_bo_pin() return the SG table because
that allows us to return an ERR_PTR()-encoded error code if we need to,
or return NULL to signal that we don't need the SG table to be remapped
and can simply use the DMA address as-is. At the same time, returning
the DMA address is made optional because in the example of command
buffers, host1x doesn't need to know the DMA address since it will have
to create its own mapping anyway.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 06:37:09 -06:00
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static inline void host1x_bo_unpin(struct device *dev, struct host1x_bo *bo,
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struct sg_table *sgt)
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2013-09-24 08:30:32 -06:00
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{
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gpu: host1x: Overhaul host1x_bo_{pin,unpin}() API
The host1x_bo_pin() and host1x_bo_unpin() APIs are used to pin and unpin
buffers during host1x job submission. Pinning currently returns the SG
table and the DMA address (an IOVA if an IOMMU is used or a physical
address if no IOMMU is used) of the buffer. The DMA address is only used
for buffers that are relocated, whereas the host1x driver will map
gather buffers into its own IOVA space so that they can be processed by
the CDMA engine.
This approach has a couple of issues. On one hand it's not very useful
to return a DMA address for the buffer if host1x doesn't need it. On the
other hand, returning the SG table of the buffer is suboptimal because a
single SG table cannot be shared for multiple mappings, because the DMA
address is stored within the SG table, and the DMA address may be
different for different devices.
Subsequent patches will move the host1x driver over to the DMA API which
doesn't work with a single shared SG table. Fix this by returning a new
SG table each time a buffer is pinned. This allows the buffer to be
referenced by multiple jobs for different engines.
Change the prototypes of host1x_bo_pin() and host1x_bo_unpin() to take a
struct device *, specifying the device for which the buffer should be
pinned. This is required in order to be able to properly construct the
SG table. While at it, make host1x_bo_pin() return the SG table because
that allows us to return an ERR_PTR()-encoded error code if we need to,
or return NULL to signal that we don't need the SG table to be remapped
and can simply use the DMA address as-is. At the same time, returning
the DMA address is made optional because in the example of command
buffers, host1x doesn't need to know the DMA address since it will have
to create its own mapping anyway.
Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 06:37:09 -06:00
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bo->ops->unpin(dev, sgt);
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2013-09-24 08:30:32 -06:00
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}
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static inline void *host1x_bo_mmap(struct host1x_bo *bo)
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{
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return bo->ops->mmap(bo);
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}
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static inline void host1x_bo_munmap(struct host1x_bo *bo, void *addr)
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{
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bo->ops->munmap(bo, addr);
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}
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/*
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* host1x syncpoints
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*/
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2013-10-14 06:21:52 -06:00
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#define HOST1X_SYNCPT_CLIENT_MANAGED (1 << 0)
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2013-10-14 06:21:53 -06:00
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#define HOST1X_SYNCPT_HAS_BASE (1 << 1)
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2013-10-14 06:21:52 -06:00
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2013-10-14 06:21:53 -06:00
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struct host1x_syncpt_base;
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2013-09-24 08:30:32 -06:00
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struct host1x_syncpt;
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struct host1x;
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struct host1x_syncpt *host1x_syncpt_get(struct host1x *host, u32 id);
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u32 host1x_syncpt_id(struct host1x_syncpt *sp);
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u32 host1x_syncpt_read_min(struct host1x_syncpt *sp);
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u32 host1x_syncpt_read_max(struct host1x_syncpt *sp);
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2015-01-28 06:29:02 -07:00
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u32 host1x_syncpt_read(struct host1x_syncpt *sp);
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2013-09-24 08:30:32 -06:00
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int host1x_syncpt_incr(struct host1x_syncpt *sp);
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2014-02-19 15:48:36 -07:00
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u32 host1x_syncpt_incr_max(struct host1x_syncpt *sp, u32 incrs);
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2013-09-24 08:30:32 -06:00
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int host1x_syncpt_wait(struct host1x_syncpt *sp, u32 thresh, long timeout,
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u32 *value);
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2017-08-30 04:48:31 -06:00
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struct host1x_syncpt *host1x_syncpt_request(struct host1x_client *client,
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2013-10-14 06:21:52 -06:00
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unsigned long flags);
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2013-09-24 08:30:32 -06:00
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void host1x_syncpt_free(struct host1x_syncpt *sp);
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2013-10-14 06:21:53 -06:00
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struct host1x_syncpt_base *host1x_syncpt_get_base(struct host1x_syncpt *sp);
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u32 host1x_syncpt_base_id(struct host1x_syncpt_base *base);
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2013-09-24 08:30:32 -06:00
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/*
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* host1x channel
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*/
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struct host1x_channel;
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struct host1x_job;
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2018-06-18 06:01:51 -06:00
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struct host1x_channel *host1x_channel_request(struct host1x_client *client);
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2013-09-24 08:30:32 -06:00
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struct host1x_channel *host1x_channel_get(struct host1x_channel *channel);
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void host1x_channel_put(struct host1x_channel *channel);
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int host1x_job_submit(struct host1x_job *job);
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/*
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* host1x job
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*/
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2019-10-28 06:37:11 -06:00
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#define HOST1X_RELOC_READ (1 << 0)
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#define HOST1X_RELOC_WRITE (1 << 1)
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2013-09-24 08:30:32 -06:00
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struct host1x_reloc {
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2014-06-10 02:25:00 -06:00
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struct {
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struct host1x_bo *bo;
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unsigned long offset;
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} cmdbuf;
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struct {
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struct host1x_bo *bo;
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unsigned long offset;
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} target;
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unsigned long shift;
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2019-10-28 06:37:11 -06:00
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|
|
unsigned long flags;
|
2013-09-24 08:30:32 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct host1x_job {
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|
|
|
|
/* When refcount goes to zero, job can be freed */
|
|
|
|
|
struct kref ref;
|
|
|
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|
|
|
|
/* List entry */
|
|
|
|
|
struct list_head list;
|
|
|
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|
|
|
/* Channel where job is submitted to */
|
|
|
|
|
struct host1x_channel *channel;
|
|
|
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|
|
2018-05-16 06:12:33 -06:00
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|
|
/* client where the job originated */
|
|
|
|
|
struct host1x_client *client;
|
2013-09-24 08:30:32 -06:00
|
|
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|
|
|
|
|
/* Gathers and their memory */
|
|
|
|
|
struct host1x_job_gather *gathers;
|
|
|
|
|
unsigned int num_gathers;
|
|
|
|
|
|
|
|
|
|
/* Array of handles to be pinned & unpinned */
|
2018-05-16 08:58:44 -06:00
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|
|
struct host1x_reloc *relocs;
|
2013-09-24 08:30:32 -06:00
|
|
|
unsigned int num_relocs;
|
|
|
|
|
struct host1x_job_unpin_data *unpins;
|
|
|
|
|
unsigned int num_unpins;
|
|
|
|
|
|
|
|
|
|
dma_addr_t *addr_phys;
|
|
|
|
|
dma_addr_t *gather_addr_phys;
|
|
|
|
|
dma_addr_t *reloc_addr_phys;
|
|
|
|
|
|
|
|
|
|
/* Sync point id, number of increments and end related to the submit */
|
|
|
|
|
u32 syncpt_id;
|
|
|
|
|
u32 syncpt_incrs;
|
|
|
|
|
u32 syncpt_end;
|
|
|
|
|
|
|
|
|
|
/* Maximum time to wait for this job */
|
|
|
|
|
unsigned int timeout;
|
|
|
|
|
|
|
|
|
|
/* Index and number of slots used in the push buffer */
|
|
|
|
|
unsigned int first_get;
|
|
|
|
|
unsigned int num_slots;
|
|
|
|
|
|
|
|
|
|
/* Copy of gathers */
|
|
|
|
|
size_t gather_copy_size;
|
|
|
|
|
dma_addr_t gather_copy;
|
|
|
|
|
u8 *gather_copy_mapped;
|
|
|
|
|
|
|
|
|
|
/* Check if register is marked as an address reg */
|
2017-06-14 17:18:38 -06:00
|
|
|
int (*is_addr_reg)(struct device *dev, u32 class, u32 reg);
|
2013-09-24 08:30:32 -06:00
|
|
|
|
2017-06-14 17:18:37 -06:00
|
|
|
/* Check if class belongs to the unit */
|
|
|
|
|
int (*is_valid_class)(u32 class);
|
|
|
|
|
|
2013-09-24 08:30:32 -06:00
|
|
|
/* Request a SETCLASS to this class */
|
|
|
|
|
u32 class;
|
|
|
|
|
|
|
|
|
|
/* Add a channel wait for previous ops to complete */
|
|
|
|
|
bool serialize;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct host1x_job *host1x_job_alloc(struct host1x_channel *ch,
|
2018-05-05 00:45:47 -06:00
|
|
|
u32 num_cmdbufs, u32 num_relocs);
|
2018-05-16 09:01:43 -06:00
|
|
|
void host1x_job_add_gather(struct host1x_job *job, struct host1x_bo *bo,
|
|
|
|
|
unsigned int words, unsigned int offset);
|
2013-09-24 08:30:32 -06:00
|
|
|
struct host1x_job *host1x_job_get(struct host1x_job *job);
|
|
|
|
|
void host1x_job_put(struct host1x_job *job);
|
|
|
|
|
int host1x_job_pin(struct host1x_job *job, struct device *dev);
|
|
|
|
|
void host1x_job_unpin(struct host1x_job *job);
|
|
|
|
|
|
2013-10-14 06:43:22 -06:00
|
|
|
/*
|
|
|
|
|
* subdevice probe infrastructure
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
struct host1x_device;
|
|
|
|
|
|
2017-04-10 04:27:01 -06:00
|
|
|
/**
|
|
|
|
|
* struct host1x_driver - host1x logical device driver
|
|
|
|
|
* @driver: core driver
|
|
|
|
|
* @subdevs: table of OF device IDs matching subdevices for this driver
|
|
|
|
|
* @list: list node for the driver
|
|
|
|
|
* @probe: called when the host1x logical device is probed
|
|
|
|
|
* @remove: called when the host1x logical device is removed
|
|
|
|
|
* @shutdown: called when the host1x logical device is shut down
|
|
|
|
|
*/
|
2013-10-14 06:43:22 -06:00
|
|
|
struct host1x_driver {
|
2014-12-18 07:29:14 -07:00
|
|
|
struct device_driver driver;
|
|
|
|
|
|
2013-10-14 06:43:22 -06:00
|
|
|
const struct of_device_id *subdevs;
|
|
|
|
|
struct list_head list;
|
|
|
|
|
|
|
|
|
|
int (*probe)(struct host1x_device *device);
|
|
|
|
|
int (*remove)(struct host1x_device *device);
|
2014-12-18 07:29:14 -07:00
|
|
|
void (*shutdown)(struct host1x_device *device);
|
2013-10-14 06:43:22 -06:00
|
|
|
};
|
|
|
|
|
|
2014-12-18 07:29:14 -07:00
|
|
|
static inline struct host1x_driver *
|
|
|
|
|
to_host1x_driver(struct device_driver *driver)
|
|
|
|
|
{
|
|
|
|
|
return container_of(driver, struct host1x_driver, driver);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int host1x_driver_register_full(struct host1x_driver *driver,
|
|
|
|
|
struct module *owner);
|
2013-10-14 06:43:22 -06:00
|
|
|
void host1x_driver_unregister(struct host1x_driver *driver);
|
|
|
|
|
|
2014-12-18 07:29:14 -07:00
|
|
|
#define host1x_driver_register(driver) \
|
|
|
|
|
host1x_driver_register_full(driver, THIS_MODULE)
|
|
|
|
|
|
2013-10-14 06:43:22 -06:00
|
|
|
struct host1x_device {
|
|
|
|
|
struct host1x_driver *driver;
|
|
|
|
|
struct list_head list;
|
|
|
|
|
struct device dev;
|
|
|
|
|
|
|
|
|
|
struct mutex subdevs_lock;
|
|
|
|
|
struct list_head subdevs;
|
|
|
|
|
struct list_head active;
|
|
|
|
|
|
|
|
|
|
struct mutex clients_lock;
|
|
|
|
|
struct list_head clients;
|
2014-11-05 03:43:26 -07:00
|
|
|
|
2014-12-18 07:29:14 -07:00
|
|
|
bool registered;
|
2019-06-05 02:46:05 -06:00
|
|
|
|
|
|
|
|
struct device_dma_parameters dma_parms;
|
2013-10-14 06:43:22 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static inline struct host1x_device *to_host1x_device(struct device *dev)
|
|
|
|
|
{
|
|
|
|
|
return container_of(dev, struct host1x_device, dev);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int host1x_device_init(struct host1x_device *device);
|
|
|
|
|
int host1x_device_exit(struct host1x_device *device);
|
|
|
|
|
|
|
|
|
|
int host1x_client_register(struct host1x_client *client);
|
|
|
|
|
int host1x_client_unregister(struct host1x_client *client);
|
|
|
|
|
|
2019-12-02 07:29:03 -07:00
|
|
|
int host1x_client_suspend(struct host1x_client *client);
|
|
|
|
|
int host1x_client_resume(struct host1x_client *client);
|
|
|
|
|
|
2013-09-02 01:48:53 -06:00
|
|
|
struct tegra_mipi_device;
|
|
|
|
|
|
|
|
|
|
struct tegra_mipi_device *tegra_mipi_request(struct device *device);
|
|
|
|
|
void tegra_mipi_free(struct tegra_mipi_device *device);
|
2016-08-12 08:00:53 -06:00
|
|
|
int tegra_mipi_enable(struct tegra_mipi_device *device);
|
|
|
|
|
int tegra_mipi_disable(struct tegra_mipi_device *device);
|
2013-09-02 01:48:53 -06:00
|
|
|
int tegra_mipi_calibrate(struct tegra_mipi_device *device);
|
|
|
|
|
|
2013-03-22 08:34:03 -06:00
|
|
|
#endif
|