2014-09-17 05:08:30 -06:00
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=============================================================================
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Freescale Frame Manager Device Bindings
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CONTENTS
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- FMan Node
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- FMan Port Node
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- FMan MURAM Node
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- FMan dTSEC/XGEC/mEMAC Node
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- FMan IEEE 1588 Node
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2015-01-28 04:54:24 -07:00
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- FMan MDIO Node
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2014-09-17 05:08:30 -06:00
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- Example
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=============================================================================
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FMan Node
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DESCRIPTION
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Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
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etc.) the FMan node will have child nodes for each of them.
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PROPERTIES
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- compatible
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Usage: required
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Value type: <stringlist>
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Definition: Must include "fsl,fman"
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FMan version can be determined via FM_IP_REV_1 register in the
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FMan block. The offset is 0xc4 from the beginning of the
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Frame Processing Manager memory map (0xc3000 from the
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beginning of the FMan node).
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- cell-index
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Usage: required
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Value type: <u32>
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Definition: Specifies the index of the FMan unit.
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The cell-index value may be used by the SoC, to identify the
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2016-07-13 12:08:07 -06:00
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FMan unit in the SoC memory map. In the table below,
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2014-09-17 05:08:30 -06:00
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there's a description of the cell-index use in each SoC:
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- P1023:
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register[bit] FMan unit cell-index
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============================================================
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DEVDISR[1] 1 0
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- P2041, P3041, P4080 P5020, P5040:
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register[bit] FMan unit cell-index
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============================================================
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DCFG_DEVDISR2[6] 1 0
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DCFG_DEVDISR2[14] 2 1
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(Second FM available only in P4080 and P5040)
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- B4860, T1040, T2080, T4240:
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register[bit] FMan unit cell-index
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============================================================
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DCFG_CCSR_DEVDISR2[24] 1 0
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DCFG_CCSR_DEVDISR2[25] 2 1
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(Second FM available only in T4240)
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DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
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the specific SoC "Device Configuration/Pin Control" Memory
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Map.
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property. Specifies the offset of the
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following configuration registers:
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- BMI configuration registers.
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- QMI configuration registers.
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- DMA configuration registers.
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- FPM configuration registers.
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- FMan controller configuration registers.
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- ranges
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property.
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- clocks
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Usage: required
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Value type: <prop-encoded-array>
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2014-11-06 19:56:07 -07:00
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Definition: phandle for the fman input clock.
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2014-09-17 05:08:30 -06:00
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- clock-names
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2014-11-06 19:56:07 -07:00
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usage: required
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2014-09-17 05:08:30 -06:00
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Value type: <stringlist>
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2014-11-06 19:56:07 -07:00
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Definition: "fmanclk" for the fman input clock.
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2014-09-17 05:08:30 -06:00
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- interrupts
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A pair of IRQs are specified in this property.
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The first element is associated with the event interrupts and
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the second element is associated with the error interrupts.
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- fsl,qman-channel-range
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Usage: required
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Value type: <prop-encoded-array>
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Definition: Specifies the range of the available dedicated
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channels in the FMan. The first cell specifies the beginning
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of the range and the second cell specifies the number of
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channels.
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Further information available at:
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"Work Queue (WQ) Channel Assignments in the QMan" section
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in DPAA Reference Manual.
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2014-11-06 19:56:07 -07:00
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- fsl,qman
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- fsl,bman
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Usage: required
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Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt
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dt-bindings: net: FMan erratum A050385
[ Upstream commit 26d5bb9e4c4b541c475751e015072eb2cbf70d15 ]
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak; thus stopping further packet processing.
The FMAN internal queue can overflow when FMAN splits single
read or write transactions into multiple smaller transactions
such that more than 17 AXI transactions are in flight from FMAN
to interconnect. When the FMAN internal queue overflows, it can
stall further packet processing. The issue can occur with any one
of the following three conditions:
1. FMAN AXI transaction crosses 4K address boundary (Errata
A010022)
2. FMAN DMA address for an AXI transaction is not 16 byte
aligned, i.e. the last 4 bits of an address are non-zero
3. Scatter Gather (SG) frames have more than one SG buffer in
the SG list and any one of the buffers, except the last
buffer in the SG list has data size that is not a multiple
of 16 bytes, i.e., other than 16, 32, 48, 64, etc.
With any one of the above three conditions present, there is
likelihood of stalled FMAN packet processing, especially under
stress with multiple ports injecting line-rate traffic.
To avoid situations that stall FMAN packet processing, all of the
above three conditions must be avoided; therefore, configure the
system with the following rules:
1. Frame buffers must not span a 4KB address boundary, unless
the frame start address is 256 byte aligned
2. All FMAN DMA start addresses (for example, BMAN buffer
address, FD[address] + FD[offset]) are 16B aligned
3. SG table and buffer addresses are 16B aligned and the size
of SG buffers are multiple of 16 bytes, except for the last
SG buffer that can be of any size.
Additional workaround notes:
- Address alignment of 64 bytes is recommended for maximally
efficient system bus transactions (although 16 byte alignment is
sufficient to avoid the stall condition)
- To support frame sizes that are larger than 4K bytes, there are
two options:
1. Large single buffer frames that span a 4KB page boundary can
be converted into SG frames to avoid transaction splits at
the 4KB boundary,
2. Align the large single buffer to 256B address boundaries,
ensure that the frame address plus offset is 256B aligned.
- If software generated SG frames have buffers that are unaligned
and with random non-multiple of 16 byte lengths, before
transmitting such frames via FMAN, frames will need to be copied
into a new single buffer or multiple buffer SG frame that is
compliant with the three rules listed above.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-03-04 09:04:25 -07:00
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- fsl,erratum-a050385
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Usage: optional
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Value type: boolean
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Definition: A boolean property. Indicates the presence of the
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erratum A050385 which indicates that DMA transactions that are
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split can result in a FMan lock.
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2014-09-17 05:08:30 -06:00
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=============================================================================
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FMan MURAM Node
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DESCRIPTION
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FMan Internal memory - shared between all the FMan modules.
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It contains data structures that are common and written to or read by
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the modules.
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FMan internal memory is split into the following parts:
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Packet buffering (Tx/Rx FIFOs)
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Frames internal context
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PROPERTIES
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- compatible
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Usage: required
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Value type: <stringlist>
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Definition: Must include "fsl,fman-muram"
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- ranges
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Usage: required
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Value type: <prop-encoded-array>
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Definition: A standard property.
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Specifies the multi-user memory offset and the size within
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the FMan.
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EXAMPLE
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muram@0 {
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compatible = "fsl,fman-muram";
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ranges = <0 0x000000 0x28000>;
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};
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=============================================================================
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FMan Port Node
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DESCRIPTION
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The Frame Manager (FMan) supports several types of hardware ports:
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Ethernet receiver (RX)
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Ethernet transmitter (TX)
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Offline/Host command (O/H)
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PROPERTIES
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- compatible
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Usage: required
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Value type: <stringlist>
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Definition: A standard property.
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Must include one of the following:
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- "fsl,fman-v2-port-oh" for FManV2 OH ports
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- "fsl,fman-v2-port-rx" for FManV2 RX ports
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- "fsl,fman-v2-port-tx" for FManV2 TX ports
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- "fsl,fman-v3-port-oh" for FManV3 OH ports
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- "fsl,fman-v3-port-rx" for FManV3 RX ports
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- "fsl,fman-v3-port-tx" for FManV3 TX ports
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- cell-index
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Usage: required
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Value type: <u32>
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Definition: Specifies the hardware port id.
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Each hardware port on the FMan has its own hardware PortID.
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Super set of all hardware Port IDs available at FMan Reference
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Manual under "FMan Hardware Ports in Freescale Devices" table.
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Each hardware port is assigned a 4KB, port-specific page in
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the FMan hardware port memory region (which is part of the
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FMan memory map). The first 4 KB in the FMan hardware ports
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memory region is used for what are called common registers.
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The subsequent 63 4KB pages are allocated to the hardware
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ports.
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The page of a specific port is determined by the cell-index.
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: There is one reg region describing the port
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configuration registers.
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2015-06-01 06:06:51 -06:00
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- fsl,fman-10g-port
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Usage: optional
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Value type: boolean
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Definition: The default port rate is 1G.
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If this property exists, the port is s 10G port.
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- fsl,fman-best-effort-port
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Usage: optional
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Value type: boolean
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Definition: Can be defined only if 10G-support is set.
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This property marks a best-effort 10G port (10G port that
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may not be capable of line rate).
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2014-09-17 05:08:30 -06:00
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EXAMPLE
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port@a8000 {
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cell-index = <0x28>;
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compatible = "fsl,fman-v2-port-tx";
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reg = <0xa8000 0x1000>;
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};
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port@88000 {
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cell-index = <0x8>;
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compatible = "fsl,fman-v2-port-rx";
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reg = <0x88000 0x1000>;
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};
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port@81000 {
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cell-index = <0x1>;
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compatible = "fsl,fman-v2-port-oh";
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reg = <0x81000 0x1000>;
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};
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=============================================================================
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FMan dTSEC/XGEC/mEMAC Node
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DESCRIPTION
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mEMAC/dTSEC/XGEC are the Ethernet network interfaces
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PROPERTIES
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- compatible
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Usage: required
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Value type: <stringlist>
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Definition: A standard property.
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Must include one of the following:
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- "fsl,fman-dtsec" for dTSEC MAC
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- "fsl,fman-xgec" for XGEC MAC
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- "fsl,fman-memac" for mEMAC MAC
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2014-09-17 05:08:30 -06:00
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- cell-index
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Usage: required
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Value type: <u32>
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Definition: Specifies the MAC id.
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The cell-index value may be used by the FMan or the SoC, to
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identify the MAC unit in the FMan (or SoC) memory map.
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In the tables below there's a description of the cell-index
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2014-09-17 05:08:30 -06:00
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use, there are two tables, one describes the use of cell-index
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by the FMan, the second describes the use by the SoC:
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1. FMan Registers
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FManV2:
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register[bit] MAC cell-index
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============================================================
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FM_EPI[16] XGEC 8
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FM_EPI[16+n] dTSECn n-1
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FM_NPI[11+n] dTSECn n-1
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n = 1,..,5
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FManV3:
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register[bit] MAC cell-index
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============================================================
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FM_EPI[16+n] mEMACn n-1
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FM_EPI[25] mEMAC10 9
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FM_NPI[11+n] mEMACn n-1
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FM_NPI[10] mEMAC10 9
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FM_NPI[11] mEMAC9 8
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n = 1,..8
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FM_EPI and FM_NPI are located in the FMan memory map.
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2. SoC registers:
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- P2041, P3041, P4080 P5020, P5040:
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register[bit] FMan MAC cell
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Unit index
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============================================================
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DCFG_DEVDISR2[7] 1 XGEC 8
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DCFG_DEVDISR2[7+n] 1 dTSECn n-1
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DCFG_DEVDISR2[15] 2 XGEC 8
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DCFG_DEVDISR2[15+n] 2 dTSECn n-1
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n = 1,..5
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- T1040, T2080, T4240, B4860:
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register[bit] FMan MAC cell
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Unit index
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============================================================
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DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1
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DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1
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n = 1,..6,9,10
|
|
|
|
|
|
|
|
|
|
EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
|
|
|
|
|
the specific SoC "Device Configuration/Pin Control" Memory
|
|
|
|
|
Map.
|
|
|
|
|
|
|
|
|
|
- reg
|
|
|
|
|
Usage: required
|
|
|
|
|
Value type: <prop-encoded-array>
|
|
|
|
|
Definition: A standard property.
|
|
|
|
|
|
|
|
|
|
- fsl,fman-ports
|
|
|
|
|
Usage: required
|
|
|
|
|
Value type: <prop-encoded-array>
|
|
|
|
|
Definition: An array of two phandles - the first references is
|
|
|
|
|
the FMan RX port and the second is the TX port used by this
|
|
|
|
|
MAC.
|
|
|
|
|
|
|
|
|
|
- ptp-timer
|
|
|
|
|
Usage required
|
|
|
|
|
Value type: <phandle>
|
|
|
|
|
Definition: A phandle for 1EEE1588 timer.
|
|
|
|
|
|
2015-12-23 18:42:11 -07:00
|
|
|
- pcsphy-handle
|
|
|
|
|
Usage required for "fsl,fman-memac" MACs
|
|
|
|
|
Value type: <phandle>
|
|
|
|
|
Definition: A phandle for pcsphy.
|
|
|
|
|
|
|
|
|
|
- tbi-handle
|
|
|
|
|
Usage required for "fsl,fman-dtsec" MACs
|
|
|
|
|
Value type: <phandle>
|
|
|
|
|
Definition: A phandle for tbiphy.
|
|
|
|
|
|
2014-09-17 05:08:30 -06:00
|
|
|
EXAMPLE
|
|
|
|
|
|
|
|
|
|
fman1_tx28: port@a8000 {
|
|
|
|
|
cell-index = <0x28>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-tx";
|
|
|
|
|
reg = <0xa8000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
fman1_rx8: port@88000 {
|
|
|
|
|
cell-index = <0x8>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-rx";
|
|
|
|
|
reg = <0x88000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ptp-timer: ptp_timer@fe000 {
|
|
|
|
|
compatible = "fsl,fman-ptp-timer";
|
|
|
|
|
reg = <0xfe000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ethernet@e0000 {
|
|
|
|
|
compatible = "fsl,fman-dtsec";
|
|
|
|
|
cell-index = <0>;
|
|
|
|
|
reg = <0xe0000 0x1000>;
|
|
|
|
|
fsl,fman-ports = <&fman1_rx8 &fman1_tx28>;
|
|
|
|
|
ptp-timer = <&ptp-timer>;
|
2015-12-23 18:42:11 -07:00
|
|
|
tbi-handle = <&tbi0>;
|
2014-09-17 05:08:30 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
============================================================================
|
|
|
|
|
FMan IEEE 1588 Node
|
|
|
|
|
|
2018-06-25 06:37:09 -06:00
|
|
|
Refer to Documentation/devicetree/bindings/ptp/ptp-qoriq.txt
|
2014-09-17 05:08:30 -06:00
|
|
|
|
2015-01-28 04:54:24 -07:00
|
|
|
=============================================================================
|
|
|
|
|
FMan MDIO Node
|
|
|
|
|
|
|
|
|
|
DESCRIPTION
|
|
|
|
|
|
|
|
|
|
The MDIO is a bus to which the PHY devices are connected.
|
|
|
|
|
|
|
|
|
|
PROPERTIES
|
|
|
|
|
|
|
|
|
|
- compatible
|
|
|
|
|
Usage: required
|
|
|
|
|
Value type: <stringlist>
|
|
|
|
|
Definition: A standard property.
|
|
|
|
|
Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
|
|
|
|
|
Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
|
|
|
|
|
Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
|
|
|
|
|
FMan v3.
|
|
|
|
|
|
|
|
|
|
- reg
|
|
|
|
|
Usage: required
|
|
|
|
|
Value type: <prop-encoded-array>
|
|
|
|
|
Definition: A standard property.
|
|
|
|
|
|
|
|
|
|
- bus-frequency
|
|
|
|
|
Usage: optional
|
|
|
|
|
Value type: <u32>
|
|
|
|
|
Definition: Specifies the external MDIO bus clock speed to
|
|
|
|
|
be used, if different from the standard 2.5 MHz.
|
|
|
|
|
This may be due to the standard speed being unsupported (e.g.
|
|
|
|
|
due to a hardware problem), or to advertise that all relevant
|
|
|
|
|
components in the system support a faster speed.
|
|
|
|
|
|
|
|
|
|
- interrupts
|
|
|
|
|
Usage: required for external MDIO
|
|
|
|
|
Value type: <prop-encoded-array>
|
|
|
|
|
Definition: Event interrupt of external MDIO controller.
|
|
|
|
|
|
|
|
|
|
- fsl,fman-internal-mdio
|
|
|
|
|
Usage: required for internal MDIO
|
|
|
|
|
Value type: boolean
|
|
|
|
|
Definition: Fman has internal MDIO for internal PCS(Physical
|
|
|
|
|
Coding Sublayer) PHYs and external MDIO for external PHYs.
|
|
|
|
|
The settings and programming routines for internal/external
|
|
|
|
|
MDIO are different. Must be included for internal MDIO.
|
|
|
|
|
|
2015-12-23 18:42:11 -07:00
|
|
|
For internal PHY device on internal mdio bus, a PHY node should be created.
|
|
|
|
|
See the definition of the PHY node in booting-without-of.txt for an
|
|
|
|
|
example of how to define a PHY (Internal PHY has no interrupt line).
|
|
|
|
|
- For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
|
|
|
|
|
- For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY,
|
|
|
|
|
PCS PHY addr must be '0'.
|
|
|
|
|
|
2015-01-28 04:54:24 -07:00
|
|
|
EXAMPLE
|
|
|
|
|
|
|
|
|
|
Example for FMan v2 external MDIO:
|
|
|
|
|
|
|
|
|
|
mdio@f1000 {
|
|
|
|
|
compatible = "fsl,fman-xmdio";
|
|
|
|
|
reg = <0xf1000 0x1000>;
|
|
|
|
|
interrupts = <101 2 0 0>;
|
|
|
|
|
};
|
|
|
|
|
|
2015-12-23 18:42:11 -07:00
|
|
|
Example for FMan v2 internal MDIO:
|
|
|
|
|
|
|
|
|
|
mdio@e3120 {
|
|
|
|
|
compatible = "fsl,fman-mdio";
|
|
|
|
|
reg = <0xe3120 0xee0>;
|
|
|
|
|
fsl,fman-internal-mdio;
|
|
|
|
|
|
|
|
|
|
tbi1: tbi-phy@8 {
|
|
|
|
|
reg = <0x8>;
|
|
|
|
|
device_type = "tbi-phy";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2015-01-28 04:54:24 -07:00
|
|
|
Example for FMan v3 internal MDIO:
|
|
|
|
|
|
|
|
|
|
mdio@f1000 {
|
|
|
|
|
compatible = "fsl,fman-memac-mdio";
|
|
|
|
|
reg = <0xf1000 0x1000>;
|
|
|
|
|
fsl,fman-internal-mdio;
|
2015-12-23 18:42:11 -07:00
|
|
|
|
|
|
|
|
pcsphy6: ethernet-phy@0 {
|
|
|
|
|
reg = <0x0>;
|
|
|
|
|
};
|
2015-01-28 04:54:24 -07:00
|
|
|
};
|
|
|
|
|
|
2014-09-17 05:08:30 -06:00
|
|
|
=============================================================================
|
|
|
|
|
Example
|
|
|
|
|
|
|
|
|
|
fman@400000 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
cell-index = <1>;
|
|
|
|
|
compatible = "fsl,fman"
|
|
|
|
|
ranges = <0 0x400000 0x100000>;
|
|
|
|
|
reg = <0x400000 0x100000>;
|
|
|
|
|
clocks = <&fman_clk>;
|
|
|
|
|
clock-names = "fmanclk";
|
|
|
|
|
interrupts = <
|
|
|
|
|
96 2 0 0
|
|
|
|
|
16 2 1 1>;
|
|
|
|
|
fsl,qman-channel-range = <0x40 0xc>;
|
|
|
|
|
|
|
|
|
|
muram@0 {
|
|
|
|
|
compatible = "fsl,fman-muram";
|
|
|
|
|
reg = <0x0 0x28000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
port@81000 {
|
|
|
|
|
cell-index = <1>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-oh";
|
|
|
|
|
reg = <0x81000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
port@82000 {
|
|
|
|
|
cell-index = <2>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-oh";
|
|
|
|
|
reg = <0x82000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
port@83000 {
|
|
|
|
|
cell-index = <3>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-oh";
|
|
|
|
|
reg = <0x83000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
port@84000 {
|
|
|
|
|
cell-index = <4>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-oh";
|
|
|
|
|
reg = <0x84000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
port@85000 {
|
|
|
|
|
cell-index = <5>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-oh";
|
|
|
|
|
reg = <0x85000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
port@86000 {
|
|
|
|
|
cell-index = <6>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-oh";
|
|
|
|
|
reg = <0x86000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
fman1_rx_0x8: port@88000 {
|
|
|
|
|
cell-index = <0x8>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-rx";
|
|
|
|
|
reg = <0x88000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
fman1_rx_0x9: port@89000 {
|
|
|
|
|
cell-index = <0x9>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-rx";
|
|
|
|
|
reg = <0x89000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
fman1_rx_0xa: port@8a000 {
|
|
|
|
|
cell-index = <0xa>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-rx";
|
|
|
|
|
reg = <0x8a000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
fman1_rx_0xb: port@8b000 {
|
|
|
|
|
cell-index = <0xb>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-rx";
|
|
|
|
|
reg = <0x8b000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
fman1_rx_0xc: port@8c000 {
|
|
|
|
|
cell-index = <0xc>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-rx";
|
|
|
|
|
reg = <0x8c000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
fman1_rx_0x10: port@90000 {
|
|
|
|
|
cell-index = <0x10>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-rx";
|
|
|
|
|
reg = <0x90000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
fman1_tx_0x28: port@a8000 {
|
|
|
|
|
cell-index = <0x28>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-tx";
|
|
|
|
|
reg = <0xa8000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
fman1_tx_0x29: port@a9000 {
|
|
|
|
|
cell-index = <0x29>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-tx";
|
|
|
|
|
reg = <0xa9000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
fman1_tx_0x2a: port@aa000 {
|
|
|
|
|
cell-index = <0x2a>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-tx";
|
|
|
|
|
reg = <0xaa000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
fman1_tx_0x2b: port@ab000 {
|
|
|
|
|
cell-index = <0x2b>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-tx";
|
|
|
|
|
reg = <0xab000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
fman1_tx_0x2c: port@ac0000 {
|
|
|
|
|
cell-index = <0x2c>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-tx";
|
|
|
|
|
reg = <0xac000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
fman1_tx_0x30: port@b0000 {
|
|
|
|
|
cell-index = <0x30>;
|
|
|
|
|
compatible = "fsl,fman-v2-port-tx";
|
|
|
|
|
reg = <0xb0000 0x1000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ethernet@e0000 {
|
|
|
|
|
compatible = "fsl,fman-dtsec";
|
|
|
|
|
cell-index = <0>;
|
|
|
|
|
reg = <0xe0000 0x1000>;
|
|
|
|
|
fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
|
2015-12-23 18:42:11 -07:00
|
|
|
tbi-handle = <&tbi5>;
|
2014-09-17 05:08:30 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ethernet@e2000 {
|
|
|
|
|
compatible = "fsl,fman-dtsec";
|
|
|
|
|
cell-index = <1>;
|
|
|
|
|
reg = <0xe2000 0x1000>;
|
|
|
|
|
fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>;
|
2015-12-23 18:42:11 -07:00
|
|
|
tbi-handle = <&tbi6>;
|
2014-09-17 05:08:30 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ethernet@e4000 {
|
|
|
|
|
compatible = "fsl,fman-dtsec";
|
|
|
|
|
cell-index = <2>;
|
|
|
|
|
reg = <0xe4000 0x1000>;
|
|
|
|
|
fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>;
|
2015-12-23 18:42:11 -07:00
|
|
|
tbi-handle = <&tbi7>;
|
2014-09-17 05:08:30 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ethernet@e6000 {
|
|
|
|
|
compatible = "fsl,fman-dtsec";
|
|
|
|
|
cell-index = <3>;
|
|
|
|
|
reg = <0xe6000 0x1000>;
|
|
|
|
|
fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>;
|
2015-12-23 18:42:11 -07:00
|
|
|
tbi-handle = <&tbi8>;
|
2014-09-17 05:08:30 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ethernet@e8000 {
|
|
|
|
|
compatible = "fsl,fman-dtsec";
|
|
|
|
|
cell-index = <4>;
|
|
|
|
|
reg = <0xf0000 0x1000>;
|
|
|
|
|
fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>;
|
2015-12-23 18:42:11 -07:00
|
|
|
tbi-handle = <&tbi9>;
|
2014-09-17 05:08:30 -06:00
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|
|
|
|
|
|
ethernet@f0000 {
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|
|
|
|
cell-index = <8>;
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|
|
|
compatible = "fsl,fman-xgec";
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|
|
|
|
reg = <0xf0000 0x1000>;
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|
|
|
fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
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|
|
|
};
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|
|
|
|
|
ptp-timer@fe000 {
|
|
|
|
|
compatible = "fsl,fman-ptp-timer";
|
|
|
|
|
reg = <0xfe000 0x1000>;
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|
|
|
|
};
|
2015-01-28 04:54:24 -07:00
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|
|
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|
|
mdio@f1000 {
|
|
|
|
|
compatible = "fsl,fman-xmdio";
|
|
|
|
|
reg = <0xf1000 0x1000>;
|
|
|
|
|
interrupts = <101 2 0 0>;
|
|
|
|
|
};
|
2014-09-17 05:08:30 -06:00
|
|
|
};
|