arm64: dts: ti: Add Support for AM654 SoC
The AM654 SoC is a lead device of the K3 Multicore SoC architecture
platform, targeted for broad market and industrial control with aim to
meet the complex processing needs of modern embedded products.
Some highlights of this SoC are:
* Quad ARMv8 A53 cores split over two clusters
* GICv3 compliant GIC500
* Configurable L3 Cache and IO-coherent architecture
* Dual lock-step capable R5F uC for safety-critical applications
* High data throughput capable distributed DMA architecture under NAVSS
* Three Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
* Centralized System Controller for Security, Power, and Resource
management.
* Dual ADCSS, eQEP/eCAP, eHRPWM, dual CAN-FD
* Flash subsystem with OSPI and Hyperbus interfaces
* Multimedia capability with CAL, DSS7-UL, SGX544, McASP
* Peripheral connectivity including USB3, PCIE, MMC/SD, GPMC, I2C, SPI,
GPIO
See AM65x Technical Reference Manual (SPRUID7, April 2018)
for further details: http://www.ti.com/lit/pdf/spruid7
NOTE:
1. AM654 is the first of the device variants, hence we introduce a
generic am65.dtsi.
2. We indicate the proper bus topology, the ranges are elaborated in
each bus segment instead of using the top level ranges to make sure
that peripherals in each segment use the address space accurately.
3. Peripherals in each bus segment is maintained in a separate dtsi
allowing for reuse in different bus segment representation from a
different core such as R5. This is also the reason for maintaining a
1-1 address map in the ranges.
4. Cache descriptions follow the ARM64 standard description.
Further tweaks may be necessary as we introduce more complex devices,
but can be introduced in context of the device introduction.
Reviewed-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-06-26 10:26:13 -06:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM6 SoC Family Main Domain peripherals
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*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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2019-05-29 03:18:09 -06:00
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#include <dt-bindings/phy/phy-am654-serdes.h>
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arm64: dts: ti: Add Support for AM654 SoC
The AM654 SoC is a lead device of the K3 Multicore SoC architecture
platform, targeted for broad market and industrial control with aim to
meet the complex processing needs of modern embedded products.
Some highlights of this SoC are:
* Quad ARMv8 A53 cores split over two clusters
* GICv3 compliant GIC500
* Configurable L3 Cache and IO-coherent architecture
* Dual lock-step capable R5F uC for safety-critical applications
* High data throughput capable distributed DMA architecture under NAVSS
* Three Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
* Centralized System Controller for Security, Power, and Resource
management.
* Dual ADCSS, eQEP/eCAP, eHRPWM, dual CAN-FD
* Flash subsystem with OSPI and Hyperbus interfaces
* Multimedia capability with CAL, DSS7-UL, SGX544, McASP
* Peripheral connectivity including USB3, PCIE, MMC/SD, GPMC, I2C, SPI,
GPIO
See AM65x Technical Reference Manual (SPRUID7, April 2018)
for further details: http://www.ti.com/lit/pdf/spruid7
NOTE:
1. AM654 is the first of the device variants, hence we introduce a
generic am65.dtsi.
2. We indicate the proper bus topology, the ranges are elaborated in
each bus segment instead of using the top level ranges to make sure
that peripherals in each segment use the address space accurately.
3. Peripherals in each bus segment is maintained in a separate dtsi
allowing for reuse in different bus segment representation from a
different core such as R5. This is also the reason for maintaining a
1-1 address map in the ranges.
4. Cache descriptions follow the ARM64 standard description.
Further tweaks may be necessary as we introduce more complex devices,
but can be introduced in context of the device introduction.
Reviewed-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-06-26 10:26:13 -06:00
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&cbass_main {
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2019-01-11 02:44:15 -07:00
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msmc_ram: sram@70000000 {
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compatible = "mmio-sram";
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reg = <0x0 0x70000000 0x0 0x200000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x70000000 0x200000>;
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atf-sram@0 {
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reg = <0x0 0x20000>;
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};
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sysfw-sram@f0000 {
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reg = <0xf0000 0x10000>;
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};
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l3cache-sram@100000 {
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reg = <0x100000 0x100000>;
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};
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};
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arm64: dts: ti: Add Support for AM654 SoC
The AM654 SoC is a lead device of the K3 Multicore SoC architecture
platform, targeted for broad market and industrial control with aim to
meet the complex processing needs of modern embedded products.
Some highlights of this SoC are:
* Quad ARMv8 A53 cores split over two clusters
* GICv3 compliant GIC500
* Configurable L3 Cache and IO-coherent architecture
* Dual lock-step capable R5F uC for safety-critical applications
* High data throughput capable distributed DMA architecture under NAVSS
* Three Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
* Centralized System Controller for Security, Power, and Resource
management.
* Dual ADCSS, eQEP/eCAP, eHRPWM, dual CAN-FD
* Flash subsystem with OSPI and Hyperbus interfaces
* Multimedia capability with CAL, DSS7-UL, SGX544, McASP
* Peripheral connectivity including USB3, PCIE, MMC/SD, GPMC, I2C, SPI,
GPIO
See AM65x Technical Reference Manual (SPRUID7, April 2018)
for further details: http://www.ti.com/lit/pdf/spruid7
NOTE:
1. AM654 is the first of the device variants, hence we introduce a
generic am65.dtsi.
2. We indicate the proper bus topology, the ranges are elaborated in
each bus segment instead of using the top level ranges to make sure
that peripherals in each segment use the address space accurately.
3. Peripherals in each bus segment is maintained in a separate dtsi
allowing for reuse in different bus segment representation from a
different core such as R5. This is also the reason for maintaining a
1-1 address map in the ranges.
4. Cache descriptions follow the ARM64 standard description.
Further tweaks may be necessary as we introduce more complex devices,
but can be introduced in context of the device introduction.
Reviewed-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-06-26 10:26:13 -06:00
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gic500: interrupt-controller@1800000 {
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compatible = "arm,gic-v3";
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2018-09-05 05:17:38 -06:00
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#address-cells = <2>;
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#size-cells = <2>;
|
arm64: dts: ti: Add Support for AM654 SoC
The AM654 SoC is a lead device of the K3 Multicore SoC architecture
platform, targeted for broad market and industrial control with aim to
meet the complex processing needs of modern embedded products.
Some highlights of this SoC are:
* Quad ARMv8 A53 cores split over two clusters
* GICv3 compliant GIC500
* Configurable L3 Cache and IO-coherent architecture
* Dual lock-step capable R5F uC for safety-critical applications
* High data throughput capable distributed DMA architecture under NAVSS
* Three Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
* Centralized System Controller for Security, Power, and Resource
management.
* Dual ADCSS, eQEP/eCAP, eHRPWM, dual CAN-FD
* Flash subsystem with OSPI and Hyperbus interfaces
* Multimedia capability with CAL, DSS7-UL, SGX544, McASP
* Peripheral connectivity including USB3, PCIE, MMC/SD, GPMC, I2C, SPI,
GPIO
See AM65x Technical Reference Manual (SPRUID7, April 2018)
for further details: http://www.ti.com/lit/pdf/spruid7
NOTE:
1. AM654 is the first of the device variants, hence we introduce a
generic am65.dtsi.
2. We indicate the proper bus topology, the ranges are elaborated in
each bus segment instead of using the top level ranges to make sure
that peripherals in each segment use the address space accurately.
3. Peripherals in each bus segment is maintained in a separate dtsi
allowing for reuse in different bus segment representation from a
different core such as R5. This is also the reason for maintaining a
1-1 address map in the ranges.
4. Cache descriptions follow the ARM64 standard description.
Further tweaks may be necessary as we introduce more complex devices,
but can be introduced in context of the device introduction.
Reviewed-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-06-26 10:26:13 -06:00
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ranges;
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#interrupt-cells = <3>;
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interrupt-controller;
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2018-09-05 05:17:38 -06:00
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reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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<0x00 0x01880000 0x00 0x90000>; /* GICR */
|
arm64: dts: ti: Add Support for AM654 SoC
The AM654 SoC is a lead device of the K3 Multicore SoC architecture
platform, targeted for broad market and industrial control with aim to
meet the complex processing needs of modern embedded products.
Some highlights of this SoC are:
* Quad ARMv8 A53 cores split over two clusters
* GICv3 compliant GIC500
* Configurable L3 Cache and IO-coherent architecture
* Dual lock-step capable R5F uC for safety-critical applications
* High data throughput capable distributed DMA architecture under NAVSS
* Three Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
* Centralized System Controller for Security, Power, and Resource
management.
* Dual ADCSS, eQEP/eCAP, eHRPWM, dual CAN-FD
* Flash subsystem with OSPI and Hyperbus interfaces
* Multimedia capability with CAL, DSS7-UL, SGX544, McASP
* Peripheral connectivity including USB3, PCIE, MMC/SD, GPMC, I2C, SPI,
GPIO
See AM65x Technical Reference Manual (SPRUID7, April 2018)
for further details: http://www.ti.com/lit/pdf/spruid7
NOTE:
1. AM654 is the first of the device variants, hence we introduce a
generic am65.dtsi.
2. We indicate the proper bus topology, the ranges are elaborated in
each bus segment instead of using the top level ranges to make sure
that peripherals in each segment use the address space accurately.
3. Peripherals in each bus segment is maintained in a separate dtsi
allowing for reuse in different bus segment representation from a
different core such as R5. This is also the reason for maintaining a
1-1 address map in the ranges.
4. Cache descriptions follow the ARM64 standard description.
Further tweaks may be necessary as we introduce more complex devices,
but can be introduced in context of the device introduction.
Reviewed-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-06-26 10:26:13 -06:00
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/*
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* vcpumntirq:
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* virtual CPU interface maintenance interrupt
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*/
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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2019-08-08 08:39:28 -06:00
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gic_its: gic-its@1820000 {
|
arm64: dts: ti: Add Support for AM654 SoC
The AM654 SoC is a lead device of the K3 Multicore SoC architecture
platform, targeted for broad market and industrial control with aim to
meet the complex processing needs of modern embedded products.
Some highlights of this SoC are:
* Quad ARMv8 A53 cores split over two clusters
* GICv3 compliant GIC500
* Configurable L3 Cache and IO-coherent architecture
* Dual lock-step capable R5F uC for safety-critical applications
* High data throughput capable distributed DMA architecture under NAVSS
* Three Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
* Centralized System Controller for Security, Power, and Resource
management.
* Dual ADCSS, eQEP/eCAP, eHRPWM, dual CAN-FD
* Flash subsystem with OSPI and Hyperbus interfaces
* Multimedia capability with CAL, DSS7-UL, SGX544, McASP
* Peripheral connectivity including USB3, PCIE, MMC/SD, GPMC, I2C, SPI,
GPIO
See AM65x Technical Reference Manual (SPRUID7, April 2018)
for further details: http://www.ti.com/lit/pdf/spruid7
NOTE:
1. AM654 is the first of the device variants, hence we introduce a
generic am65.dtsi.
2. We indicate the proper bus topology, the ranges are elaborated in
each bus segment instead of using the top level ranges to make sure
that peripherals in each segment use the address space accurately.
3. Peripherals in each bus segment is maintained in a separate dtsi
allowing for reuse in different bus segment representation from a
different core such as R5. This is also the reason for maintaining a
1-1 address map in the ranges.
4. Cache descriptions follow the ARM64 standard description.
Further tweaks may be necessary as we introduce more complex devices,
but can be introduced in context of the device introduction.
Reviewed-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-06-26 10:26:13 -06:00
|
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|
compatible = "arm,gic-v3-its";
|
2018-09-05 05:17:38 -06:00
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reg = <0x00 0x01820000 0x00 0x10000>;
|
2019-05-29 03:18:07 -06:00
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socionext,synquacer-pre-its = <0x1000000 0x400000>;
|
arm64: dts: ti: Add Support for AM654 SoC
The AM654 SoC is a lead device of the K3 Multicore SoC architecture
platform, targeted for broad market and industrial control with aim to
meet the complex processing needs of modern embedded products.
Some highlights of this SoC are:
* Quad ARMv8 A53 cores split over two clusters
* GICv3 compliant GIC500
* Configurable L3 Cache and IO-coherent architecture
* Dual lock-step capable R5F uC for safety-critical applications
* High data throughput capable distributed DMA architecture under NAVSS
* Three Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
* Centralized System Controller for Security, Power, and Resource
management.
* Dual ADCSS, eQEP/eCAP, eHRPWM, dual CAN-FD
* Flash subsystem with OSPI and Hyperbus interfaces
* Multimedia capability with CAL, DSS7-UL, SGX544, McASP
* Peripheral connectivity including USB3, PCIE, MMC/SD, GPMC, I2C, SPI,
GPIO
See AM65x Technical Reference Manual (SPRUID7, April 2018)
for further details: http://www.ti.com/lit/pdf/spruid7
NOTE:
1. AM654 is the first of the device variants, hence we introduce a
generic am65.dtsi.
2. We indicate the proper bus topology, the ranges are elaborated in
each bus segment instead of using the top level ranges to make sure
that peripherals in each segment use the address space accurately.
3. Peripherals in each bus segment is maintained in a separate dtsi
allowing for reuse in different bus segment representation from a
different core such as R5. This is also the reason for maintaining a
1-1 address map in the ranges.
4. Cache descriptions follow the ARM64 standard description.
Further tweaks may be necessary as we introduce more complex devices,
but can be introduced in context of the device introduction.
Reviewed-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-06-26 10:26:13 -06:00
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msi-controller;
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#msi-cells = <1>;
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};
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};
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2018-09-05 10:20:22 -06:00
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2018-09-05 10:20:23 -06:00
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secure_proxy_main: mailbox@32c00000 {
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x00 0x32c00000 0x00 0x100000>,
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<0x00 0x32400000 0x00 0x100000>,
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<0x00 0x32800000 0x00 0x100000>;
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interrupt-names = "rx_011";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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};
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2019-05-29 03:18:09 -06:00
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serdes0: serdes@900000 {
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compatible = "ti,phy-am654-serdes";
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reg = <0x0 0x900000 0x0 0x2000>;
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reg-names = "serdes";
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#phy-cells = <2>;
|
2019-07-29 06:30:22 -06:00
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power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
|
2019-05-29 03:18:09 -06:00
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clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
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clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
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assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
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assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
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ti,serdes-clk = <&serdes0_clk>;
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#clock-cells = <1>;
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mux-controls = <&serdes_mux 0>;
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};
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serdes1: serdes@910000 {
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compatible = "ti,phy-am654-serdes";
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reg = <0x0 0x910000 0x0 0x2000>;
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reg-names = "serdes";
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#phy-cells = <2>;
|
2019-07-29 06:30:22 -06:00
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power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
|
2019-05-29 03:18:09 -06:00
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clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
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clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
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assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
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assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
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ti,serdes-clk = <&serdes1_clk>;
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#clock-cells = <1>;
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mux-controls = <&serdes_mux 1>;
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};
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|
2018-09-05 10:20:22 -06:00
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main_uart0: serial@2800000 {
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compatible = "ti,am654-uart";
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reg = <0x00 0x02800000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
|
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
|
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|
|
clock-frequency = <48000000>;
|
|
|
|
|
current-speed = <115200>;
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
|
2018-09-05 10:20:22 -06:00
|
|
|
};
|
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main_uart1: serial@2810000 {
|
|
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|
compatible = "ti,am654-uart";
|
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|
|
reg = <0x00 0x02810000 0x00 0x100>;
|
|
|
|
|
reg-shift = <2>;
|
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|
|
reg-io-width = <4>;
|
|
|
|
|
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-frequency = <48000000>;
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
|
2018-09-05 10:20:22 -06:00
|
|
|
};
|
|
|
|
|
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|
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|
main_uart2: serial@2820000 {
|
|
|
|
|
compatible = "ti,am654-uart";
|
|
|
|
|
reg = <0x00 0x02820000 0x00 0x100>;
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
|
reg-io-width = <4>;
|
|
|
|
|
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-frequency = <48000000>;
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
|
2018-09-05 10:20:22 -06:00
|
|
|
};
|
2018-11-12 23:01:09 -07:00
|
|
|
|
|
|
|
|
main_pmx0: pinmux@11c000 {
|
|
|
|
|
compatible = "pinctrl-single";
|
|
|
|
|
reg = <0x0 0x11c000 0x0 0x2e4>;
|
|
|
|
|
#pinctrl-cells = <1>;
|
|
|
|
|
pinctrl-single,register-width = <32>;
|
|
|
|
|
pinctrl-single,function-mask = <0xffffffff>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_pmx1: pinmux@11c2e8 {
|
|
|
|
|
compatible = "pinctrl-single";
|
|
|
|
|
reg = <0x0 0x11c2e8 0x0 0x24>;
|
|
|
|
|
#pinctrl-cells = <1>;
|
|
|
|
|
pinctrl-single,register-width = <32>;
|
|
|
|
|
pinctrl-single,function-mask = <0xffffffff>;
|
|
|
|
|
};
|
2018-11-12 23:01:11 -07:00
|
|
|
|
|
|
|
|
main_i2c0: i2c@2000000 {
|
|
|
|
|
compatible = "ti,am654-i2c", "ti,omap4-i2c";
|
|
|
|
|
reg = <0x0 0x2000000 0x0 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
clocks = <&k3_clks 110 1>;
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
|
2018-11-12 23:01:11 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_i2c1: i2c@2010000 {
|
|
|
|
|
compatible = "ti,am654-i2c", "ti,omap4-i2c";
|
|
|
|
|
reg = <0x0 0x2010000 0x0 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
clocks = <&k3_clks 111 1>;
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
|
2018-11-12 23:01:11 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_i2c2: i2c@2020000 {
|
|
|
|
|
compatible = "ti,am654-i2c", "ti,omap4-i2c";
|
|
|
|
|
reg = <0x0 0x2020000 0x0 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
clocks = <&k3_clks 112 1>;
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
|
2018-11-12 23:01:11 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_i2c3: i2c@2030000 {
|
|
|
|
|
compatible = "ti,am654-i2c", "ti,omap4-i2c";
|
|
|
|
|
reg = <0x0 0x2030000 0x0 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
clocks = <&k3_clks 113 1>;
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
|
2018-11-12 23:01:11 -07:00
|
|
|
};
|
2018-12-07 02:35:34 -07:00
|
|
|
|
|
|
|
|
ecap0: pwm@3100000 {
|
|
|
|
|
compatible = "ti,am654-ecap", "ti,am3352-ecap";
|
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
|
reg = <0x0 0x03100000 0x0 0x60>;
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
|
2018-12-07 02:35:34 -07:00
|
|
|
clocks = <&k3_clks 39 0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
};
|
2018-12-09 03:22:21 -07:00
|
|
|
|
|
|
|
|
main_spi0: spi@2100000 {
|
|
|
|
|
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
|
|
|
|
reg = <0x0 0x2100000 0x0 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&k3_clks 137 1>;
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
|
2018-12-09 03:22:21 -07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_spi1: spi@2110000 {
|
|
|
|
|
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
|
|
|
|
reg = <0x0 0x2110000 0x0 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&k3_clks 138 1>;
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
|
2018-12-09 03:22:21 -07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
assigned-clocks = <&k3_clks 137 1>;
|
|
|
|
|
assigned-clock-rates = <48000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_spi2: spi@2120000 {
|
|
|
|
|
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
|
|
|
|
reg = <0x0 0x2120000 0x0 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&k3_clks 139 1>;
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
|
2018-12-09 03:22:21 -07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_spi3: spi@2130000 {
|
|
|
|
|
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
|
|
|
|
reg = <0x0 0x2130000 0x0 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&k3_clks 140 1>;
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
|
2018-12-09 03:22:21 -07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_spi4: spi@2140000 {
|
|
|
|
|
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
|
|
|
|
|
reg = <0x0 0x2140000 0x0 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&k3_clks 141 1>;
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
|
2018-12-09 03:22:21 -07:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
2019-01-17 02:44:23 -07:00
|
|
|
|
|
|
|
|
sdhci0: sdhci@4f80000 {
|
|
|
|
|
compatible = "ti,am654-sdhci-5.1";
|
|
|
|
|
reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
|
2019-01-17 02:44:23 -07:00
|
|
|
clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
|
|
|
|
|
clock-names = "clk_ahb", "clk_xin";
|
|
|
|
|
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
mmc-ddr-1_8v;
|
|
|
|
|
mmc-hs200-1_8v;
|
|
|
|
|
ti,otap-del-sel = <0x2>;
|
|
|
|
|
ti,trm-icp = <0x8>;
|
|
|
|
|
dma-coherent;
|
|
|
|
|
};
|
2019-02-05 05:45:20 -07:00
|
|
|
|
|
|
|
|
scm_conf: scm_conf@100000 {
|
|
|
|
|
compatible = "syscon", "simple-mfd";
|
|
|
|
|
reg = <0 0x00100000 0 0x1c000>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x0 0x0 0x00100000 0x1c000>;
|
2019-05-29 03:18:08 -06:00
|
|
|
|
2019-05-29 03:18:10 -06:00
|
|
|
pcie0_mode: pcie-mode@4060 {
|
|
|
|
|
compatible = "syscon";
|
|
|
|
|
reg = <0x00004060 0x4>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcie1_mode: pcie-mode@4070 {
|
|
|
|
|
compatible = "syscon";
|
|
|
|
|
reg = <0x00004070 0x4>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcie_devid: pcie-devid@210 {
|
|
|
|
|
compatible = "syscon";
|
|
|
|
|
reg = <0x00000210 0x4>;
|
|
|
|
|
};
|
|
|
|
|
|
2019-05-29 03:18:09 -06:00
|
|
|
serdes0_clk: serdes_clk@4080 {
|
|
|
|
|
compatible = "syscon";
|
|
|
|
|
reg = <0x00004080 0x4>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
serdes1_clk: serdes_clk@4090 {
|
|
|
|
|
compatible = "syscon";
|
|
|
|
|
reg = <0x00004090 0x4>;
|
|
|
|
|
};
|
|
|
|
|
|
2019-05-29 03:18:08 -06:00
|
|
|
serdes_mux: mux-controller {
|
|
|
|
|
compatible = "mmio-mux";
|
|
|
|
|
#mux-control-cells = <1>;
|
|
|
|
|
mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
|
|
|
|
|
<0x4090 0x3>; /* SERDES1 lane select */
|
|
|
|
|
};
|
2019-02-05 05:45:20 -07:00
|
|
|
};
|
2019-02-05 05:45:21 -07:00
|
|
|
|
|
|
|
|
dwc3_0: dwc3@4000000 {
|
|
|
|
|
compatible = "ti,am654-dwc3";
|
|
|
|
|
reg = <0x0 0x4000000 0x0 0x4000>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x0 0x0 0x4000000 0x20000>;
|
|
|
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dma-coherent;
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
|
2020-03-11 08:41:11 -06:00
|
|
|
clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
|
2019-02-05 05:45:21 -07:00
|
|
|
assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
|
|
|
|
|
<&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
|
|
|
|
|
|
|
|
|
|
usb0: usb@10000 {
|
|
|
|
|
compatible = "snps,dwc3";
|
|
|
|
|
reg = <0x10000 0x10000>;
|
|
|
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "peripheral",
|
|
|
|
|
"host",
|
|
|
|
|
"otg";
|
|
|
|
|
maximum-speed = "high-speed";
|
|
|
|
|
dr_mode = "otg";
|
|
|
|
|
phys = <&usb0_phy>;
|
|
|
|
|
phy-names = "usb2-phy";
|
|
|
|
|
snps,dis_u3_susphy_quirk;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb0_phy: phy@4100000 {
|
|
|
|
|
compatible = "ti,am654-usb2", "ti,omap-usb2";
|
|
|
|
|
reg = <0x0 0x4100000 0x0 0x54>;
|
|
|
|
|
syscon-phy-power = <&scm_conf 0x4000>;
|
|
|
|
|
clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
|
|
|
|
|
clock-names = "wkupclk", "refclk";
|
|
|
|
|
#phy-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dwc3_1: dwc3@4020000 {
|
|
|
|
|
compatible = "ti,am654-dwc3";
|
|
|
|
|
reg = <0x0 0x4020000 0x0 0x4000>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x0 0x0 0x4020000 0x20000>;
|
|
|
|
|
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dma-coherent;
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
|
2020-03-11 08:41:11 -06:00
|
|
|
clocks = <&k3_clks 152 2>;
|
2019-02-05 05:45:21 -07:00
|
|
|
assigned-clocks = <&k3_clks 152 2>;
|
|
|
|
|
assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
|
|
|
|
|
|
|
|
|
|
usb1: usb@10000 {
|
|
|
|
|
compatible = "snps,dwc3";
|
|
|
|
|
reg = <0x10000 0x10000>;
|
|
|
|
|
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "peripheral",
|
|
|
|
|
"host",
|
|
|
|
|
"otg";
|
|
|
|
|
maximum-speed = "high-speed";
|
|
|
|
|
dr_mode = "otg";
|
|
|
|
|
phys = <&usb1_phy>;
|
|
|
|
|
phy-names = "usb2-phy";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb1_phy: phy@4110000 {
|
|
|
|
|
compatible = "ti,am654-usb2", "ti,omap-usb2";
|
|
|
|
|
reg = <0x0 0x4110000 0x0 0x54>;
|
|
|
|
|
syscon-phy-power = <&scm_conf 0x4020>;
|
|
|
|
|
clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
|
|
|
|
|
clock-names = "wkupclk", "refclk";
|
|
|
|
|
#phy-cells = <0>;
|
|
|
|
|
};
|
2019-05-02 03:41:18 -06:00
|
|
|
|
|
|
|
|
intr_main_gpio: interrupt-controller0 {
|
|
|
|
|
compatible = "ti,sci-intr";
|
|
|
|
|
ti,intr-trigger-type = <1>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
interrupt-parent = <&gic500>;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
ti,sci = <&dmsc>;
|
|
|
|
|
ti,sci-dst-id = <56>;
|
|
|
|
|
ti,sci-rm-range-girq = <0x1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cbass_main_navss: interconnect0 {
|
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
ranges;
|
|
|
|
|
|
|
|
|
|
intr_main_navss: interrupt-controller1 {
|
|
|
|
|
compatible = "ti,sci-intr";
|
|
|
|
|
ti,intr-trigger-type = <4>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
interrupt-parent = <&gic500>;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
ti,sci = <&dmsc>;
|
|
|
|
|
ti,sci-dst-id = <56>;
|
|
|
|
|
ti,sci-rm-range-girq = <0x0>, <0x2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
inta_main_udmass: interrupt-controller@33d00000 {
|
|
|
|
|
compatible = "ti,sci-inta";
|
|
|
|
|
reg = <0x0 0x33d00000 0x0 0x100000>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
interrupt-parent = <&intr_main_navss>;
|
|
|
|
|
msi-controller;
|
|
|
|
|
ti,sci = <&dmsc>;
|
|
|
|
|
ti,sci-dev-id = <179>;
|
|
|
|
|
ti,sci-rm-range-vint = <0x0>;
|
|
|
|
|
ti,sci-rm-range-global-event = <0x1>;
|
|
|
|
|
};
|
2019-07-22 13:05:38 -06:00
|
|
|
|
|
|
|
|
hwspinlock: spinlock@30e00000 {
|
|
|
|
|
compatible = "ti,am654-hwspinlock";
|
|
|
|
|
reg = <0x00 0x30e00000 0x00 0x1000>;
|
|
|
|
|
#hwlock-cells = <1>;
|
|
|
|
|
};
|
2019-05-02 03:41:18 -06:00
|
|
|
};
|
2019-06-06 03:56:19 -06:00
|
|
|
|
|
|
|
|
main_gpio0: main_gpio0@600000 {
|
|
|
|
|
compatible = "ti,am654-gpio", "ti,keystone-gpio";
|
|
|
|
|
reg = <0x0 0x600000 0x0 0x100>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-parent = <&intr_main_gpio>;
|
|
|
|
|
interrupts = <57 256>, <57 257>, <57 258>, <57 259>, <57 260>,
|
|
|
|
|
<57 261>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
ti,ngpio = <96>;
|
|
|
|
|
ti,davinci-gpio-unbanked = <0>;
|
|
|
|
|
clocks = <&k3_clks 57 0>;
|
|
|
|
|
clock-names = "gpio";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
main_gpio1: main_gpio1@601000 {
|
|
|
|
|
compatible = "ti,am654-gpio", "ti,keystone-gpio";
|
|
|
|
|
reg = <0x0 0x601000 0x0 0x100>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-parent = <&intr_main_gpio>;
|
|
|
|
|
interrupts = <58 256>, <58 257>, <58 258>, <58 259>, <58 260>,
|
|
|
|
|
<58 261>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
ti,ngpio = <90>;
|
|
|
|
|
ti,davinci-gpio-unbanked = <0>;
|
|
|
|
|
clocks = <&k3_clks 58 0>;
|
|
|
|
|
clock-names = "gpio";
|
|
|
|
|
};
|
2019-05-29 03:18:10 -06:00
|
|
|
|
|
|
|
|
pcie0_rc: pcie@5500000 {
|
|
|
|
|
compatible = "ti,am654-pcie-rc";
|
|
|
|
|
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
|
|
|
|
|
reg-names = "app", "dbics", "config", "atu";
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
|
2019-05-29 03:18:10 -06:00
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
|
|
|
|
|
0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
|
|
|
|
|
ti,syscon-pcie-id = <&pcie_devid>;
|
|
|
|
|
ti,syscon-pcie-mode = <&pcie0_mode>;
|
|
|
|
|
bus-range = <0x0 0xff>;
|
|
|
|
|
num-viewport = <16>;
|
|
|
|
|
max-link-speed = <3>;
|
|
|
|
|
dma-coherent;
|
|
|
|
|
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
|
msi-map = <0x0 &gic_its 0x0 0x10000>;
|
|
|
|
|
};
|
|
|
|
|
|
2019-05-29 03:18:11 -06:00
|
|
|
pcie0_ep: pcie-ep@5500000 {
|
|
|
|
|
compatible = "ti,am654-pcie-ep";
|
|
|
|
|
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
|
|
|
|
|
reg-names = "app", "dbics", "addr_space", "atu";
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
|
2019-05-29 03:18:11 -06:00
|
|
|
ti,syscon-pcie-mode = <&pcie0_mode>;
|
|
|
|
|
num-ib-windows = <16>;
|
|
|
|
|
num-ob-windows = <16>;
|
|
|
|
|
max-link-speed = <3>;
|
|
|
|
|
dma-coherent;
|
|
|
|
|
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
|
};
|
|
|
|
|
|
2019-05-29 03:18:10 -06:00
|
|
|
pcie1_rc: pcie@5600000 {
|
|
|
|
|
compatible = "ti,am654-pcie-rc";
|
|
|
|
|
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
|
|
|
|
|
reg-names = "app", "dbics", "config", "atu";
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
|
2019-05-29 03:18:10 -06:00
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
|
|
|
|
|
0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>;
|
|
|
|
|
ti,syscon-pcie-id = <&pcie_devid>;
|
|
|
|
|
ti,syscon-pcie-mode = <&pcie1_mode>;
|
|
|
|
|
bus-range = <0x0 0xff>;
|
|
|
|
|
num-viewport = <16>;
|
|
|
|
|
max-link-speed = <3>;
|
|
|
|
|
dma-coherent;
|
|
|
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
|
msi-map = <0x0 &gic_its 0x10000 0x10000>;
|
|
|
|
|
};
|
2019-05-29 03:18:11 -06:00
|
|
|
|
|
|
|
|
pcie1_ep: pcie-ep@5600000 {
|
|
|
|
|
compatible = "ti,am654-pcie-ep";
|
|
|
|
|
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
|
|
|
|
|
reg-names = "app", "dbics", "addr_space", "atu";
|
2019-07-29 06:30:22 -06:00
|
|
|
power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
|
2019-05-29 03:18:11 -06:00
|
|
|
ti,syscon-pcie-mode = <&pcie1_mode>;
|
|
|
|
|
num-ib-windows = <16>;
|
|
|
|
|
num-ob-windows = <16>;
|
|
|
|
|
max-link-speed = <3>;
|
|
|
|
|
dma-coherent;
|
|
|
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
|
};
|
arm64: dts: ti: Add Support for AM654 SoC
The AM654 SoC is a lead device of the K3 Multicore SoC architecture
platform, targeted for broad market and industrial control with aim to
meet the complex processing needs of modern embedded products.
Some highlights of this SoC are:
* Quad ARMv8 A53 cores split over two clusters
* GICv3 compliant GIC500
* Configurable L3 Cache and IO-coherent architecture
* Dual lock-step capable R5F uC for safety-critical applications
* High data throughput capable distributed DMA architecture under NAVSS
* Three Gigabit Industrial Communication Subsystems (ICSSG), each with dual
PRUs and dual RTUs
* Hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
* Centralized System Controller for Security, Power, and Resource
management.
* Dual ADCSS, eQEP/eCAP, eHRPWM, dual CAN-FD
* Flash subsystem with OSPI and Hyperbus interfaces
* Multimedia capability with CAL, DSS7-UL, SGX544, McASP
* Peripheral connectivity including USB3, PCIE, MMC/SD, GPMC, I2C, SPI,
GPIO
See AM65x Technical Reference Manual (SPRUID7, April 2018)
for further details: http://www.ti.com/lit/pdf/spruid7
NOTE:
1. AM654 is the first of the device variants, hence we introduce a
generic am65.dtsi.
2. We indicate the proper bus topology, the ranges are elaborated in
each bus segment instead of using the top level ranges to make sure
that peripherals in each segment use the address space accurately.
3. Peripherals in each bus segment is maintained in a separate dtsi
allowing for reuse in different bus segment representation from a
different core such as R5. This is also the reason for maintaining a
1-1 address map in the ranges.
4. Cache descriptions follow the ARM64 standard description.
Further tweaks may be necessary as we introduce more complex devices,
but can be introduced in context of the device introduction.
Reviewed-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2018-06-26 10:26:13 -06:00
|
|
|
};
|