2018-06-25 15:41:56 -06:00
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// SPDX-License-Identifier: GPL-2.0
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2013-08-21 21:33:56 -06:00
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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******************************************************************************/
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#define _HAL_INIT_C_
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2013-10-13 21:52:20 -06:00
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#include <linux/firmware.h>
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2014-02-09 14:15:54 -07:00
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#include <linux/vmalloc.h>
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2013-08-21 21:33:56 -06:00
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#include <drv_types.h>
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#include <rtw_efuse.h>
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2014-08-31 00:44:22 -06:00
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#include <phy.h>
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2013-08-21 21:33:56 -06:00
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#include <rtl8188e_hal.h>
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#include <rtw_iol.h>
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2014-06-20 08:59:47 -06:00
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void iol_mode_enable(struct adapter *padapter, u8 enable)
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2013-08-21 21:33:56 -06:00
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{
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u8 reg_0xf0 = 0;
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if (enable) {
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/* Enable initial offload */
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2014-06-11 11:21:36 -06:00
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reg_0xf0 = usb_read8(padapter, REG_SYS_CFG);
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2014-06-11 11:21:33 -06:00
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usb_write8(padapter, REG_SYS_CFG, reg_0xf0|SW_OFFLOAD_EN);
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2013-08-21 21:33:56 -06:00
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if (!padapter->bFWReady) {
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DBG_88E("bFWReady == false call reset 8051...\n");
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_8051Reset88E(padapter);
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}
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} else {
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/* disable initial offload */
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2014-06-11 11:21:36 -06:00
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reg_0xf0 = usb_read8(padapter, REG_SYS_CFG);
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2014-06-11 11:21:33 -06:00
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usb_write8(padapter, REG_SYS_CFG, reg_0xf0 & ~SW_OFFLOAD_EN);
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2013-08-21 21:33:56 -06:00
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}
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}
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2014-06-20 08:59:47 -06:00
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s32 iol_execute(struct adapter *padapter, u8 control)
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2013-08-21 21:33:56 -06:00
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{
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s32 status = _FAIL;
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u8 reg_0x88 = 0;
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2015-11-02 03:39:22 -07:00
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unsigned long start = 0;
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2013-08-21 21:33:56 -06:00
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control = control&0x0f;
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2014-06-11 11:21:36 -06:00
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reg_0x88 = usb_read8(padapter, REG_HMEBOX_E0);
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2014-06-11 11:21:33 -06:00
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usb_write8(padapter, REG_HMEBOX_E0, reg_0x88|control);
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2013-08-21 21:33:56 -06:00
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2013-12-19 21:38:40 -07:00
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start = jiffies;
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2014-06-11 11:21:36 -06:00
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while ((reg_0x88 = usb_read8(padapter, REG_HMEBOX_E0)) & control &&
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2015-11-02 03:39:22 -07:00
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jiffies_to_msecs(jiffies - start) < 1000) {
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2015-11-02 03:43:09 -07:00
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udelay(5);
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2013-08-21 21:33:56 -06:00
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}
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2014-06-11 11:21:36 -06:00
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reg_0x88 = usb_read8(padapter, REG_HMEBOX_E0);
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2013-08-21 21:33:56 -06:00
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status = (reg_0x88 & control) ? _FAIL : _SUCCESS;
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if (reg_0x88 & control<<4)
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status = _FAIL;
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return status;
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}
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static s32 iol_InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy)
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{
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s32 rst = _SUCCESS;
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2017-02-21 07:59:21 -07:00
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2013-08-21 21:33:56 -06:00
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iol_mode_enable(padapter, 1);
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2014-06-11 11:21:33 -06:00
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usb_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
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2013-08-21 21:33:56 -06:00
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rst = iol_execute(padapter, CMD_INIT_LLT);
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iol_mode_enable(padapter, 0);
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return rst;
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}
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s32 rtl8188e_iol_efuse_patch(struct adapter *padapter)
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{
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s32 result = _SUCCESS;
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DBG_88E("==> %s\n", __func__);
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2018-08-04 08:35:40 -06:00
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if (rtw_iol_applied(padapter)) {
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2013-08-21 21:33:56 -06:00
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iol_mode_enable(padapter, 1);
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result = iol_execute(padapter, CMD_READ_EFUSE_MAP);
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if (result == _SUCCESS)
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result = iol_execute(padapter, CMD_EFUSE_PATCH);
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iol_mode_enable(padapter, 0);
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}
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return result;
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}
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#define MAX_REG_BOLCK_SIZE 196
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void _8051Reset88E(struct adapter *padapter)
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{
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u8 u1bTmp;
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2014-06-11 11:21:36 -06:00
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u1bTmp = usb_read8(padapter, REG_SYS_FUNC_EN+1);
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2015-10-18 23:51:41 -06:00
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usb_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT(2)));
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usb_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp|(BIT(2)));
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2013-08-21 21:33:56 -06:00
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DBG_88E("=====> _8051Reset88E(): 8051 reset success .\n");
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}
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void rtl8188e_InitializeFirmwareVars(struct adapter *padapter)
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{
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/* Init Fw LPS related. */
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padapter->pwrctrlpriv.bFwCurrentInPSMode = false;
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/* Init H2C counter. by tynli. 2009.12.09. */
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2016-09-18 11:28:06 -06:00
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padapter->HalData->LastHMEBoxNum = 0;
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2013-08-21 21:33:56 -06:00
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}
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2016-09-03 09:33:40 -06:00
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void rtw_hal_free_data(struct adapter *padapter)
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2013-08-21 21:33:56 -06:00
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{
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kfree(padapter->HalData);
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padapter->HalData = NULL;
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}
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2016-09-03 09:33:34 -06:00
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void rtw_hal_read_chip_version(struct adapter *padapter)
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2013-08-21 21:33:56 -06:00
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{
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u32 value32;
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struct HAL_VERSION ChipVersion;
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2016-09-18 11:28:06 -06:00
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struct hal_data_8188e *pHalData = padapter->HalData;
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2013-08-21 21:33:56 -06:00
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2014-06-11 11:21:34 -06:00
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value32 = usb_read32(padapter, REG_SYS_CFG);
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2013-08-21 21:33:56 -06:00
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ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
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ChipVersion.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
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ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK)>>CHIP_VER_RTL_SHIFT; /* IC version (CUT) */
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dump_chip_info(ChipVersion);
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pHalData->VersionID = ChipVersion;
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}
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2016-09-03 09:32:53 -06:00
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void rtw_hal_set_odm_var(struct adapter *Adapter, enum hal_odm_variable eVariable, void *pValue1, bool bSet)
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2013-08-21 21:33:56 -06:00
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{
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2016-09-18 11:28:06 -06:00
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struct odm_dm_struct *podmpriv = &Adapter->HalData->odmpriv;
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2013-08-21 21:33:56 -06:00
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switch (eVariable) {
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case HAL_ODM_STA_INFO:
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{
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2014-10-30 05:33:19 -06:00
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struct sta_info *psta = pValue1;
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2014-11-28 09:39:09 -07:00
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2013-08-21 21:33:56 -06:00
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if (bSet) {
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DBG_88E("### Set STA_(%d) info\n", psta->mac_id);
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ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, psta);
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ODM_RAInfo_Init(podmpriv, psta->mac_id);
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} else {
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DBG_88E("### Clean STA_(%d) info\n", psta->mac_id);
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ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, NULL);
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}
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}
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break;
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case HAL_ODM_P2P_STATE:
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2016-09-16 08:33:12 -06:00
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podmpriv->bWIFI_Direct = bSet;
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2013-08-21 21:33:56 -06:00
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break;
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case HAL_ODM_WIFI_DISPLAY_STATE:
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2016-09-16 08:33:12 -06:00
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podmpriv->bWIFI_Display = bSet;
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2013-08-21 21:33:56 -06:00
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break;
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default:
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break;
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}
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}
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2016-09-03 09:32:50 -06:00
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void rtw_hal_notch_filter(struct adapter *adapter, bool enable)
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2013-08-21 21:33:56 -06:00
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{
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if (enable) {
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DBG_88E("Enable notch filter\n");
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2015-10-18 23:51:41 -06:00
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usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) | BIT(1));
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2013-08-21 21:33:56 -06:00
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} else {
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DBG_88E("Disable notch filter\n");
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2015-10-18 23:51:41 -06:00
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usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) & ~BIT(1));
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2013-08-21 21:33:56 -06:00
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}
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}
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/* */
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/* */
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/* LLT R/W/Init function */
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/* */
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/* */
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static s32 _LLTWrite(struct adapter *padapter, u32 address, u32 data)
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{
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s32 status = _SUCCESS;
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s32 count = 0;
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u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
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u16 LLTReg = REG_LLT_INIT;
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2014-06-11 11:21:31 -06:00
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usb_write32(padapter, LLTReg, value);
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2013-08-21 21:33:56 -06:00
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/* polling */
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do {
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2014-06-11 11:21:34 -06:00
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value = usb_read32(padapter, LLTReg);
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2013-08-21 21:33:56 -06:00
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if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
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break;
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if (count > POLLING_LLT_THRESHOLD) {
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RT_TRACE(_module_hal_init_c_, _drv_err_, ("Failed to polling write LLT done at address %d!\n", address));
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status = _FAIL;
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break;
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}
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2015-11-02 03:43:09 -07:00
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udelay(5);
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2013-08-21 21:33:56 -06:00
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} while (count++);
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return status;
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}
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s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy)
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{
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s32 status = _FAIL;
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u32 i;
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u32 Last_Entry_Of_TxPktBuf = LAST_ENTRY_OF_TX_PKT_BUFFER;/* 176, 22k */
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2018-08-04 08:35:40 -06:00
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if (rtw_iol_applied(padapter)) {
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2013-08-21 21:33:56 -06:00
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status = iol_InitLLTTable(padapter, txpktbuf_bndy);
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} else {
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for (i = 0; i < (txpktbuf_bndy - 1); i++) {
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status = _LLTWrite(padapter, i, i + 1);
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2018-03-05 11:37:59 -07:00
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if (status != _SUCCESS)
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2013-08-21 21:33:56 -06:00
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return status;
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}
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/* end of list */
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status = _LLTWrite(padapter, (txpktbuf_bndy - 1), 0xFF);
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2018-03-05 11:37:59 -07:00
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if (status != _SUCCESS)
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2013-08-21 21:33:56 -06:00
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return status;
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/* Make the other pages as ring buffer */
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/* This ring buffer is used as beacon buffer if we config this MAC as two MAC transfer. */
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/* Otherwise used as local loopback buffer. */
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for (i = txpktbuf_bndy; i < Last_Entry_Of_TxPktBuf; i++) {
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status = _LLTWrite(padapter, i, (i + 1));
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2018-03-05 11:37:59 -07:00
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if (status != _SUCCESS)
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2013-08-21 21:33:56 -06:00
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return status;
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}
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/* Let last entry point to the start entry of ring buffer */
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status = _LLTWrite(padapter, Last_Entry_Of_TxPktBuf, txpktbuf_bndy);
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2018-12-18 11:34:51 -07:00
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if (status != _SUCCESS)
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2013-08-21 21:33:56 -06:00
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return status;
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}
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return status;
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}
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2018-09-19 14:40:01 -06:00
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void Hal_InitPGData88E(struct adapter *padapter)
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2013-08-21 21:33:56 -06:00
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{
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struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
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if (!pEEPROM->bautoload_fail_flag) { /* autoload OK. */
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if (!is_boot_from_eeprom(padapter)) {
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/* Read EFUSE real map to shadow. */
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2014-06-20 08:59:38 -06:00
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EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI);
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2013-08-21 21:33:56 -06:00
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}
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} else {/* autoload fail */
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RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("AutoLoad Fail reported from CR9346!!\n"));
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/* update to default value 0xFF */
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if (!is_boot_from_eeprom(padapter))
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2014-06-20 08:59:38 -06:00
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EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI);
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2013-08-21 21:33:56 -06:00
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}
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}
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2018-09-19 14:40:01 -06:00
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void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo)
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2013-08-21 21:33:56 -06:00
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{
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struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
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u16 EEPROMId;
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/* Checl 0x8129 again for making sure autoload status!! */
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EEPROMId = le16_to_cpu(*((__le16 *)hwinfo));
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if (EEPROMId != RTL_EEPROM_ID) {
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DBG_88E("EEPROM ID(%#x) is invalid!!\n", EEPROMId);
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pEEPROM->bautoload_fail_flag = true;
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} else {
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pEEPROM->bautoload_fail_flag = false;
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}
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DBG_88E("EEPROM ID = 0x%04x\n", EEPROMId);
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}
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static void Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g *pwrInfo24G, u8 *PROMContent, bool AutoLoadFail)
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{
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u32 rfPath, eeAddr = EEPROM_TX_PWR_INX_88E, group, TxCount = 0;
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2014-06-22 02:19:28 -06:00
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memset(pwrInfo24G, 0, sizeof(struct txpowerinfo24g));
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2013-08-21 21:33:56 -06:00
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if (AutoLoadFail) {
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for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) {
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/* 2.4G default value */
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for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
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pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
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|
pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
|
|
|
|
}
|
|
|
|
for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
|
|
|
|
if (TxCount == 0) {
|
|
|
|
pwrInfo24G->BW20_Diff[rfPath][0] = EEPROM_DEFAULT_24G_HT20_DIFF;
|
|
|
|
pwrInfo24G->OFDM_Diff[rfPath][0] = EEPROM_DEFAULT_24G_OFDM_DIFF;
|
|
|
|
} else {
|
|
|
|
pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
|
|
|
|
pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
|
|
|
|
pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
|
|
|
|
pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) {
|
|
|
|
/* 2.4G default value */
|
|
|
|
for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
|
|
|
|
pwrInfo24G->IndexCCK_Base[rfPath][group] = PROMContent[eeAddr++];
|
|
|
|
if (pwrInfo24G->IndexCCK_Base[rfPath][group] == 0xFF)
|
|
|
|
pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
|
|
|
|
}
|
|
|
|
for (group = 0; group < MAX_CHNL_GROUP_24G-1; group++) {
|
|
|
|
pwrInfo24G->IndexBW40_Base[rfPath][group] = PROMContent[eeAddr++];
|
|
|
|
if (pwrInfo24G->IndexBW40_Base[rfPath][group] == 0xFF)
|
|
|
|
pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
|
|
|
|
}
|
|
|
|
for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
|
|
|
|
if (TxCount == 0) {
|
|
|
|
pwrInfo24G->BW40_Diff[rfPath][TxCount] = 0;
|
|
|
|
if (PROMContent[eeAddr] == 0xFF) {
|
|
|
|
pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_HT20_DIFF;
|
|
|
|
} else {
|
|
|
|
pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
|
2015-10-18 23:51:41 -06:00
|
|
|
if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
|
2013-08-21 21:33:56 -06:00
|
|
|
pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (PROMContent[eeAddr] == 0xFF) {
|
|
|
|
pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_OFDM_DIFF;
|
|
|
|
} else {
|
|
|
|
pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
|
2015-10-18 23:51:41 -06:00
|
|
|
if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
|
2013-08-21 21:33:56 -06:00
|
|
|
pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
|
|
|
|
}
|
|
|
|
pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0;
|
|
|
|
eeAddr++;
|
|
|
|
} else {
|
|
|
|
if (PROMContent[eeAddr] == 0xFF) {
|
|
|
|
pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
|
|
|
|
} else {
|
|
|
|
pwrInfo24G->BW40_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
|
2015-10-18 23:51:41 -06:00
|
|
|
if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
|
2013-08-21 21:33:56 -06:00
|
|
|
pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (PROMContent[eeAddr] == 0xFF) {
|
|
|
|
pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
|
|
|
|
} else {
|
|
|
|
pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
|
2015-10-18 23:51:41 -06:00
|
|
|
if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
|
2013-08-21 21:33:56 -06:00
|
|
|
pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
|
|
|
|
}
|
|
|
|
eeAddr++;
|
|
|
|
|
|
|
|
if (PROMContent[eeAddr] == 0xFF) {
|
|
|
|
pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
|
|
|
|
} else {
|
|
|
|
pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
|
2015-10-18 23:51:41 -06:00
|
|
|
if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
|
2013-08-21 21:33:56 -06:00
|
|
|
pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (PROMContent[eeAddr] == 0xFF) {
|
|
|
|
pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
|
|
|
|
} else {
|
|
|
|
pwrInfo24G->CCK_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
|
2015-10-18 23:51:41 -06:00
|
|
|
if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
|
2013-08-21 21:33:56 -06:00
|
|
|
pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0;
|
|
|
|
}
|
|
|
|
eeAddr++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-07 13:55:15 -07:00
|
|
|
void Hal_GetChnlGroup88E(u8 chnl, u8 *group)
|
2013-08-21 21:33:56 -06:00
|
|
|
{
|
2018-09-19 14:39:58 -06:00
|
|
|
if (chnl < 3) /* Channel 1-2 */
|
2018-09-19 14:40:00 -06:00
|
|
|
*group = 0;
|
2018-09-19 14:39:58 -06:00
|
|
|
else if (chnl < 6) /* Channel 3-5 */
|
2018-09-19 14:40:00 -06:00
|
|
|
*group = 1;
|
2018-09-19 14:39:58 -06:00
|
|
|
else if (chnl < 9) /* Channel 6-8 */
|
2018-09-19 14:40:00 -06:00
|
|
|
*group = 2;
|
2018-09-19 14:39:58 -06:00
|
|
|
else if (chnl < 12) /* Channel 9-11 */
|
2018-09-19 14:40:00 -06:00
|
|
|
*group = 3;
|
2018-09-19 14:39:58 -06:00
|
|
|
else if (chnl < 14) /* Channel 12-13 */
|
2018-09-19 14:40:00 -06:00
|
|
|
*group = 4;
|
2018-09-19 14:39:58 -06:00
|
|
|
else if (chnl == 14) /* Channel 14 */
|
2018-09-19 14:40:00 -06:00
|
|
|
*group = 5;
|
2013-08-21 21:33:56 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
void Hal_ReadPowerSavingMode88E(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
|
|
|
|
{
|
|
|
|
if (AutoLoadFail) {
|
|
|
|
padapter->pwrctrlpriv.bHWPowerdown = false;
|
|
|
|
padapter->pwrctrlpriv.bSupportRemoteWakeup = false;
|
|
|
|
} else {
|
|
|
|
/* hw power down mode selection , 0:rf-off / 1:power down */
|
|
|
|
|
|
|
|
if (padapter->registrypriv.hwpdn_mode == 2)
|
2015-10-18 23:51:41 -06:00
|
|
|
padapter->pwrctrlpriv.bHWPowerdown = (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & BIT(4));
|
2013-08-21 21:33:56 -06:00
|
|
|
else
|
|
|
|
padapter->pwrctrlpriv.bHWPowerdown = padapter->registrypriv.hwpdn_mode;
|
|
|
|
|
|
|
|
/* decide hw if support remote wakeup function */
|
|
|
|
/* if hw supported, 8051 (SIE) will generate WeakUP signal(D+/D- toggle) when autoresume */
|
2015-10-18 23:51:41 -06:00
|
|
|
padapter->pwrctrlpriv.bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT(1)) ? true : false;
|
2013-08-21 21:33:56 -06:00
|
|
|
|
|
|
|
DBG_88E("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) , bSupportRemoteWakeup(%x)\n", __func__,
|
2017-03-30 14:49:33 -06:00
|
|
|
padapter->pwrctrlpriv.bHWPwrPindetect, padapter->pwrctrlpriv.bHWPowerdown, padapter->pwrctrlpriv.bSupportRemoteWakeup);
|
2013-08-21 21:33:56 -06:00
|
|
|
|
|
|
|
DBG_88E("### PS params => power_mgnt(%x), usbss_enable(%x) ###\n", padapter->registrypriv.power_mgnt, padapter->registrypriv.usbss_enable);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *PROMContent, bool AutoLoadFail)
|
|
|
|
{
|
2016-09-18 11:28:06 -06:00
|
|
|
struct hal_data_8188e *pHalData = padapter->HalData;
|
2013-08-21 21:33:56 -06:00
|
|
|
struct txpowerinfo24g pwrInfo24G;
|
2016-10-07 12:01:17 -06:00
|
|
|
u8 ch, group;
|
2018-09-19 14:39:59 -06:00
|
|
|
u8 TxCount;
|
2013-08-21 21:33:56 -06:00
|
|
|
|
|
|
|
Hal_ReadPowerValueFromPROM_8188E(&pwrInfo24G, PROMContent, AutoLoadFail);
|
|
|
|
|
|
|
|
if (!AutoLoadFail)
|
|
|
|
pHalData->bTXPowerDataReadFromEEPORM = true;
|
|
|
|
|
2016-10-07 12:01:17 -06:00
|
|
|
for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
|
2018-09-19 14:39:59 -06:00
|
|
|
Hal_GetChnlGroup88E(ch, &group);
|
|
|
|
pHalData->Index24G_CCK_Base[0][ch] = pwrInfo24G.IndexCCK_Base[0][group];
|
|
|
|
if (ch == 14)
|
|
|
|
pHalData->Index24G_BW40_Base[0][ch] = pwrInfo24G.IndexBW40_Base[0][4];
|
|
|
|
else
|
|
|
|
pHalData->Index24G_BW40_Base[0][ch] = pwrInfo24G.IndexBW40_Base[0][group];
|
|
|
|
|
|
|
|
DBG_88E("======= Path %d, Channel %d =======\n", 0, ch);
|
|
|
|
DBG_88E("Index24G_CCK_Base[%d][%d] = 0x%x\n", 0, ch, pHalData->Index24G_CCK_Base[0][ch]);
|
|
|
|
DBG_88E("Index24G_BW40_Base[%d][%d] = 0x%x\n", 0, ch, pHalData->Index24G_BW40_Base[0][ch]);
|
2013-08-21 21:33:56 -06:00
|
|
|
}
|
2016-10-07 12:01:17 -06:00
|
|
|
for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
|
|
|
|
pHalData->CCK_24G_Diff[0][TxCount] = pwrInfo24G.CCK_Diff[0][TxCount];
|
|
|
|
pHalData->OFDM_24G_Diff[0][TxCount] = pwrInfo24G.OFDM_Diff[0][TxCount];
|
|
|
|
pHalData->BW20_24G_Diff[0][TxCount] = pwrInfo24G.BW20_Diff[0][TxCount];
|
|
|
|
pHalData->BW40_24G_Diff[0][TxCount] = pwrInfo24G.BW40_Diff[0][TxCount];
|
|
|
|
DBG_88E("======= TxCount %d =======\n", TxCount);
|
|
|
|
DBG_88E("CCK_24G_Diff[%d][%d] = %d\n", 0, TxCount, pHalData->CCK_24G_Diff[0][TxCount]);
|
|
|
|
DBG_88E("OFDM_24G_Diff[%d][%d] = %d\n", 0, TxCount, pHalData->OFDM_24G_Diff[0][TxCount]);
|
|
|
|
DBG_88E("BW20_24G_Diff[%d][%d] = %d\n", 0, TxCount, pHalData->BW20_24G_Diff[0][TxCount]);
|
|
|
|
DBG_88E("BW40_24G_Diff[%d][%d] = %d\n", 0, TxCount, pHalData->BW40_24G_Diff[0][TxCount]);
|
|
|
|
}
|
2013-08-21 21:33:56 -06:00
|
|
|
|
|
|
|
/* 2010/10/19 MH Add Regulator recognize for CU. */
|
|
|
|
if (!AutoLoadFail) {
|
|
|
|
pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_88E]&0x7); /* bit0~2 */
|
|
|
|
if (PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
|
|
|
|
pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION&0x7); /* bit0~2 */
|
|
|
|
} else {
|
|
|
|
pHalData->EEPROMRegulatory = 0;
|
|
|
|
}
|
|
|
|
DBG_88E("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory);
|
|
|
|
}
|
|
|
|
|
|
|
|
void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo, bool AutoLoadFail)
|
|
|
|
{
|
2016-09-18 11:28:06 -06:00
|
|
|
struct hal_data_8188e *pHalData = pAdapter->HalData;
|
2013-08-21 21:33:56 -06:00
|
|
|
|
|
|
|
if (!AutoLoadFail) {
|
|
|
|
pHalData->CrystalCap = hwinfo[EEPROM_XTAL_88E];
|
|
|
|
if (pHalData->CrystalCap == 0xFF)
|
|
|
|
pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E;
|
|
|
|
} else {
|
|
|
|
pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E;
|
|
|
|
}
|
|
|
|
DBG_88E("CrystalCap: 0x%2x\n", pHalData->CrystalCap);
|
|
|
|
}
|
|
|
|
|
|
|
|
void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo, bool AutoLoadFail)
|
|
|
|
{
|
2016-09-18 11:28:06 -06:00
|
|
|
struct hal_data_8188e *pHalData = pAdapter->HalData;
|
2013-08-21 21:33:56 -06:00
|
|
|
|
|
|
|
if (!AutoLoadFail)
|
2015-03-03 22:31:56 -07:00
|
|
|
pHalData->BoardType = (hwinfo[EEPROM_RF_BOARD_OPTION_88E]
|
|
|
|
& 0xE0) >> 5;
|
2013-08-21 21:33:56 -06:00
|
|
|
else
|
|
|
|
pHalData->BoardType = 0;
|
|
|
|
DBG_88E("Board Type: 0x%2x\n", pHalData->BoardType);
|
|
|
|
}
|
|
|
|
|
|
|
|
void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
|
|
|
|
{
|
2016-09-18 11:28:06 -06:00
|
|
|
struct hal_data_8188e *pHalData = padapter->HalData;
|
2013-08-21 21:33:56 -06:00
|
|
|
|
|
|
|
if (!AutoLoadFail) {
|
|
|
|
pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_88E];
|
|
|
|
if (pHalData->EEPROMVersion == 0xFF)
|
|
|
|
pHalData->EEPROMVersion = EEPROM_Default_Version;
|
|
|
|
} else {
|
|
|
|
pHalData->EEPROMVersion = 1;
|
|
|
|
}
|
|
|
|
RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
|
|
|
|
("Hal_EfuseParseEEPROMVer(), EEVer = %d\n",
|
|
|
|
pHalData->EEPROMVersion));
|
|
|
|
}
|
|
|
|
|
|
|
|
void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
|
|
|
|
{
|
|
|
|
padapter->mlmepriv.ChannelPlan =
|
2018-10-14 04:17:38 -06:00
|
|
|
hal_com_get_channel_plan(hwinfo ? hwinfo[EEPROM_ChannelPlan_88E] : 0xFF,
|
2013-08-21 21:33:56 -06:00
|
|
|
padapter->registrypriv.channel_plan,
|
|
|
|
RT_CHANNEL_DOMAIN_WORLD_WIDE_13, AutoLoadFail);
|
|
|
|
|
|
|
|
DBG_88E("mlmepriv.ChannelPlan = 0x%02x\n", padapter->mlmepriv.ChannelPlan);
|
|
|
|
}
|
|
|
|
|
|
|
|
void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail)
|
|
|
|
{
|
2016-09-18 11:28:06 -06:00
|
|
|
struct hal_data_8188e *pHalData = padapter->HalData;
|
2013-08-21 21:33:56 -06:00
|
|
|
|
|
|
|
if (!AutoLoadFail) {
|
|
|
|
pHalData->EEPROMCustomerID = hwinfo[EEPROM_CUSTOMERID_88E];
|
|
|
|
} else {
|
|
|
|
pHalData->EEPROMCustomerID = 0;
|
|
|
|
pHalData->EEPROMSubCustomerID = 0;
|
|
|
|
}
|
|
|
|
DBG_88E("EEPROM Customer ID: 0x%2x\n", pHalData->EEPROMCustomerID);
|
|
|
|
}
|
|
|
|
|
|
|
|
void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter, u8 *PROMContent, bool AutoLoadFail)
|
|
|
|
{
|
2016-09-18 11:28:06 -06:00
|
|
|
struct hal_data_8188e *pHalData = pAdapter->HalData;
|
2013-08-21 21:33:56 -06:00
|
|
|
struct registry_priv *registry_par = &pAdapter->registrypriv;
|
|
|
|
|
|
|
|
if (!AutoLoadFail) {
|
|
|
|
/* Antenna Diversity setting. */
|
|
|
|
if (registry_par->antdiv_cfg == 2) { /* 2:By EFUSE */
|
|
|
|
pHalData->AntDivCfg = (PROMContent[EEPROM_RF_BOARD_OPTION_88E]&0x18)>>3;
|
|
|
|
if (PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
|
2013-11-07 15:13:47 -07:00
|
|
|
pHalData->AntDivCfg = (EEPROM_DEFAULT_BOARD_OPTION&0x18)>>3;
|
2013-08-21 21:33:56 -06:00
|
|
|
} else {
|
|
|
|
pHalData->AntDivCfg = registry_par->antdiv_cfg; /* 0:OFF , 1:ON, 2:By EFUSE */
|
|
|
|
}
|
|
|
|
|
|
|
|
if (registry_par->antdiv_type == 0) {
|
|
|
|
/* If TRxAntDivType is AUTO in advanced setting, use EFUSE value instead. */
|
|
|
|
pHalData->TRxAntDivType = PROMContent[EEPROM_RF_ANTENNA_OPT_88E];
|
|
|
|
if (pHalData->TRxAntDivType == 0xFF)
|
|
|
|
pHalData->TRxAntDivType = CG_TRX_HW_ANTDIV; /* For 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) */
|
|
|
|
} else {
|
|
|
|
pHalData->TRxAntDivType = registry_par->antdiv_type;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pHalData->TRxAntDivType == CG_TRX_HW_ANTDIV || pHalData->TRxAntDivType == CGCS_RX_HW_ANTDIV)
|
|
|
|
pHalData->AntDivCfg = 1; /* 0xC1[3] is ignored. */
|
|
|
|
} else {
|
|
|
|
pHalData->AntDivCfg = 0;
|
|
|
|
pHalData->TRxAntDivType = pHalData->TRxAntDivType; /* The value in the driver setting of device manager. */
|
|
|
|
}
|
|
|
|
DBG_88E("EEPROM : AntDivCfg = %x, TRxAntDivType = %x\n", pHalData->AntDivCfg, pHalData->TRxAntDivType);
|
|
|
|
}
|
|
|
|
|
|
|
|
void Hal_ReadThermalMeter_88E(struct adapter *Adapter, u8 *PROMContent, bool AutoloadFail)
|
|
|
|
{
|
2016-09-18 11:28:06 -06:00
|
|
|
struct hal_data_8188e *pHalData = Adapter->HalData;
|
2013-08-21 21:33:56 -06:00
|
|
|
|
|
|
|
/* ThermalMeter from EEPROM */
|
|
|
|
if (!AutoloadFail)
|
|
|
|
pHalData->EEPROMThermalMeter = PROMContent[EEPROM_THERMAL_METER_88E];
|
|
|
|
else
|
|
|
|
pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E;
|
|
|
|
|
|
|
|
if (pHalData->EEPROMThermalMeter == 0xff || AutoloadFail) {
|
|
|
|
pHalData->bAPKThermalMeterIgnore = true;
|
|
|
|
pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E;
|
|
|
|
}
|
|
|
|
DBG_88E("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter);
|
|
|
|
}
|