2007-02-14 01:33:09 -07:00
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/*
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* Driver for Atmel AT32 and AT91 SPI Controllers
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*
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* Copyright (C) 2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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2013-04-02 23:59:19 -06:00
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#include <linux/dmaengine.h>
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2007-02-14 01:33:09 -07:00
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/spi/spi.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2013-04-02 23:59:19 -06:00
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#include <linux/platform_data/dma-atmel.h>
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2012-11-23 05:44:39 -07:00
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#include <linux/of.h>
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2007-02-14 01:33:09 -07:00
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2013-03-19 01:42:15 -06:00
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#include <linux/io.h>
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#include <linux/gpio.h>
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2016-11-08 10:48:52 -07:00
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#include <linux/of_gpio.h>
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2014-03-04 18:58:49 -07:00
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#include <linux/pinctrl/consumer.h>
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2014-10-16 03:23:10 -06:00
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#include <linux/pm_runtime.h>
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2007-02-20 14:58:19 -07:00
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2011-06-06 01:16:30 -06:00
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/* SPI register offsets */
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#define SPI_CR 0x0000
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#define SPI_MR 0x0004
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#define SPI_RDR 0x0008
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#define SPI_TDR 0x000c
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#define SPI_SR 0x0010
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#define SPI_IER 0x0014
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#define SPI_IDR 0x0018
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#define SPI_IMR 0x001c
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#define SPI_CSR0 0x0030
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#define SPI_CSR1 0x0034
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#define SPI_CSR2 0x0038
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#define SPI_CSR3 0x003c
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spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
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#define SPI_FMR 0x0040
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#define SPI_FLR 0x0044
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2013-03-19 01:42:15 -06:00
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#define SPI_VERSION 0x00fc
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2011-06-06 01:16:30 -06:00
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#define SPI_RPR 0x0100
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#define SPI_RCR 0x0104
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#define SPI_TPR 0x0108
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#define SPI_TCR 0x010c
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#define SPI_RNPR 0x0110
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#define SPI_RNCR 0x0114
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#define SPI_TNPR 0x0118
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#define SPI_TNCR 0x011c
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#define SPI_PTCR 0x0120
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#define SPI_PTSR 0x0124
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/* Bitfields in CR */
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#define SPI_SPIEN_OFFSET 0
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#define SPI_SPIEN_SIZE 1
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#define SPI_SPIDIS_OFFSET 1
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#define SPI_SPIDIS_SIZE 1
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#define SPI_SWRST_OFFSET 7
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#define SPI_SWRST_SIZE 1
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#define SPI_LASTXFER_OFFSET 24
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#define SPI_LASTXFER_SIZE 1
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spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
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#define SPI_TXFCLR_OFFSET 16
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#define SPI_TXFCLR_SIZE 1
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#define SPI_RXFCLR_OFFSET 17
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#define SPI_RXFCLR_SIZE 1
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#define SPI_FIFOEN_OFFSET 30
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#define SPI_FIFOEN_SIZE 1
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#define SPI_FIFODIS_OFFSET 31
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#define SPI_FIFODIS_SIZE 1
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2011-06-06 01:16:30 -06:00
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/* Bitfields in MR */
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#define SPI_MSTR_OFFSET 0
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#define SPI_MSTR_SIZE 1
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#define SPI_PS_OFFSET 1
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#define SPI_PS_SIZE 1
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#define SPI_PCSDEC_OFFSET 2
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#define SPI_PCSDEC_SIZE 1
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#define SPI_FDIV_OFFSET 3
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#define SPI_FDIV_SIZE 1
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#define SPI_MODFDIS_OFFSET 4
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#define SPI_MODFDIS_SIZE 1
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2013-03-19 01:42:15 -06:00
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#define SPI_WDRBT_OFFSET 5
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#define SPI_WDRBT_SIZE 1
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2011-06-06 01:16:30 -06:00
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#define SPI_LLB_OFFSET 7
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#define SPI_LLB_SIZE 1
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#define SPI_PCS_OFFSET 16
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#define SPI_PCS_SIZE 4
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#define SPI_DLYBCS_OFFSET 24
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#define SPI_DLYBCS_SIZE 8
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/* Bitfields in RDR */
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#define SPI_RD_OFFSET 0
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#define SPI_RD_SIZE 16
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/* Bitfields in TDR */
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#define SPI_TD_OFFSET 0
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#define SPI_TD_SIZE 16
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/* Bitfields in SR */
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#define SPI_RDRF_OFFSET 0
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#define SPI_RDRF_SIZE 1
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#define SPI_TDRE_OFFSET 1
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#define SPI_TDRE_SIZE 1
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#define SPI_MODF_OFFSET 2
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#define SPI_MODF_SIZE 1
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#define SPI_OVRES_OFFSET 3
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#define SPI_OVRES_SIZE 1
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#define SPI_ENDRX_OFFSET 4
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#define SPI_ENDRX_SIZE 1
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#define SPI_ENDTX_OFFSET 5
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#define SPI_ENDTX_SIZE 1
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#define SPI_RXBUFF_OFFSET 6
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#define SPI_RXBUFF_SIZE 1
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#define SPI_TXBUFE_OFFSET 7
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#define SPI_TXBUFE_SIZE 1
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#define SPI_NSSR_OFFSET 8
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#define SPI_NSSR_SIZE 1
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#define SPI_TXEMPTY_OFFSET 9
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#define SPI_TXEMPTY_SIZE 1
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#define SPI_SPIENS_OFFSET 16
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#define SPI_SPIENS_SIZE 1
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spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
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#define SPI_TXFEF_OFFSET 24
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#define SPI_TXFEF_SIZE 1
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#define SPI_TXFFF_OFFSET 25
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#define SPI_TXFFF_SIZE 1
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#define SPI_TXFTHF_OFFSET 26
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#define SPI_TXFTHF_SIZE 1
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#define SPI_RXFEF_OFFSET 27
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#define SPI_RXFEF_SIZE 1
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#define SPI_RXFFF_OFFSET 28
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#define SPI_RXFFF_SIZE 1
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#define SPI_RXFTHF_OFFSET 29
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#define SPI_RXFTHF_SIZE 1
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#define SPI_TXFPTEF_OFFSET 30
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#define SPI_TXFPTEF_SIZE 1
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#define SPI_RXFPTEF_OFFSET 31
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#define SPI_RXFPTEF_SIZE 1
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2011-06-06 01:16:30 -06:00
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/* Bitfields in CSR0 */
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#define SPI_CPOL_OFFSET 0
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#define SPI_CPOL_SIZE 1
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#define SPI_NCPHA_OFFSET 1
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#define SPI_NCPHA_SIZE 1
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#define SPI_CSAAT_OFFSET 3
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#define SPI_CSAAT_SIZE 1
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#define SPI_BITS_OFFSET 4
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#define SPI_BITS_SIZE 4
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#define SPI_SCBR_OFFSET 8
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#define SPI_SCBR_SIZE 8
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#define SPI_DLYBS_OFFSET 16
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#define SPI_DLYBS_SIZE 8
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#define SPI_DLYBCT_OFFSET 24
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#define SPI_DLYBCT_SIZE 8
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/* Bitfields in RCR */
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#define SPI_RXCTR_OFFSET 0
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#define SPI_RXCTR_SIZE 16
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/* Bitfields in TCR */
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#define SPI_TXCTR_OFFSET 0
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#define SPI_TXCTR_SIZE 16
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/* Bitfields in RNCR */
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#define SPI_RXNCR_OFFSET 0
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#define SPI_RXNCR_SIZE 16
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/* Bitfields in TNCR */
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#define SPI_TXNCR_OFFSET 0
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#define SPI_TXNCR_SIZE 16
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/* Bitfields in PTCR */
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#define SPI_RXTEN_OFFSET 0
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#define SPI_RXTEN_SIZE 1
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#define SPI_RXTDIS_OFFSET 1
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#define SPI_RXTDIS_SIZE 1
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#define SPI_TXTEN_OFFSET 8
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#define SPI_TXTEN_SIZE 1
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#define SPI_TXTDIS_OFFSET 9
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#define SPI_TXTDIS_SIZE 1
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spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
|
|
|
/* Bitfields in FMR */
|
|
|
|
#define SPI_TXRDYM_OFFSET 0
|
|
|
|
#define SPI_TXRDYM_SIZE 2
|
|
|
|
#define SPI_RXRDYM_OFFSET 4
|
|
|
|
#define SPI_RXRDYM_SIZE 2
|
|
|
|
#define SPI_TXFTHRES_OFFSET 16
|
|
|
|
#define SPI_TXFTHRES_SIZE 6
|
|
|
|
#define SPI_RXFTHRES_OFFSET 24
|
|
|
|
#define SPI_RXFTHRES_SIZE 6
|
|
|
|
|
|
|
|
/* Bitfields in FLR */
|
|
|
|
#define SPI_TXFL_OFFSET 0
|
|
|
|
#define SPI_TXFL_SIZE 6
|
|
|
|
#define SPI_RXFL_OFFSET 16
|
|
|
|
#define SPI_RXFL_SIZE 6
|
|
|
|
|
2011-06-06 01:16:30 -06:00
|
|
|
/* Constants for BITS */
|
|
|
|
#define SPI_BITS_8_BPT 0
|
|
|
|
#define SPI_BITS_9_BPT 1
|
|
|
|
#define SPI_BITS_10_BPT 2
|
|
|
|
#define SPI_BITS_11_BPT 3
|
|
|
|
#define SPI_BITS_12_BPT 4
|
|
|
|
#define SPI_BITS_13_BPT 5
|
|
|
|
#define SPI_BITS_14_BPT 6
|
|
|
|
#define SPI_BITS_15_BPT 7
|
|
|
|
#define SPI_BITS_16_BPT 8
|
spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
|
|
|
#define SPI_ONE_DATA 0
|
|
|
|
#define SPI_TWO_DATA 1
|
|
|
|
#define SPI_FOUR_DATA 2
|
2011-06-06 01:16:30 -06:00
|
|
|
|
|
|
|
/* Bit manipulation macros */
|
|
|
|
#define SPI_BIT(name) \
|
|
|
|
(1 << SPI_##name##_OFFSET)
|
2013-09-10 05:36:27 -06:00
|
|
|
#define SPI_BF(name, value) \
|
2011-06-06 01:16:30 -06:00
|
|
|
(((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
|
2013-09-10 05:36:27 -06:00
|
|
|
#define SPI_BFEXT(name, value) \
|
2011-06-06 01:16:30 -06:00
|
|
|
(((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
|
2013-09-10 05:36:27 -06:00
|
|
|
#define SPI_BFINS(name, value, old) \
|
|
|
|
(((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
|
|
|
|
| SPI_BF(name, value))
|
2011-06-06 01:16:30 -06:00
|
|
|
|
|
|
|
/* Register access macros */
|
2015-03-18 09:53:08 -06:00
|
|
|
#ifdef CONFIG_AVR32
|
2013-09-10 05:36:27 -06:00
|
|
|
#define spi_readl(port, reg) \
|
2011-06-06 01:16:30 -06:00
|
|
|
__raw_readl((port)->regs + SPI_##reg)
|
2013-09-10 05:36:27 -06:00
|
|
|
#define spi_writel(port, reg, value) \
|
2011-06-06 01:16:30 -06:00
|
|
|
__raw_writel((value), (port)->regs + SPI_##reg)
|
spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
|
|
|
|
|
|
|
#define spi_readw(port, reg) \
|
|
|
|
__raw_readw((port)->regs + SPI_##reg)
|
|
|
|
#define spi_writew(port, reg, value) \
|
|
|
|
__raw_writew((value), (port)->regs + SPI_##reg)
|
|
|
|
|
|
|
|
#define spi_readb(port, reg) \
|
|
|
|
__raw_readb((port)->regs + SPI_##reg)
|
|
|
|
#define spi_writeb(port, reg, value) \
|
|
|
|
__raw_writeb((value), (port)->regs + SPI_##reg)
|
2015-03-18 09:53:08 -06:00
|
|
|
#else
|
|
|
|
#define spi_readl(port, reg) \
|
|
|
|
readl_relaxed((port)->regs + SPI_##reg)
|
|
|
|
#define spi_writel(port, reg, value) \
|
|
|
|
writel_relaxed((value), (port)->regs + SPI_##reg)
|
spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
|
|
|
|
|
|
|
#define spi_readw(port, reg) \
|
|
|
|
readw_relaxed((port)->regs + SPI_##reg)
|
|
|
|
#define spi_writew(port, reg, value) \
|
|
|
|
writew_relaxed((value), (port)->regs + SPI_##reg)
|
|
|
|
|
|
|
|
#define spi_readb(port, reg) \
|
|
|
|
readb_relaxed((port)->regs + SPI_##reg)
|
|
|
|
#define spi_writeb(port, reg, value) \
|
|
|
|
writeb_relaxed((value), (port)->regs + SPI_##reg)
|
2015-03-18 09:53:08 -06:00
|
|
|
#endif
|
2013-04-02 23:59:19 -06:00
|
|
|
/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
|
|
|
|
* cache operations; better heuristics consider wordsize and bitrate.
|
|
|
|
*/
|
|
|
|
#define DMA_MIN_BYTES 16
|
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
#define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
|
|
|
|
|
2014-10-16 03:23:10 -06:00
|
|
|
#define AUTOSUSPEND_TIMEOUT 2000
|
|
|
|
|
2013-03-19 01:42:15 -06:00
|
|
|
struct atmel_spi_caps {
|
|
|
|
bool is_spi2;
|
|
|
|
bool has_wdrbt;
|
|
|
|
bool has_dma_support;
|
2017-06-23 09:39:16 -06:00
|
|
|
bool has_pdc_support;
|
2013-03-19 01:42:15 -06:00
|
|
|
};
|
2007-02-14 01:33:09 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The core SPI transfer engine just talks to a register bank to set up
|
|
|
|
* DMA transfers; transfer queue progress is driven by IRQs. The clock
|
|
|
|
* framework provides the base clock, subdivided for each spi_device.
|
|
|
|
*/
|
|
|
|
struct atmel_spi {
|
|
|
|
spinlock_t lock;
|
2013-04-02 23:58:36 -06:00
|
|
|
unsigned long flags;
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2013-04-02 23:57:42 -06:00
|
|
|
phys_addr_t phybase;
|
2007-02-14 01:33:09 -07:00
|
|
|
void __iomem *regs;
|
|
|
|
int irq;
|
|
|
|
struct clk *clk;
|
|
|
|
struct platform_device *pdev;
|
2016-11-14 08:13:20 -07:00
|
|
|
unsigned long spi_clk;
|
2007-02-14 01:33:09 -07:00
|
|
|
|
|
|
|
struct spi_transfer *current_transfer;
|
2014-03-26 19:26:38 -06:00
|
|
|
int current_remaining_bytes;
|
2013-03-19 01:45:01 -06:00
|
|
|
int done_status;
|
2017-12-19 08:17:59 -07:00
|
|
|
dma_addr_t dma_addr_rx_bbuf;
|
|
|
|
dma_addr_t dma_addr_tx_bbuf;
|
|
|
|
void *addr_rx_bbuf;
|
|
|
|
void *addr_tx_bbuf;
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
struct completion xfer_completion;
|
|
|
|
|
2013-03-19 01:42:15 -06:00
|
|
|
struct atmel_spi_caps caps;
|
2013-04-02 23:59:19 -06:00
|
|
|
|
|
|
|
bool use_dma;
|
|
|
|
bool use_pdc;
|
2015-06-09 05:53:52 -06:00
|
|
|
bool use_cs_gpios;
|
2014-01-08 22:19:15 -07:00
|
|
|
|
|
|
|
bool keep_cs;
|
|
|
|
bool cs_active;
|
spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
|
|
|
|
|
|
|
u32 fifo_size;
|
2007-02-14 01:33:09 -07:00
|
|
|
};
|
|
|
|
|
2009-01-06 15:41:43 -07:00
|
|
|
/* Controller-specific per-slave state */
|
|
|
|
struct atmel_spi_device {
|
|
|
|
unsigned int npcs_pin;
|
|
|
|
u32 csr;
|
|
|
|
};
|
|
|
|
|
2016-11-24 04:24:58 -07:00
|
|
|
#define SPI_MAX_DMA_XFER 65535 /* true for both PDC and DMA */
|
2007-02-14 01:33:09 -07:00
|
|
|
#define INVALID_DMA_ADDRESS 0xffffffff
|
|
|
|
|
2009-01-06 15:41:42 -07:00
|
|
|
/*
|
|
|
|
* Version 2 of the SPI controller has
|
|
|
|
* - CR.LASTXFER
|
|
|
|
* - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
|
|
|
|
* - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
|
|
|
|
* - SPI_CSRx.CSAAT
|
|
|
|
* - SPI_CSRx.SBCR allows faster clocking
|
|
|
|
*/
|
2013-03-19 01:42:15 -06:00
|
|
|
static bool atmel_spi_is_v2(struct atmel_spi *as)
|
2009-01-06 15:41:42 -07:00
|
|
|
{
|
2013-03-19 01:42:15 -06:00
|
|
|
return as->caps.is_spi2;
|
2009-01-06 15:41:42 -07:00
|
|
|
}
|
|
|
|
|
2007-02-14 01:33:09 -07:00
|
|
|
/*
|
|
|
|
* Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
|
|
|
|
* they assume that spi slave device state will not change on deselect, so
|
2007-07-17 05:04:08 -06:00
|
|
|
* that automagic deselection is OK. ("NPCSx rises if no data is to be
|
|
|
|
* transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
|
|
|
|
* controllers have CSAAT and friends.
|
2007-02-14 01:33:09 -07:00
|
|
|
*
|
2007-07-17 05:04:08 -06:00
|
|
|
* Since the CSAAT functionality is a bit weird on newer controllers as
|
|
|
|
* well, we use GPIO to control nCSx pins on all controllers, updating
|
|
|
|
* MR.PCS to avoid confusing the controller. Using GPIOs also lets us
|
|
|
|
* support active-high chipselects despite the controller's belief that
|
|
|
|
* only active-low devices/systems exists.
|
|
|
|
*
|
|
|
|
* However, at91rm9200 has a second erratum whereby nCS0 doesn't work
|
|
|
|
* right when driven with GPIO. ("Mode Fault does not allow more than one
|
|
|
|
* Master on Chip Select 0.") No workaround exists for that ... so for
|
|
|
|
* nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
|
|
|
|
* and (c) will trigger that first erratum in some cases.
|
2007-02-14 01:33:09 -07:00
|
|
|
*/
|
|
|
|
|
2007-07-17 05:04:08 -06:00
|
|
|
static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
|
2007-02-14 01:33:09 -07:00
|
|
|
{
|
2009-01-06 15:41:43 -07:00
|
|
|
struct atmel_spi_device *asd = spi->controller_state;
|
2007-02-14 01:33:09 -07:00
|
|
|
unsigned active = spi->mode & SPI_CS_HIGH;
|
2007-07-17 05:04:08 -06:00
|
|
|
u32 mr;
|
|
|
|
|
2013-03-19 01:42:15 -06:00
|
|
|
if (atmel_spi_is_v2(as)) {
|
2013-03-19 01:43:01 -06:00
|
|
|
spi_writel(as, CSR0 + 4 * spi->chip_select, asd->csr);
|
|
|
|
/* For the low SPI version, there is a issue that PDC transfer
|
|
|
|
* on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
|
2009-01-06 15:41:43 -07:00
|
|
|
*/
|
|
|
|
spi_writel(as, CSR0, asd->csr);
|
2013-03-19 01:42:15 -06:00
|
|
|
if (as->caps.has_wdrbt) {
|
2013-03-19 01:43:01 -06:00
|
|
|
spi_writel(as, MR,
|
|
|
|
SPI_BF(PCS, ~(0x01 << spi->chip_select))
|
|
|
|
| SPI_BIT(WDRBT)
|
|
|
|
| SPI_BIT(MODFDIS)
|
|
|
|
| SPI_BIT(MSTR));
|
2013-03-19 01:42:15 -06:00
|
|
|
} else {
|
2013-03-19 01:43:01 -06:00
|
|
|
spi_writel(as, MR,
|
|
|
|
SPI_BF(PCS, ~(0x01 << spi->chip_select))
|
|
|
|
| SPI_BIT(MODFDIS)
|
|
|
|
| SPI_BIT(MSTR));
|
2013-03-19 01:42:15 -06:00
|
|
|
}
|
2013-04-02 23:59:19 -06:00
|
|
|
|
2009-01-06 15:41:43 -07:00
|
|
|
mr = spi_readl(as, MR);
|
2015-06-09 05:53:52 -06:00
|
|
|
if (as->use_cs_gpios)
|
|
|
|
gpio_set_value(asd->npcs_pin, active);
|
2009-01-06 15:41:43 -07:00
|
|
|
} else {
|
|
|
|
u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
|
|
|
|
int i;
|
|
|
|
u32 csr;
|
|
|
|
|
|
|
|
/* Make sure clock polarity is correct */
|
|
|
|
for (i = 0; i < spi->master->num_chipselect; i++) {
|
|
|
|
csr = spi_readl(as, CSR0 + 4 * i);
|
|
|
|
if ((csr ^ cpol) & SPI_BIT(CPOL))
|
|
|
|
spi_writel(as, CSR0 + 4 * i,
|
|
|
|
csr ^ SPI_BIT(CPOL));
|
|
|
|
}
|
|
|
|
|
|
|
|
mr = spi_readl(as, MR);
|
|
|
|
mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
|
2015-06-09 05:53:52 -06:00
|
|
|
if (as->use_cs_gpios && spi->chip_select != 0)
|
2009-01-06 15:41:43 -07:00
|
|
|
gpio_set_value(asd->npcs_pin, active);
|
|
|
|
spi_writel(as, MR, mr);
|
|
|
|
}
|
2007-07-17 05:04:08 -06:00
|
|
|
|
|
|
|
dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
|
2009-01-06 15:41:43 -07:00
|
|
|
asd->npcs_pin, active ? " (high)" : "",
|
2007-07-17 05:04:08 -06:00
|
|
|
mr);
|
2007-02-14 01:33:09 -07:00
|
|
|
}
|
|
|
|
|
2007-07-17 05:04:08 -06:00
|
|
|
static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
|
2007-02-14 01:33:09 -07:00
|
|
|
{
|
2009-01-06 15:41:43 -07:00
|
|
|
struct atmel_spi_device *asd = spi->controller_state;
|
2007-02-14 01:33:09 -07:00
|
|
|
unsigned active = spi->mode & SPI_CS_HIGH;
|
2007-07-17 05:04:08 -06:00
|
|
|
u32 mr;
|
|
|
|
|
|
|
|
/* only deactivate *this* device; sometimes transfers to
|
|
|
|
* another device may be active when this routine is called.
|
|
|
|
*/
|
|
|
|
mr = spi_readl(as, MR);
|
|
|
|
if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
|
|
|
|
mr = SPI_BFINS(PCS, 0xf, mr);
|
|
|
|
spi_writel(as, MR, mr);
|
|
|
|
}
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2007-07-17 05:04:08 -06:00
|
|
|
dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
|
2009-01-06 15:41:43 -07:00
|
|
|
asd->npcs_pin, active ? " (low)" : "",
|
2007-07-17 05:04:08 -06:00
|
|
|
mr);
|
|
|
|
|
2015-06-09 05:53:52 -06:00
|
|
|
if (!as->use_cs_gpios)
|
|
|
|
spi_writel(as, CR, SPI_BIT(LASTXFER));
|
|
|
|
else if (atmel_spi_is_v2(as) || spi->chip_select != 0)
|
2009-01-06 15:41:43 -07:00
|
|
|
gpio_set_value(asd->npcs_pin, !active);
|
2007-02-14 01:33:09 -07:00
|
|
|
}
|
|
|
|
|
2013-07-28 07:32:27 -06:00
|
|
|
static void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock)
|
2013-04-02 23:58:36 -06:00
|
|
|
{
|
|
|
|
spin_lock_irqsave(&as->lock, as->flags);
|
|
|
|
}
|
|
|
|
|
2013-07-28 07:32:27 -06:00
|
|
|
static void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock)
|
2013-04-02 23:58:36 -06:00
|
|
|
{
|
|
|
|
spin_unlock_irqrestore(&as->lock, as->flags);
|
|
|
|
}
|
|
|
|
|
2017-12-19 08:17:59 -07:00
|
|
|
static inline bool atmel_spi_is_vmalloc_xfer(struct spi_transfer *xfer)
|
|
|
|
{
|
|
|
|
return is_vmalloc_addr(xfer->tx_buf) || is_vmalloc_addr(xfer->rx_buf);
|
|
|
|
}
|
|
|
|
|
2013-04-02 23:59:19 -06:00
|
|
|
static inline bool atmel_spi_use_dma(struct atmel_spi *as,
|
|
|
|
struct spi_transfer *xfer)
|
|
|
|
{
|
|
|
|
return as->use_dma && xfer->len >= DMA_MIN_BYTES;
|
|
|
|
}
|
|
|
|
|
2016-11-24 04:24:59 -07:00
|
|
|
static bool atmel_spi_can_dma(struct spi_master *master,
|
|
|
|
struct spi_device *spi,
|
|
|
|
struct spi_transfer *xfer)
|
|
|
|
{
|
|
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
|
|
|
|
2017-12-19 08:17:59 -07:00
|
|
|
if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5))
|
|
|
|
return atmel_spi_use_dma(as, xfer) &&
|
|
|
|
!atmel_spi_is_vmalloc_xfer(xfer);
|
|
|
|
else
|
|
|
|
return atmel_spi_use_dma(as, xfer);
|
|
|
|
|
2016-11-24 04:24:59 -07:00
|
|
|
}
|
|
|
|
|
2013-04-02 23:59:19 -06:00
|
|
|
static int atmel_spi_dma_slave_config(struct atmel_spi *as,
|
|
|
|
struct dma_slave_config *slave_config,
|
|
|
|
u8 bits_per_word)
|
|
|
|
{
|
2016-11-24 04:25:01 -07:00
|
|
|
struct spi_master *master = platform_get_drvdata(as->pdev);
|
2013-04-02 23:59:19 -06:00
|
|
|
int err = 0;
|
|
|
|
|
|
|
|
if (bits_per_word > 8) {
|
|
|
|
slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
|
|
|
|
slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
|
|
|
|
} else {
|
|
|
|
slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
|
|
|
|
slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
|
|
|
|
}
|
|
|
|
|
|
|
|
slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
|
|
|
|
slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
|
|
|
|
slave_config->src_maxburst = 1;
|
|
|
|
slave_config->dst_maxburst = 1;
|
|
|
|
slave_config->device_fc = false;
|
|
|
|
|
spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
|
|
|
/*
|
|
|
|
* This driver uses fixed peripheral select mode (PS bit set to '0' in
|
|
|
|
* the Mode Register).
|
|
|
|
* So according to the datasheet, when FIFOs are available (and
|
|
|
|
* enabled), the Transmit FIFO operates in Multiple Data Mode.
|
|
|
|
* In this mode, up to 2 data, not 4, can be written into the Transmit
|
|
|
|
* Data Register in a single access.
|
|
|
|
* However, the first data has to be written into the lowest 16 bits and
|
|
|
|
* the second data into the highest 16 bits of the Transmit
|
|
|
|
* Data Register. For 8bit data (the most frequent case), it would
|
|
|
|
* require to rework tx_buf so each data would actualy fit 16 bits.
|
|
|
|
* So we'd rather write only one data at the time. Hence the transmit
|
|
|
|
* path works the same whether FIFOs are available (and enabled) or not.
|
|
|
|
*/
|
2013-04-02 23:59:19 -06:00
|
|
|
slave_config->direction = DMA_MEM_TO_DEV;
|
2016-11-24 04:25:01 -07:00
|
|
|
if (dmaengine_slave_config(master->dma_tx, slave_config)) {
|
2013-04-02 23:59:19 -06:00
|
|
|
dev_err(&as->pdev->dev,
|
|
|
|
"failed to configure tx dma channel\n");
|
|
|
|
err = -EINVAL;
|
|
|
|
}
|
|
|
|
|
spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
|
|
|
/*
|
|
|
|
* This driver configures the spi controller for master mode (MSTR bit
|
|
|
|
* set to '1' in the Mode Register).
|
|
|
|
* So according to the datasheet, when FIFOs are available (and
|
|
|
|
* enabled), the Receive FIFO operates in Single Data Mode.
|
|
|
|
* So the receive path works the same whether FIFOs are available (and
|
|
|
|
* enabled) or not.
|
|
|
|
*/
|
2013-04-02 23:59:19 -06:00
|
|
|
slave_config->direction = DMA_DEV_TO_MEM;
|
2016-11-24 04:25:01 -07:00
|
|
|
if (dmaengine_slave_config(master->dma_rx, slave_config)) {
|
2013-04-02 23:59:19 -06:00
|
|
|
dev_err(&as->pdev->dev,
|
|
|
|
"failed to configure rx dma channel\n");
|
|
|
|
err = -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2016-11-24 04:25:01 -07:00
|
|
|
static int atmel_spi_configure_dma(struct spi_master *master,
|
|
|
|
struct atmel_spi *as)
|
2013-04-02 23:59:19 -06:00
|
|
|
{
|
|
|
|
struct dma_slave_config slave_config;
|
2013-05-31 09:01:59 -06:00
|
|
|
struct device *dev = &as->pdev->dev;
|
2013-04-02 23:59:19 -06:00
|
|
|
int err;
|
|
|
|
|
2013-05-31 09:01:59 -06:00
|
|
|
dma_cap_mask_t mask;
|
|
|
|
dma_cap_zero(mask);
|
|
|
|
dma_cap_set(DMA_SLAVE, mask);
|
2013-04-02 23:59:19 -06:00
|
|
|
|
2016-11-24 04:25:01 -07:00
|
|
|
master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
|
|
|
|
if (IS_ERR(master->dma_tx)) {
|
|
|
|
err = PTR_ERR(master->dma_tx);
|
2014-11-14 09:12:54 -07:00
|
|
|
if (err == -EPROBE_DEFER) {
|
|
|
|
dev_warn(dev, "no DMA channel available at the moment\n");
|
2016-11-24 04:25:01 -07:00
|
|
|
goto error_clear;
|
2014-11-14 09:12:54 -07:00
|
|
|
}
|
2013-05-31 09:01:59 -06:00
|
|
|
dev_err(dev,
|
|
|
|
"DMA TX channel not available, SPI unable to use DMA\n");
|
|
|
|
err = -EBUSY;
|
2016-11-24 04:25:01 -07:00
|
|
|
goto error_clear;
|
2013-04-02 23:59:19 -06:00
|
|
|
}
|
2013-05-31 09:01:59 -06:00
|
|
|
|
2014-11-14 09:12:54 -07:00
|
|
|
/*
|
|
|
|
* No reason to check EPROBE_DEFER here since we have already requested
|
|
|
|
* tx channel. If it fails here, it's for another reason.
|
|
|
|
*/
|
2016-11-24 04:25:01 -07:00
|
|
|
master->dma_rx = dma_request_slave_channel(dev, "rx");
|
2013-05-31 09:01:59 -06:00
|
|
|
|
2016-11-24 04:25:01 -07:00
|
|
|
if (!master->dma_rx) {
|
2013-05-31 09:01:59 -06:00
|
|
|
dev_err(dev,
|
|
|
|
"DMA RX channel not available, SPI unable to use DMA\n");
|
2013-04-02 23:59:19 -06:00
|
|
|
err = -EBUSY;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
err = atmel_spi_dma_slave_config(as, &slave_config, 8);
|
|
|
|
if (err)
|
|
|
|
goto error;
|
|
|
|
|
|
|
|
dev_info(&as->pdev->dev,
|
|
|
|
"Using %s (tx) and %s (rx) for DMA transfers\n",
|
2016-11-24 04:25:01 -07:00
|
|
|
dma_chan_name(master->dma_tx),
|
|
|
|
dma_chan_name(master->dma_rx));
|
|
|
|
|
2013-04-02 23:59:19 -06:00
|
|
|
return 0;
|
|
|
|
error:
|
2016-11-24 04:25:01 -07:00
|
|
|
if (master->dma_rx)
|
|
|
|
dma_release_channel(master->dma_rx);
|
|
|
|
if (!IS_ERR(master->dma_tx))
|
|
|
|
dma_release_channel(master->dma_tx);
|
|
|
|
error_clear:
|
|
|
|
master->dma_tx = master->dma_rx = NULL;
|
2013-04-02 23:59:19 -06:00
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2016-11-24 04:25:01 -07:00
|
|
|
static void atmel_spi_stop_dma(struct spi_master *master)
|
2013-04-02 23:59:19 -06:00
|
|
|
{
|
2016-11-24 04:25:01 -07:00
|
|
|
if (master->dma_rx)
|
|
|
|
dmaengine_terminate_all(master->dma_rx);
|
|
|
|
if (master->dma_tx)
|
|
|
|
dmaengine_terminate_all(master->dma_tx);
|
2013-04-02 23:59:19 -06:00
|
|
|
}
|
|
|
|
|
2016-11-24 04:25:01 -07:00
|
|
|
static void atmel_spi_release_dma(struct spi_master *master)
|
2013-04-02 23:59:19 -06:00
|
|
|
{
|
2016-11-24 04:25:01 -07:00
|
|
|
if (master->dma_rx) {
|
|
|
|
dma_release_channel(master->dma_rx);
|
|
|
|
master->dma_rx = NULL;
|
|
|
|
}
|
|
|
|
if (master->dma_tx) {
|
|
|
|
dma_release_channel(master->dma_tx);
|
|
|
|
master->dma_tx = NULL;
|
|
|
|
}
|
2013-04-02 23:59:19 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/* This function is called by the DMA driver from tasklet context */
|
|
|
|
static void dma_callback(void *data)
|
|
|
|
{
|
|
|
|
struct spi_master *master = data;
|
|
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
|
|
|
|
2017-12-19 08:17:59 -07:00
|
|
|
if (is_vmalloc_addr(as->current_transfer->rx_buf) &&
|
|
|
|
IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
|
|
|
|
memcpy(as->current_transfer->rx_buf, as->addr_rx_bbuf,
|
|
|
|
as->current_transfer->len);
|
|
|
|
}
|
2014-01-08 22:19:15 -07:00
|
|
|
complete(&as->xfer_completion);
|
2013-04-02 23:59:19 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
|
|
|
* Next transfer using PIO without FIFO.
|
2013-04-02 23:59:19 -06:00
|
|
|
*/
|
spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
|
|
|
static void atmel_spi_next_xfer_single(struct spi_master *master,
|
|
|
|
struct spi_transfer *xfer)
|
2013-04-02 23:59:19 -06:00
|
|
|
{
|
|
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
2014-01-08 22:19:15 -07:00
|
|
|
unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
|
2013-04-02 23:59:19 -06:00
|
|
|
|
|
|
|
dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
|
|
|
|
|
|
|
|
/* Make sure data is not remaining in RDR */
|
|
|
|
spi_readl(as, RDR);
|
|
|
|
while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
|
|
|
|
spi_readl(as, RDR);
|
|
|
|
cpu_relax();
|
|
|
|
}
|
|
|
|
|
2016-11-24 04:24:58 -07:00
|
|
|
if (xfer->bits_per_word > 8)
|
|
|
|
spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
|
|
|
|
else
|
|
|
|
spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
|
2013-04-02 23:59:19 -06:00
|
|
|
|
|
|
|
dev_dbg(master->dev.parent,
|
2013-05-02 05:25:11 -06:00
|
|
|
" start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
|
|
|
|
xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
|
|
|
|
xfer->bits_per_word);
|
2013-04-02 23:59:19 -06:00
|
|
|
|
|
|
|
/* Enable relevant interrupts */
|
|
|
|
spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
|
|
|
|
}
|
|
|
|
|
spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
|
|
|
/*
|
|
|
|
* Next transfer using PIO with FIFO.
|
|
|
|
*/
|
|
|
|
static void atmel_spi_next_xfer_fifo(struct spi_master *master,
|
|
|
|
struct spi_transfer *xfer)
|
|
|
|
{
|
|
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
|
|
|
u32 current_remaining_data, num_data;
|
|
|
|
u32 offset = xfer->len - as->current_remaining_bytes;
|
|
|
|
const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset);
|
|
|
|
const u8 *bytes = (const u8 *)((u8 *)xfer->tx_buf + offset);
|
|
|
|
u16 td0, td1;
|
|
|
|
u32 fifomr;
|
|
|
|
|
|
|
|
dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_fifo\n");
|
|
|
|
|
|
|
|
/* Compute the number of data to transfer in the current iteration */
|
|
|
|
current_remaining_data = ((xfer->bits_per_word > 8) ?
|
|
|
|
((u32)as->current_remaining_bytes >> 1) :
|
|
|
|
(u32)as->current_remaining_bytes);
|
|
|
|
num_data = min(current_remaining_data, as->fifo_size);
|
|
|
|
|
|
|
|
/* Flush RX and TX FIFOs */
|
|
|
|
spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR));
|
|
|
|
while (spi_readl(as, FLR))
|
|
|
|
cpu_relax();
|
|
|
|
|
|
|
|
/* Set RX FIFO Threshold to the number of data to transfer */
|
|
|
|
fifomr = spi_readl(as, FMR);
|
|
|
|
spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr));
|
|
|
|
|
|
|
|
/* Clear FIFO flags in the Status Register, especially RXFTHF */
|
|
|
|
(void)spi_readl(as, SR);
|
|
|
|
|
|
|
|
/* Fill TX FIFO */
|
|
|
|
while (num_data >= 2) {
|
2016-11-24 04:24:58 -07:00
|
|
|
if (xfer->bits_per_word > 8) {
|
|
|
|
td0 = *words++;
|
|
|
|
td1 = *words++;
|
spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
|
|
|
} else {
|
2016-11-24 04:24:58 -07:00
|
|
|
td0 = *bytes++;
|
|
|
|
td1 = *bytes++;
|
spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
spi_writel(as, TDR, (td1 << 16) | td0);
|
|
|
|
num_data -= 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (num_data) {
|
2016-11-24 04:24:58 -07:00
|
|
|
if (xfer->bits_per_word > 8)
|
|
|
|
td0 = *words++;
|
|
|
|
else
|
|
|
|
td0 = *bytes++;
|
spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
|
|
|
|
|
|
|
spi_writew(as, TDR, td0);
|
|
|
|
num_data--;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_dbg(master->dev.parent,
|
|
|
|
" start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
|
|
|
|
xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
|
|
|
|
xfer->bits_per_word);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable RX FIFO Threshold Flag interrupt to be notified about
|
|
|
|
* transfer completion.
|
|
|
|
*/
|
|
|
|
spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES));
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Next transfer using PIO.
|
|
|
|
*/
|
|
|
|
static void atmel_spi_next_xfer_pio(struct spi_master *master,
|
|
|
|
struct spi_transfer *xfer)
|
|
|
|
{
|
|
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
|
|
|
|
|
|
|
if (as->fifo_size)
|
|
|
|
atmel_spi_next_xfer_fifo(master, xfer);
|
|
|
|
else
|
|
|
|
atmel_spi_next_xfer_single(master, xfer);
|
|
|
|
}
|
|
|
|
|
2013-04-02 23:59:19 -06:00
|
|
|
/*
|
|
|
|
* Submit next transfer for DMA.
|
|
|
|
*/
|
|
|
|
static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
|
|
|
|
struct spi_transfer *xfer,
|
|
|
|
u32 *plen)
|
|
|
|
{
|
|
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
2016-11-24 04:25:01 -07:00
|
|
|
struct dma_chan *rxchan = master->dma_rx;
|
|
|
|
struct dma_chan *txchan = master->dma_tx;
|
2013-04-02 23:59:19 -06:00
|
|
|
struct dma_async_tx_descriptor *rxdesc;
|
|
|
|
struct dma_async_tx_descriptor *txdesc;
|
|
|
|
struct dma_slave_config slave_config;
|
|
|
|
dma_cookie_t cookie;
|
|
|
|
|
|
|
|
dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
|
|
|
|
|
|
|
|
/* Check that the channels are available */
|
|
|
|
if (!rxchan || !txchan)
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
/* release lock for DMA operations */
|
|
|
|
atmel_spi_unlock(as);
|
|
|
|
|
2016-11-24 04:24:59 -07:00
|
|
|
*plen = xfer->len;
|
2013-04-02 23:59:19 -06:00
|
|
|
|
2015-10-20 06:26:47 -06:00
|
|
|
if (atmel_spi_dma_slave_config(as, &slave_config,
|
|
|
|
xfer->bits_per_word))
|
2013-04-02 23:59:19 -06:00
|
|
|
goto err_exit;
|
|
|
|
|
|
|
|
/* Send both scatterlists */
|
2017-12-19 08:17:59 -07:00
|
|
|
if (atmel_spi_is_vmalloc_xfer(xfer) &&
|
|
|
|
IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
|
|
|
|
rxdesc = dmaengine_prep_slave_single(rxchan,
|
|
|
|
as->dma_addr_rx_bbuf,
|
|
|
|
xfer->len,
|
2018-03-24 04:48:00 -06:00
|
|
|
DMA_DEV_TO_MEM,
|
2017-12-19 08:17:59 -07:00
|
|
|
DMA_PREP_INTERRUPT |
|
|
|
|
DMA_CTRL_ACK);
|
|
|
|
} else {
|
|
|
|
rxdesc = dmaengine_prep_slave_sg(rxchan,
|
|
|
|
xfer->rx_sg.sgl,
|
|
|
|
xfer->rx_sg.nents,
|
2018-03-24 04:48:00 -06:00
|
|
|
DMA_DEV_TO_MEM,
|
2017-12-19 08:17:59 -07:00
|
|
|
DMA_PREP_INTERRUPT |
|
|
|
|
DMA_CTRL_ACK);
|
|
|
|
}
|
2013-04-02 23:59:19 -06:00
|
|
|
if (!rxdesc)
|
|
|
|
goto err_dma;
|
|
|
|
|
2017-12-19 08:17:59 -07:00
|
|
|
if (atmel_spi_is_vmalloc_xfer(xfer) &&
|
|
|
|
IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
|
|
|
|
memcpy(as->addr_tx_bbuf, xfer->tx_buf, xfer->len);
|
|
|
|
txdesc = dmaengine_prep_slave_single(txchan,
|
|
|
|
as->dma_addr_tx_bbuf,
|
2018-03-24 04:48:00 -06:00
|
|
|
xfer->len, DMA_MEM_TO_DEV,
|
2017-12-19 08:17:59 -07:00
|
|
|
DMA_PREP_INTERRUPT |
|
|
|
|
DMA_CTRL_ACK);
|
|
|
|
} else {
|
|
|
|
txdesc = dmaengine_prep_slave_sg(txchan,
|
|
|
|
xfer->tx_sg.sgl,
|
|
|
|
xfer->tx_sg.nents,
|
2018-03-24 04:48:00 -06:00
|
|
|
DMA_MEM_TO_DEV,
|
2017-12-19 08:17:59 -07:00
|
|
|
DMA_PREP_INTERRUPT |
|
|
|
|
DMA_CTRL_ACK);
|
|
|
|
}
|
2013-04-02 23:59:19 -06:00
|
|
|
if (!txdesc)
|
|
|
|
goto err_dma;
|
|
|
|
|
|
|
|
dev_dbg(master->dev.parent,
|
2013-07-30 11:35:35 -06:00
|
|
|
" start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
|
|
|
|
xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma,
|
|
|
|
xfer->rx_buf, (unsigned long long)xfer->rx_dma);
|
2013-04-02 23:59:19 -06:00
|
|
|
|
|
|
|
/* Enable relevant interrupts */
|
|
|
|
spi_writel(as, IER, SPI_BIT(OVRES));
|
|
|
|
|
|
|
|
/* Put the callback on the RX transfer only, that should finish last */
|
|
|
|
rxdesc->callback = dma_callback;
|
|
|
|
rxdesc->callback_param = master;
|
|
|
|
|
|
|
|
/* Submit and fire RX and TX with TX last so we're ready to read! */
|
|
|
|
cookie = rxdesc->tx_submit(rxdesc);
|
|
|
|
if (dma_submit_error(cookie))
|
|
|
|
goto err_dma;
|
|
|
|
cookie = txdesc->tx_submit(txdesc);
|
|
|
|
if (dma_submit_error(cookie))
|
|
|
|
goto err_dma;
|
|
|
|
rxchan->device->device_issue_pending(rxchan);
|
|
|
|
txchan->device->device_issue_pending(txchan);
|
|
|
|
|
|
|
|
/* take back lock */
|
|
|
|
atmel_spi_lock(as);
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_dma:
|
|
|
|
spi_writel(as, IDR, SPI_BIT(OVRES));
|
2016-11-24 04:25:01 -07:00
|
|
|
atmel_spi_stop_dma(master);
|
2013-04-02 23:59:19 -06:00
|
|
|
err_exit:
|
|
|
|
atmel_spi_lock(as);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2008-02-06 02:38:12 -07:00
|
|
|
static void atmel_spi_next_xfer_data(struct spi_master *master,
|
|
|
|
struct spi_transfer *xfer,
|
|
|
|
dma_addr_t *tx_dma,
|
|
|
|
dma_addr_t *rx_dma,
|
|
|
|
u32 *plen)
|
|
|
|
{
|
2016-11-24 04:24:58 -07:00
|
|
|
*rx_dma = xfer->rx_dma + xfer->len - *plen;
|
|
|
|
*tx_dma = xfer->tx_dma + xfer->len - *plen;
|
2016-11-24 04:24:59 -07:00
|
|
|
if (*plen > master->max_dma_len)
|
|
|
|
*plen = master->max_dma_len;
|
2008-02-06 02:38:12 -07:00
|
|
|
}
|
|
|
|
|
2013-11-07 02:34:06 -07:00
|
|
|
static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
|
|
|
|
struct spi_device *spi,
|
|
|
|
struct spi_transfer *xfer)
|
|
|
|
{
|
|
|
|
u32 scbr, csr;
|
|
|
|
unsigned long bus_hz;
|
|
|
|
|
|
|
|
/* v1 chips start out at half the peripheral bus speed. */
|
2016-11-14 08:13:20 -07:00
|
|
|
bus_hz = as->spi_clk;
|
2013-11-07 02:34:06 -07:00
|
|
|
if (!atmel_spi_is_v2(as))
|
|
|
|
bus_hz /= 2;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Calculate the lowest divider that satisfies the
|
|
|
|
* constraint, assuming div32/fdiv/mbz == 0.
|
|
|
|
*/
|
2015-09-25 00:03:01 -06:00
|
|
|
scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz);
|
2013-11-07 02:34:06 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If the resulting divider doesn't fit into the
|
|
|
|
* register bitfield, we can't satisfy the constraint.
|
|
|
|
*/
|
|
|
|
if (scbr >= (1 << SPI_SCBR_SIZE)) {
|
|
|
|
dev_err(&spi->dev,
|
|
|
|
"setup: %d Hz too slow, scbr %u; min %ld Hz\n",
|
|
|
|
xfer->speed_hz, scbr, bus_hz/255);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
if (scbr == 0) {
|
|
|
|
dev_err(&spi->dev,
|
|
|
|
"setup: %d Hz too high, scbr %u; max %ld Hz\n",
|
|
|
|
xfer->speed_hz, scbr, bus_hz);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
csr = spi_readl(as, CSR0 + 4 * spi->chip_select);
|
|
|
|
csr = SPI_BFINS(SCBR, scbr, csr);
|
|
|
|
spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-02-14 01:33:09 -07:00
|
|
|
/*
|
2013-04-02 23:59:19 -06:00
|
|
|
* Submit next transfer for PDC.
|
2007-02-14 01:33:09 -07:00
|
|
|
* lock is held, spi irq is blocked
|
|
|
|
*/
|
2013-04-02 23:59:19 -06:00
|
|
|
static void atmel_spi_pdc_next_xfer(struct spi_master *master,
|
2014-01-08 22:19:15 -07:00
|
|
|
struct spi_message *msg,
|
|
|
|
struct spi_transfer *xfer)
|
2007-02-14 01:33:09 -07:00
|
|
|
{
|
|
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
2014-01-08 22:19:15 -07:00
|
|
|
u32 len;
|
2007-02-14 01:33:09 -07:00
|
|
|
dma_addr_t tx_dma, rx_dma;
|
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
len = as->current_remaining_bytes;
|
|
|
|
atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
|
|
|
|
as->current_remaining_bytes -= len;
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
spi_writel(as, RPR, rx_dma);
|
|
|
|
spi_writel(as, TPR, tx_dma);
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
if (msg->spi->bits_per_word > 8)
|
|
|
|
len >>= 1;
|
|
|
|
spi_writel(as, RCR, len);
|
|
|
|
spi_writel(as, TCR, len);
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
dev_dbg(&msg->spi->dev,
|
|
|
|
" start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
|
|
|
|
xfer, xfer->len, xfer->tx_buf,
|
|
|
|
(unsigned long long)xfer->tx_dma, xfer->rx_buf,
|
|
|
|
(unsigned long long)xfer->rx_dma);
|
2008-08-04 14:41:12 -06:00
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
if (as->current_remaining_bytes) {
|
|
|
|
len = as->current_remaining_bytes;
|
2008-02-06 02:38:12 -07:00
|
|
|
atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
|
2014-01-08 22:19:15 -07:00
|
|
|
as->current_remaining_bytes -= len;
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2008-02-06 02:38:12 -07:00
|
|
|
spi_writel(as, RNPR, rx_dma);
|
|
|
|
spi_writel(as, TNPR, tx_dma);
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2008-02-06 02:38:12 -07:00
|
|
|
if (msg->spi->bits_per_word > 8)
|
|
|
|
len >>= 1;
|
|
|
|
spi_writel(as, RNCR, len);
|
|
|
|
spi_writel(as, TNCR, len);
|
2008-02-06 02:38:13 -07:00
|
|
|
|
|
|
|
dev_dbg(&msg->spi->dev,
|
2013-07-30 11:35:35 -06:00
|
|
|
" next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
|
|
|
|
xfer, xfer->len, xfer->tx_buf,
|
|
|
|
(unsigned long long)xfer->tx_dma, xfer->rx_buf,
|
|
|
|
(unsigned long long)xfer->rx_dma);
|
2008-02-06 02:38:12 -07:00
|
|
|
}
|
|
|
|
|
2015-02-24 08:32:57 -07:00
|
|
|
/* REVISIT: We're waiting for RXBUFF before we start the next
|
2007-02-14 01:33:09 -07:00
|
|
|
* transfer because we need to handle some difficult timing
|
2015-02-24 08:32:57 -07:00
|
|
|
* issues otherwise. If we wait for TXBUFE in one transfer and
|
|
|
|
* then starts waiting for RXBUFF in the next, it's difficult
|
|
|
|
* to tell the difference between the RXBUFF interrupt we're
|
|
|
|
* actually waiting for and the RXBUFF interrupt of the
|
2007-02-14 01:33:09 -07:00
|
|
|
* previous transfer.
|
|
|
|
*
|
|
|
|
* It should be doable, though. Just not now...
|
|
|
|
*/
|
2015-02-24 08:32:57 -07:00
|
|
|
spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));
|
2007-02-14 01:33:09 -07:00
|
|
|
spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
|
|
|
|
}
|
|
|
|
|
2007-07-17 05:04:07 -06:00
|
|
|
/*
|
|
|
|
* For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
|
|
|
|
* - The buffer is either valid for CPU access, else NULL
|
tree-wide: fix comment/printk typos
"gadget", "through", "command", "maintain", "maintain", "controller", "address",
"between", "initiali[zs]e", "instead", "function", "select", "already",
"equal", "access", "management", "hierarchy", "registration", "interest",
"relative", "memory", "offset", "already",
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-11-01 13:38:34 -06:00
|
|
|
* - If the buffer is valid, so is its DMA address
|
2007-07-17 05:04:07 -06:00
|
|
|
*
|
tree-wide: fix comment/printk typos
"gadget", "through", "command", "maintain", "maintain", "controller", "address",
"between", "initiali[zs]e", "instead", "function", "select", "already",
"equal", "access", "management", "hierarchy", "registration", "interest",
"relative", "memory", "offset", "already",
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-11-01 13:38:34 -06:00
|
|
|
* This driver manages the dma address unless message->is_dma_mapped.
|
2007-07-17 05:04:07 -06:00
|
|
|
*/
|
|
|
|
static int
|
2007-02-14 01:33:09 -07:00
|
|
|
atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
|
|
|
|
{
|
2007-07-17 05:04:07 -06:00
|
|
|
struct device *dev = &as->pdev->dev;
|
|
|
|
|
2007-02-14 01:33:09 -07:00
|
|
|
xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
|
2007-07-17 05:04:07 -06:00
|
|
|
if (xfer->tx_buf) {
|
2010-11-19 23:52:53 -07:00
|
|
|
/* tx_buf is a const void* where we need a void * for the dma
|
|
|
|
* mapping */
|
|
|
|
void *nonconst_tx = (void *)xfer->tx_buf;
|
|
|
|
|
2007-07-17 05:04:07 -06:00
|
|
|
xfer->tx_dma = dma_map_single(dev,
|
2010-11-19 23:52:53 -07:00
|
|
|
nonconst_tx, xfer->len,
|
2007-02-14 01:33:09 -07:00
|
|
|
DMA_TO_DEVICE);
|
2008-07-25 20:44:49 -06:00
|
|
|
if (dma_mapping_error(dev, xfer->tx_dma))
|
2007-07-17 05:04:07 -06:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
if (xfer->rx_buf) {
|
|
|
|
xfer->rx_dma = dma_map_single(dev,
|
2007-02-14 01:33:09 -07:00
|
|
|
xfer->rx_buf, xfer->len,
|
|
|
|
DMA_FROM_DEVICE);
|
2008-07-25 20:44:49 -06:00
|
|
|
if (dma_mapping_error(dev, xfer->rx_dma)) {
|
2007-07-17 05:04:07 -06:00
|
|
|
if (xfer->tx_buf)
|
|
|
|
dma_unmap_single(dev,
|
|
|
|
xfer->tx_dma, xfer->len,
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
2007-02-14 01:33:09 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
|
|
|
|
struct spi_transfer *xfer)
|
|
|
|
{
|
|
|
|
if (xfer->tx_dma != INVALID_DMA_ADDRESS)
|
2007-10-16 02:27:48 -06:00
|
|
|
dma_unmap_single(master->dev.parent, xfer->tx_dma,
|
2007-02-14 01:33:09 -07:00
|
|
|
xfer->len, DMA_TO_DEVICE);
|
|
|
|
if (xfer->rx_dma != INVALID_DMA_ADDRESS)
|
2007-10-16 02:27:48 -06:00
|
|
|
dma_unmap_single(master->dev.parent, xfer->rx_dma,
|
2007-02-14 01:33:09 -07:00
|
|
|
xfer->len, DMA_FROM_DEVICE);
|
|
|
|
}
|
|
|
|
|
2013-04-02 23:59:19 -06:00
|
|
|
static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
|
|
|
|
{
|
|
|
|
spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
|
|
|
atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
|
2013-04-02 23:59:19 -06:00
|
|
|
{
|
|
|
|
u8 *rxp;
|
2013-05-02 05:25:11 -06:00
|
|
|
u16 *rxp16;
|
2013-04-02 23:59:19 -06:00
|
|
|
unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
|
|
|
|
|
2016-11-24 04:24:58 -07:00
|
|
|
if (xfer->bits_per_word > 8) {
|
|
|
|
rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
|
|
|
|
*rxp16 = spi_readl(as, RDR);
|
2013-04-02 23:59:19 -06:00
|
|
|
} else {
|
2016-11-24 04:24:58 -07:00
|
|
|
rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
|
|
|
|
*rxp = spi_readl(as, RDR);
|
2013-04-02 23:59:19 -06:00
|
|
|
}
|
2013-05-02 05:25:11 -06:00
|
|
|
if (xfer->bits_per_word > 8) {
|
2014-05-06 09:44:41 -06:00
|
|
|
if (as->current_remaining_bytes > 2)
|
|
|
|
as->current_remaining_bytes -= 2;
|
|
|
|
else
|
2013-05-02 05:25:11 -06:00
|
|
|
as->current_remaining_bytes = 0;
|
|
|
|
} else {
|
|
|
|
as->current_remaining_bytes--;
|
|
|
|
}
|
2013-04-02 23:59:19 -06:00
|
|
|
}
|
|
|
|
|
spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
|
|
|
static void
|
|
|
|
atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
|
|
|
|
{
|
|
|
|
u32 fifolr = spi_readl(as, FLR);
|
|
|
|
u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr);
|
|
|
|
u32 offset = xfer->len - as->current_remaining_bytes;
|
|
|
|
u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset);
|
|
|
|
u8 *bytes = (u8 *)((u8 *)xfer->rx_buf + offset);
|
|
|
|
u16 rd; /* RD field is the lowest 16 bits of RDR */
|
|
|
|
|
|
|
|
/* Update the number of remaining bytes to transfer */
|
|
|
|
num_bytes = ((xfer->bits_per_word > 8) ?
|
|
|
|
(num_data << 1) :
|
|
|
|
num_data);
|
|
|
|
|
|
|
|
if (as->current_remaining_bytes > num_bytes)
|
|
|
|
as->current_remaining_bytes -= num_bytes;
|
|
|
|
else
|
|
|
|
as->current_remaining_bytes = 0;
|
|
|
|
|
|
|
|
/* Handle odd number of bytes when data are more than 8bit width */
|
|
|
|
if (xfer->bits_per_word > 8)
|
|
|
|
as->current_remaining_bytes &= ~0x1;
|
|
|
|
|
|
|
|
/* Read data */
|
|
|
|
while (num_data) {
|
|
|
|
rd = spi_readl(as, RDR);
|
2016-11-24 04:24:58 -07:00
|
|
|
if (xfer->bits_per_word > 8)
|
|
|
|
*words++ = rd;
|
|
|
|
else
|
|
|
|
*bytes++ = rd;
|
spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
|
|
|
num_data--;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Called from IRQ
|
|
|
|
*
|
|
|
|
* Must update "current_remaining_bytes" to keep track of data
|
|
|
|
* to transfer.
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
|
|
|
|
{
|
|
|
|
if (as->fifo_size)
|
|
|
|
atmel_spi_pump_fifo_data(as, xfer);
|
|
|
|
else
|
|
|
|
atmel_spi_pump_single_data(as, xfer);
|
|
|
|
}
|
|
|
|
|
2013-04-02 23:59:19 -06:00
|
|
|
/* Interrupt
|
|
|
|
*
|
|
|
|
* No need for locking in this Interrupt handler: done_status is the
|
2014-01-08 22:19:15 -07:00
|
|
|
* only information modified.
|
2013-04-02 23:59:19 -06:00
|
|
|
*/
|
|
|
|
static irqreturn_t
|
|
|
|
atmel_spi_pio_interrupt(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct spi_master *master = dev_id;
|
|
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
|
|
|
u32 status, pending, imr;
|
|
|
|
struct spi_transfer *xfer;
|
|
|
|
int ret = IRQ_NONE;
|
|
|
|
|
|
|
|
imr = spi_readl(as, IMR);
|
|
|
|
status = spi_readl(as, SR);
|
|
|
|
pending = status & imr;
|
|
|
|
|
|
|
|
if (pending & SPI_BIT(OVRES)) {
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
spi_writel(as, IDR, SPI_BIT(OVRES));
|
|
|
|
dev_warn(master->dev.parent, "overrun\n");
|
|
|
|
|
|
|
|
/*
|
|
|
|
* When we get an overrun, we disregard the current
|
|
|
|
* transfer. Data will not be copied back from any
|
|
|
|
* bounce buffer and msg->actual_len will not be
|
|
|
|
* updated with the last xfer.
|
|
|
|
*
|
|
|
|
* We will also not process any remaning transfers in
|
|
|
|
* the message.
|
|
|
|
*/
|
|
|
|
as->done_status = -EIO;
|
|
|
|
smp_wmb();
|
|
|
|
|
|
|
|
/* Clear any overrun happening while cleaning up */
|
|
|
|
spi_readl(as, SR);
|
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
complete(&as->xfer_completion);
|
2013-04-02 23:59:19 -06:00
|
|
|
|
spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
|
|
|
} else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) {
|
2013-04-02 23:59:19 -06:00
|
|
|
atmel_spi_lock(as);
|
|
|
|
|
|
|
|
if (as->current_remaining_bytes) {
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
xfer = as->current_transfer;
|
|
|
|
atmel_spi_pump_pio_data(as, xfer);
|
2014-01-08 22:19:15 -07:00
|
|
|
if (!as->current_remaining_bytes)
|
2013-04-02 23:59:19 -06:00
|
|
|
spi_writel(as, IDR, pending);
|
2014-01-08 22:19:15 -07:00
|
|
|
|
|
|
|
complete(&as->xfer_completion);
|
2013-04-02 23:59:19 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
atmel_spi_unlock(as);
|
|
|
|
} else {
|
|
|
|
WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
spi_writel(as, IDR, pending);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
2007-02-14 01:33:09 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t
|
2013-04-02 23:59:19 -06:00
|
|
|
atmel_spi_pdc_interrupt(int irq, void *dev_id)
|
2007-02-14 01:33:09 -07:00
|
|
|
{
|
|
|
|
struct spi_master *master = dev_id;
|
|
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
|
|
|
u32 status, pending, imr;
|
|
|
|
int ret = IRQ_NONE;
|
|
|
|
|
|
|
|
imr = spi_readl(as, IMR);
|
|
|
|
status = spi_readl(as, SR);
|
|
|
|
pending = status & imr;
|
|
|
|
|
|
|
|
if (pending & SPI_BIT(OVRES)) {
|
|
|
|
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
|
2008-08-04 14:41:12 -06:00
|
|
|
spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
|
2007-02-14 01:33:09 -07:00
|
|
|
| SPI_BIT(OVRES)));
|
|
|
|
|
|
|
|
/* Clear any overrun happening while cleaning up */
|
|
|
|
spi_readl(as, SR);
|
|
|
|
|
2013-03-19 01:45:01 -06:00
|
|
|
as->done_status = -EIO;
|
2014-01-08 22:19:15 -07:00
|
|
|
|
|
|
|
complete(&as->xfer_completion);
|
|
|
|
|
2008-08-04 14:41:12 -06:00
|
|
|
} else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
|
2007-02-14 01:33:09 -07:00
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
|
|
|
|
spi_writel(as, IDR, pending);
|
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
complete(&as->xfer_completion);
|
2007-02-14 01:33:09 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int atmel_spi_setup(struct spi_device *spi)
|
|
|
|
{
|
|
|
|
struct atmel_spi *as;
|
2009-01-06 15:41:43 -07:00
|
|
|
struct atmel_spi_device *asd;
|
2013-11-07 02:34:06 -07:00
|
|
|
u32 csr;
|
2007-02-14 01:33:09 -07:00
|
|
|
unsigned int bits = spi->bits_per_word;
|
|
|
|
unsigned int npcs_pin;
|
|
|
|
|
|
|
|
as = spi_master_get_devdata(spi->master);
|
|
|
|
|
2007-07-17 05:04:08 -06:00
|
|
|
/* see notes above re chipselect */
|
2013-03-19 01:42:15 -06:00
|
|
|
if (!atmel_spi_is_v2(as)
|
2007-07-17 05:04:08 -06:00
|
|
|
&& spi->chip_select == 0
|
|
|
|
&& (spi->mode & SPI_CS_HIGH)) {
|
|
|
|
dev_dbg(&spi->dev, "setup: can't be active-high\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2013-11-07 02:34:06 -07:00
|
|
|
csr = SPI_BF(BITS, bits - 8);
|
2007-02-14 01:33:09 -07:00
|
|
|
if (spi->mode & SPI_CPOL)
|
|
|
|
csr |= SPI_BIT(CPOL);
|
|
|
|
if (!(spi->mode & SPI_CPHA))
|
|
|
|
csr |= SPI_BIT(NCPHA);
|
2015-06-09 05:53:52 -06:00
|
|
|
if (!as->use_cs_gpios)
|
|
|
|
csr |= SPI_BIT(CSAAT);
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2008-02-06 02:38:11 -07:00
|
|
|
/* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
|
|
|
|
*
|
|
|
|
* DLYBCT would add delays between words, slowing down transfers.
|
|
|
|
* It could potentially be useful to cope with DMA bottlenecks, but
|
|
|
|
* in those cases it's probably best to just use a lower bitrate.
|
|
|
|
*/
|
|
|
|
csr |= SPI_BF(DLYBS, 0);
|
|
|
|
csr |= SPI_BF(DLYBCT, 0);
|
2007-02-14 01:33:09 -07:00
|
|
|
|
|
|
|
/* chipselect must have been muxed as GPIO (e.g. in board setup) */
|
2014-08-01 10:43:03 -06:00
|
|
|
npcs_pin = (unsigned long)spi->controller_data;
|
2012-11-23 05:44:39 -07:00
|
|
|
|
2015-06-09 05:53:52 -06:00
|
|
|
if (!as->use_cs_gpios)
|
|
|
|
npcs_pin = spi->chip_select;
|
|
|
|
else if (gpio_is_valid(spi->cs_gpio))
|
2012-11-23 05:44:39 -07:00
|
|
|
npcs_pin = spi->cs_gpio;
|
|
|
|
|
2009-01-06 15:41:43 -07:00
|
|
|
asd = spi->controller_state;
|
|
|
|
if (!asd) {
|
|
|
|
asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
|
|
|
|
if (!asd)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2016-11-08 10:48:52 -07:00
|
|
|
if (as->use_cs_gpios)
|
2015-06-09 05:53:52 -06:00
|
|
|
gpio_direction_output(npcs_pin,
|
|
|
|
!(spi->mode & SPI_CS_HIGH));
|
2009-01-06 15:41:43 -07:00
|
|
|
|
|
|
|
asd->npcs_pin = npcs_pin;
|
|
|
|
spi->controller_state = asd;
|
2007-02-14 01:33:09 -07:00
|
|
|
}
|
|
|
|
|
2009-01-06 15:41:43 -07:00
|
|
|
asd->csr = csr;
|
|
|
|
|
2007-02-14 01:33:09 -07:00
|
|
|
dev_dbg(&spi->dev,
|
2013-11-07 02:34:06 -07:00
|
|
|
"setup: bpw %u mode 0x%x -> csr%d %08x\n",
|
|
|
|
bits, spi->mode, spi->chip_select, csr);
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2013-03-19 01:42:15 -06:00
|
|
|
if (!atmel_spi_is_v2(as))
|
2009-01-06 15:41:43 -07:00
|
|
|
spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
|
2007-02-14 01:33:09 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
static int atmel_spi_one_transfer(struct spi_master *master,
|
|
|
|
struct spi_message *msg,
|
|
|
|
struct spi_transfer *xfer)
|
2007-02-14 01:33:09 -07:00
|
|
|
{
|
|
|
|
struct atmel_spi *as;
|
2014-01-08 22:19:15 -07:00
|
|
|
struct spi_device *spi = msg->spi;
|
2010-10-13 09:51:02 -06:00
|
|
|
u8 bits;
|
2014-01-08 22:19:15 -07:00
|
|
|
u32 len;
|
2010-10-13 09:51:02 -06:00
|
|
|
struct atmel_spi_device *asd;
|
2014-01-08 22:19:15 -07:00
|
|
|
int timeout;
|
|
|
|
int ret;
|
2015-02-02 08:43:31 -07:00
|
|
|
unsigned long dma_timeout;
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
as = spi_master_get_devdata(master);
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
|
|
|
|
dev_dbg(&spi->dev, "missing rx or tx buf\n");
|
2007-02-14 01:33:09 -07:00
|
|
|
return -EINVAL;
|
2014-01-08 22:19:15 -07:00
|
|
|
}
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2015-09-25 00:03:01 -06:00
|
|
|
asd = spi->controller_state;
|
|
|
|
bits = (asd->csr >> 4) & 0xf;
|
|
|
|
if (bits != xfer->bits_per_word - 8) {
|
|
|
|
dev_dbg(&spi->dev,
|
2014-01-08 22:19:15 -07:00
|
|
|
"you can't yet change bits_per_word in transfers\n");
|
2015-09-25 00:03:01 -06:00
|
|
|
return -ENOPROTOOPT;
|
2014-01-08 22:19:15 -07:00
|
|
|
}
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
/*
|
|
|
|
* DMA map early, for performance (empties dcache ASAP) and
|
|
|
|
* better fault reporting.
|
|
|
|
*/
|
|
|
|
if ((!msg->is_dma_mapped)
|
2016-11-24 04:24:59 -07:00
|
|
|
&& as->use_pdc) {
|
2014-01-08 22:19:15 -07:00
|
|
|
if (atmel_spi_dma_map_xfer(as, xfer) < 0)
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
atmel_spi_set_xfer_speed(as, msg->spi, xfer);
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
as->done_status = 0;
|
|
|
|
as->current_transfer = xfer;
|
|
|
|
as->current_remaining_bytes = xfer->len;
|
|
|
|
while (as->current_remaining_bytes) {
|
|
|
|
reinit_completion(&as->xfer_completion);
|
|
|
|
|
|
|
|
if (as->use_pdc) {
|
|
|
|
atmel_spi_pdc_next_xfer(master, msg, xfer);
|
|
|
|
} else if (atmel_spi_use_dma(as, xfer)) {
|
|
|
|
len = as->current_remaining_bytes;
|
|
|
|
ret = atmel_spi_next_xfer_dma_submit(master,
|
|
|
|
xfer, &len);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&spi->dev,
|
|
|
|
"unable to use DMA, fallback to PIO\n");
|
|
|
|
atmel_spi_next_xfer_pio(master, xfer);
|
|
|
|
} else {
|
|
|
|
as->current_remaining_bytes -= len;
|
2014-03-26 19:26:38 -06:00
|
|
|
if (as->current_remaining_bytes < 0)
|
|
|
|
as->current_remaining_bytes = 0;
|
2010-10-13 09:51:02 -06:00
|
|
|
}
|
2014-01-08 22:19:15 -07:00
|
|
|
} else {
|
|
|
|
atmel_spi_next_xfer_pio(master, xfer);
|
2010-10-13 09:51:02 -06:00
|
|
|
}
|
|
|
|
|
2014-04-13 04:45:10 -06:00
|
|
|
/* interrupts are disabled, so free the lock for schedule */
|
|
|
|
atmel_spi_unlock(as);
|
2015-02-02 08:43:31 -07:00
|
|
|
dma_timeout = wait_for_completion_timeout(&as->xfer_completion,
|
|
|
|
SPI_DMA_TIMEOUT);
|
2014-04-13 04:45:10 -06:00
|
|
|
atmel_spi_lock(as);
|
2015-02-02 08:43:31 -07:00
|
|
|
if (WARN_ON(dma_timeout == 0)) {
|
|
|
|
dev_err(&spi->dev, "spi transfer timeout\n");
|
2014-01-08 22:19:15 -07:00
|
|
|
as->done_status = -EIO;
|
2013-05-02 05:25:11 -06:00
|
|
|
}
|
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
if (as->done_status)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (as->done_status) {
|
|
|
|
if (as->use_pdc) {
|
|
|
|
dev_warn(master->dev.parent,
|
|
|
|
"overrun (%u/%u remaining)\n",
|
|
|
|
spi_readl(as, TCR), spi_readl(as, RCR));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clean up DMA registers and make sure the data
|
|
|
|
* registers are empty.
|
|
|
|
*/
|
|
|
|
spi_writel(as, RNCR, 0);
|
|
|
|
spi_writel(as, TNCR, 0);
|
|
|
|
spi_writel(as, RCR, 0);
|
|
|
|
spi_writel(as, TCR, 0);
|
|
|
|
for (timeout = 1000; timeout; timeout--)
|
|
|
|
if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
|
|
|
|
break;
|
|
|
|
if (!timeout)
|
|
|
|
dev_warn(master->dev.parent,
|
|
|
|
"timeout waiting for TXEMPTY");
|
|
|
|
while (spi_readl(as, SR) & SPI_BIT(RDRF))
|
|
|
|
spi_readl(as, RDR);
|
|
|
|
|
|
|
|
/* Clear any overrun happening while cleaning up */
|
|
|
|
spi_readl(as, SR);
|
|
|
|
|
|
|
|
} else if (atmel_spi_use_dma(as, xfer)) {
|
2016-11-24 04:25:01 -07:00
|
|
|
atmel_spi_stop_dma(master);
|
2014-01-08 22:19:15 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!msg->is_dma_mapped
|
2016-11-24 04:24:59 -07:00
|
|
|
&& as->use_pdc)
|
2014-01-08 22:19:15 -07:00
|
|
|
atmel_spi_dma_unmap_xfer(master, xfer);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
} else {
|
|
|
|
/* only update length if no error */
|
|
|
|
msg->actual_length += xfer->len;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!msg->is_dma_mapped
|
2016-11-24 04:24:59 -07:00
|
|
|
&& as->use_pdc)
|
2014-01-08 22:19:15 -07:00
|
|
|
atmel_spi_dma_unmap_xfer(master, xfer);
|
|
|
|
|
|
|
|
if (xfer->delay_usecs)
|
|
|
|
udelay(xfer->delay_usecs);
|
|
|
|
|
|
|
|
if (xfer->cs_change) {
|
|
|
|
if (list_is_last(&xfer->transfer_list,
|
|
|
|
&msg->transfers)) {
|
|
|
|
as->keep_cs = true;
|
|
|
|
} else {
|
|
|
|
as->cs_active = !as->cs_active;
|
|
|
|
if (as->cs_active)
|
|
|
|
cs_activate(as, msg->spi);
|
|
|
|
else
|
|
|
|
cs_deactivate(as, msg->spi);
|
2007-07-17 05:04:07 -06:00
|
|
|
}
|
2007-02-14 01:33:09 -07:00
|
|
|
}
|
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int atmel_spi_transfer_one_message(struct spi_master *master,
|
|
|
|
struct spi_message *msg)
|
|
|
|
{
|
|
|
|
struct atmel_spi *as;
|
|
|
|
struct spi_transfer *xfer;
|
|
|
|
struct spi_device *spi = msg->spi;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
as = spi_master_get_devdata(master);
|
|
|
|
|
|
|
|
dev_dbg(&spi->dev, "new message %p submitted for %s\n",
|
|
|
|
msg, dev_name(&spi->dev));
|
|
|
|
|
|
|
|
atmel_spi_lock(as);
|
|
|
|
cs_activate(as, spi);
|
|
|
|
|
|
|
|
as->cs_active = true;
|
|
|
|
as->keep_cs = false;
|
|
|
|
|
|
|
|
msg->status = 0;
|
|
|
|
msg->actual_length = 0;
|
|
|
|
|
|
|
|
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
|
|
|
|
ret = atmel_spi_one_transfer(master, msg, xfer);
|
|
|
|
if (ret)
|
|
|
|
goto msg_done;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (as->use_pdc)
|
|
|
|
atmel_spi_disable_pdc_transfer(as);
|
|
|
|
|
2007-02-14 01:33:09 -07:00
|
|
|
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
|
2014-01-08 22:19:15 -07:00
|
|
|
dev_dbg(&spi->dev,
|
2014-03-21 09:53:41 -06:00
|
|
|
" xfer %p: len %u tx %p/%pad rx %p/%pad\n",
|
2007-02-14 01:33:09 -07:00
|
|
|
xfer, xfer->len,
|
2014-03-21 09:53:41 -06:00
|
|
|
xfer->tx_buf, &xfer->tx_dma,
|
|
|
|
xfer->rx_buf, &xfer->rx_dma);
|
2007-02-14 01:33:09 -07:00
|
|
|
}
|
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
msg_done:
|
|
|
|
if (!as->keep_cs)
|
|
|
|
cs_deactivate(as, msg->spi);
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2013-04-02 23:58:36 -06:00
|
|
|
atmel_spi_unlock(as);
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
msg->status = as->done_status;
|
|
|
|
spi_finalize_current_message(spi->master);
|
|
|
|
|
|
|
|
return ret;
|
2007-02-14 01:33:09 -07:00
|
|
|
}
|
|
|
|
|
2007-02-20 14:58:19 -07:00
|
|
|
static void atmel_spi_cleanup(struct spi_device *spi)
|
2007-02-14 01:33:09 -07:00
|
|
|
{
|
2009-01-06 15:41:43 -07:00
|
|
|
struct atmel_spi_device *asd = spi->controller_state;
|
2007-07-17 05:04:08 -06:00
|
|
|
|
2009-01-06 15:41:43 -07:00
|
|
|
if (!asd)
|
2007-07-17 05:04:08 -06:00
|
|
|
return;
|
|
|
|
|
2009-01-06 15:41:43 -07:00
|
|
|
spi->controller_state = NULL;
|
|
|
|
kfree(asd);
|
2007-02-14 01:33:09 -07:00
|
|
|
}
|
|
|
|
|
2013-03-19 01:42:15 -06:00
|
|
|
static inline unsigned int atmel_get_version(struct atmel_spi *as)
|
|
|
|
{
|
|
|
|
return spi_readl(as, VERSION) & 0x00000fff;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void atmel_get_caps(struct atmel_spi *as)
|
|
|
|
{
|
|
|
|
unsigned int version;
|
|
|
|
|
|
|
|
version = atmel_get_version(as);
|
|
|
|
|
|
|
|
as->caps.is_spi2 = version > 0x121;
|
|
|
|
as->caps.has_wdrbt = version >= 0x210;
|
|
|
|
as->caps.has_dma_support = version >= 0x212;
|
2017-06-23 09:39:16 -06:00
|
|
|
as->caps.has_pdc_support = version < 0x212;
|
2013-03-19 01:42:15 -06:00
|
|
|
}
|
|
|
|
|
2007-02-14 01:33:09 -07:00
|
|
|
/*-------------------------------------------------------------------------*/
|
2016-11-08 10:48:52 -07:00
|
|
|
static int atmel_spi_gpio_cs(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
|
|
|
struct device_node *np = master->dev.of_node;
|
|
|
|
int i;
|
|
|
|
int ret = 0;
|
|
|
|
int nb = 0;
|
|
|
|
|
|
|
|
if (!as->use_cs_gpios)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (!np)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
nb = of_gpio_named_count(np, "cs-gpios");
|
|
|
|
for (i = 0; i < nb; i++) {
|
|
|
|
int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
|
|
|
|
"cs-gpios", i);
|
|
|
|
|
2016-11-14 07:26:44 -07:00
|
|
|
if (cs_gpio == -EPROBE_DEFER)
|
|
|
|
return cs_gpio;
|
2016-11-08 10:48:52 -07:00
|
|
|
|
2016-11-14 07:26:44 -07:00
|
|
|
if (gpio_is_valid(cs_gpio)) {
|
|
|
|
ret = devm_gpio_request(&pdev->dev, cs_gpio,
|
|
|
|
dev_name(&pdev->dev));
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
2016-11-08 10:48:52 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2017-04-12 01:05:19 -06:00
|
|
|
static void atmel_spi_init(struct atmel_spi *as)
|
|
|
|
{
|
|
|
|
spi_writel(as, CR, SPI_BIT(SWRST));
|
|
|
|
spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
|
2018-02-27 03:25:07 -07:00
|
|
|
|
|
|
|
/* It is recommended to enable FIFOs first thing after reset */
|
|
|
|
if (as->fifo_size)
|
|
|
|
spi_writel(as, CR, SPI_BIT(FIFOEN));
|
|
|
|
|
2017-04-12 01:05:19 -06:00
|
|
|
if (as->caps.has_wdrbt) {
|
|
|
|
spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS)
|
|
|
|
| SPI_BIT(MSTR));
|
|
|
|
} else {
|
|
|
|
spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (as->use_pdc)
|
|
|
|
spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
|
|
|
|
spi_writel(as, CR, SPI_BIT(SPIEN));
|
|
|
|
}
|
|
|
|
|
2012-12-07 09:57:14 -07:00
|
|
|
static int atmel_spi_probe(struct platform_device *pdev)
|
2007-02-14 01:33:09 -07:00
|
|
|
{
|
|
|
|
struct resource *regs;
|
|
|
|
int irq;
|
|
|
|
struct clk *clk;
|
|
|
|
int ret;
|
|
|
|
struct spi_master *master;
|
|
|
|
struct atmel_spi *as;
|
|
|
|
|
2014-03-04 18:58:49 -07:00
|
|
|
/* Select default pin state */
|
|
|
|
pinctrl_pm_select_default_state(&pdev->dev);
|
|
|
|
|
2007-02-14 01:33:09 -07:00
|
|
|
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!regs)
|
|
|
|
return -ENXIO;
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
if (irq < 0)
|
|
|
|
return irq;
|
|
|
|
|
2013-12-03 22:07:51 -07:00
|
|
|
clk = devm_clk_get(&pdev->dev, "spi_clk");
|
2007-02-14 01:33:09 -07:00
|
|
|
if (IS_ERR(clk))
|
|
|
|
return PTR_ERR(clk);
|
|
|
|
|
|
|
|
/* setup spi core then atmel-specific driver state */
|
|
|
|
ret = -ENOMEM;
|
2013-09-10 05:36:27 -06:00
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(*as));
|
2007-02-14 01:33:09 -07:00
|
|
|
if (!master)
|
|
|
|
goto out_free;
|
|
|
|
|
2009-06-17 17:26:04 -06:00
|
|
|
/* the spi->mode bits understood by this driver: */
|
|
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
2013-05-21 20:36:35 -06:00
|
|
|
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
|
2012-11-23 05:44:39 -07:00
|
|
|
master->dev.of_node = pdev->dev.of_node;
|
2007-02-14 01:33:09 -07:00
|
|
|
master->bus_num = pdev->id;
|
2012-11-23 05:44:39 -07:00
|
|
|
master->num_chipselect = master->dev.of_node ? 0 : 4;
|
2007-02-14 01:33:09 -07:00
|
|
|
master->setup = atmel_spi_setup;
|
2016-11-24 04:24:58 -07:00
|
|
|
master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
|
2014-01-08 22:19:15 -07:00
|
|
|
master->transfer_one_message = atmel_spi_transfer_one_message;
|
2007-02-14 01:33:09 -07:00
|
|
|
master->cleanup = atmel_spi_cleanup;
|
2014-10-16 03:23:10 -06:00
|
|
|
master->auto_runtime_pm = true;
|
2016-11-24 04:24:58 -07:00
|
|
|
master->max_dma_len = SPI_MAX_DMA_XFER;
|
2016-11-24 04:24:59 -07:00
|
|
|
master->can_dma = atmel_spi_can_dma;
|
2007-02-14 01:33:09 -07:00
|
|
|
platform_set_drvdata(pdev, master);
|
|
|
|
|
|
|
|
as = spi_master_get_devdata(master);
|
|
|
|
|
|
|
|
spin_lock_init(&as->lock);
|
2013-04-02 23:59:19 -06:00
|
|
|
|
2007-02-14 01:33:09 -07:00
|
|
|
as->pdev = pdev;
|
2013-10-16 06:22:35 -06:00
|
|
|
as->regs = devm_ioremap_resource(&pdev->dev, regs);
|
2013-10-20 21:12:02 -06:00
|
|
|
if (IS_ERR(as->regs)) {
|
|
|
|
ret = PTR_ERR(as->regs);
|
2016-11-24 04:24:58 -07:00
|
|
|
goto out_unmap_regs;
|
2013-10-20 21:12:02 -06:00
|
|
|
}
|
2013-04-02 23:57:42 -06:00
|
|
|
as->phybase = regs->start;
|
2007-02-14 01:33:09 -07:00
|
|
|
as->irq = irq;
|
|
|
|
as->clk = clk;
|
|
|
|
|
2014-01-08 22:19:15 -07:00
|
|
|
init_completion(&as->xfer_completion);
|
|
|
|
|
2013-03-19 01:42:15 -06:00
|
|
|
atmel_get_caps(as);
|
|
|
|
|
2015-06-09 05:53:52 -06:00
|
|
|
as->use_cs_gpios = true;
|
|
|
|
if (atmel_spi_is_v2(as) &&
|
2016-01-27 09:48:32 -07:00
|
|
|
pdev->dev.of_node &&
|
2015-06-09 05:53:52 -06:00
|
|
|
!of_get_property(pdev->dev.of_node, "cs-gpios", NULL)) {
|
|
|
|
as->use_cs_gpios = false;
|
|
|
|
master->num_chipselect = 4;
|
|
|
|
}
|
|
|
|
|
2016-11-08 10:48:52 -07:00
|
|
|
ret = atmel_spi_gpio_cs(pdev);
|
|
|
|
if (ret)
|
|
|
|
goto out_unmap_regs;
|
|
|
|
|
2013-04-02 23:59:19 -06:00
|
|
|
as->use_dma = false;
|
|
|
|
as->use_pdc = false;
|
|
|
|
if (as->caps.has_dma_support) {
|
2016-11-24 04:25:01 -07:00
|
|
|
ret = atmel_spi_configure_dma(master, as);
|
2016-11-24 04:24:59 -07:00
|
|
|
if (ret == 0) {
|
2013-04-02 23:59:19 -06:00
|
|
|
as->use_dma = true;
|
2016-11-24 04:24:59 -07:00
|
|
|
} else if (ret == -EPROBE_DEFER) {
|
2014-11-14 09:12:54 -07:00
|
|
|
return ret;
|
2016-11-24 04:24:59 -07:00
|
|
|
}
|
2017-06-23 09:39:16 -06:00
|
|
|
} else if (as->caps.has_pdc_support) {
|
2013-04-02 23:59:19 -06:00
|
|
|
as->use_pdc = true;
|
|
|
|
}
|
|
|
|
|
2017-12-19 08:17:59 -07:00
|
|
|
if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
|
|
|
|
as->addr_rx_bbuf = dma_alloc_coherent(&pdev->dev,
|
|
|
|
SPI_MAX_DMA_XFER,
|
|
|
|
&as->dma_addr_rx_bbuf,
|
|
|
|
GFP_KERNEL | GFP_DMA);
|
|
|
|
if (!as->addr_rx_bbuf) {
|
|
|
|
as->use_dma = false;
|
|
|
|
} else {
|
|
|
|
as->addr_tx_bbuf = dma_alloc_coherent(&pdev->dev,
|
|
|
|
SPI_MAX_DMA_XFER,
|
|
|
|
&as->dma_addr_tx_bbuf,
|
|
|
|
GFP_KERNEL | GFP_DMA);
|
|
|
|
if (!as->addr_tx_bbuf) {
|
|
|
|
as->use_dma = false;
|
|
|
|
dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
|
|
|
|
as->addr_rx_bbuf,
|
|
|
|
as->dma_addr_rx_bbuf);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!as->use_dma)
|
|
|
|
dev_info(master->dev.parent,
|
|
|
|
" can not allocate dma coherent memory\n");
|
|
|
|
}
|
|
|
|
|
2013-04-02 23:59:19 -06:00
|
|
|
if (as->caps.has_dma_support && !as->use_dma)
|
|
|
|
dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
|
|
|
|
|
|
|
|
if (as->use_pdc) {
|
2013-12-03 22:07:51 -07:00
|
|
|
ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt,
|
|
|
|
0, dev_name(&pdev->dev), master);
|
2013-04-02 23:59:19 -06:00
|
|
|
} else {
|
2013-12-03 22:07:51 -07:00
|
|
|
ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt,
|
|
|
|
0, dev_name(&pdev->dev), master);
|
2013-04-02 23:59:19 -06:00
|
|
|
}
|
2007-02-14 01:33:09 -07:00
|
|
|
if (ret)
|
|
|
|
goto out_unmap_regs;
|
|
|
|
|
|
|
|
/* Initialize the hardware */
|
2013-07-16 09:16:22 -06:00
|
|
|
ret = clk_prepare_enable(clk);
|
|
|
|
if (ret)
|
2013-09-10 05:36:26 -06:00
|
|
|
goto out_free_irq;
|
2016-11-14 08:13:20 -07:00
|
|
|
|
|
|
|
as->spi_clk = clk_get_rate(clk);
|
|
|
|
|
spi: atmel: add support to FIFOs
The latest SPI controllers embedded inside sama5d2x SoCs come with FIFOs.
When FIFOs are enabled, they can either work in SINGLE data mode or
MULTIPLE data mode. The selected mode depends on the configuration of the
SPI controller (see below).
In SINGLE data mode (or legacy mode), for a single I/O access, only one
data can be read from the Receive Data Register (RDR) or written into the
Transmit Data Register (TDR). On the other hand, in MULTIPLE data mode, up
to 4 data can be read from the RDR or up 2 data can be written into the
TDR in a single 32bit I/O access. So programmers should take good care of
the width of the I/O access to read/write the right number of data. The
exact number of read/written data depends on both the I/O access width and
the data width (from 8 up to 16 bits).
To enable the FIFO feature a "atmel,fifo-size" property must be set to
provide the maximum number of data (not bytes) the RX and TX FIFOs can
store. Hence a 32 data FIFO can always store up to 32 data unrelated with
the actual data width.
When FIFOs are enabled, the RX one is forced to operate in SINGLE data
mode because this driver configures the spi controller as a master. In
master mode only, the Received Data Register has an additionnal Peripheral
Chip Select field, which prevents us from reading more than a single data
at each register access.
Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a
8bit data size is used, only two data by access could be written into the
Transmit Data Register. Indeed the first data has to be written into the
lowest 16 bits whereas the second data has to be written into the highest
16 bits of the TDR. When DMA transfers are used to send data, we don't
rework the transmit buffer to cope with this hardware limitation: the
additional copies required to prepare a new input buffer suited to both
the DMA controller and the spi controller would waste all the benefit of
the DMA transfer. Instead, the DMA controller is configured to write only
one data at time into the TDR.
In pio mode, two data are written in the TDR in a single access.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-16 04:09:31 -06:00
|
|
|
as->fifo_size = 0;
|
|
|
|
if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
|
|
|
|
&as->fifo_size)) {
|
|
|
|
dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);
|
|
|
|
}
|
|
|
|
|
2017-04-12 01:05:19 -06:00
|
|
|
atmel_spi_init(as);
|
|
|
|
|
2014-10-16 03:23:10 -06:00
|
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
|
|
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
|
|
pm_runtime_set_active(&pdev->dev);
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
|
2013-12-03 22:07:51 -07:00
|
|
|
ret = devm_spi_register_master(&pdev->dev, master);
|
2007-02-14 01:33:09 -07:00
|
|
|
if (ret)
|
2013-04-02 23:59:19 -06:00
|
|
|
goto out_free_dma;
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2016-11-24 04:24:57 -07:00
|
|
|
/* go! */
|
2017-05-29 23:33:30 -06:00
|
|
|
dev_info(&pdev->dev, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n",
|
|
|
|
atmel_get_version(as), (unsigned long)regs->start,
|
|
|
|
irq);
|
2016-11-24 04:24:57 -07:00
|
|
|
|
2007-02-14 01:33:09 -07:00
|
|
|
return 0;
|
|
|
|
|
2013-04-02 23:59:19 -06:00
|
|
|
out_free_dma:
|
2014-10-16 03:23:10 -06:00
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
pm_runtime_set_suspended(&pdev->dev);
|
|
|
|
|
2013-04-02 23:59:19 -06:00
|
|
|
if (as->use_dma)
|
2016-11-24 04:25:01 -07:00
|
|
|
atmel_spi_release_dma(master);
|
2013-04-02 23:59:19 -06:00
|
|
|
|
2007-02-14 01:33:09 -07:00
|
|
|
spi_writel(as, CR, SPI_BIT(SWRST));
|
2008-11-12 14:27:00 -07:00
|
|
|
spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
|
2013-07-16 09:16:22 -06:00
|
|
|
clk_disable_unprepare(clk);
|
2013-09-10 05:36:26 -06:00
|
|
|
out_free_irq:
|
2007-02-14 01:33:09 -07:00
|
|
|
out_unmap_regs:
|
|
|
|
out_free:
|
|
|
|
spi_master_put(master);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-12-07 09:57:14 -07:00
|
|
|
static int atmel_spi_remove(struct platform_device *pdev)
|
2007-02-14 01:33:09 -07:00
|
|
|
{
|
|
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
|
|
|
|
2014-10-16 03:23:10 -06:00
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
|
|
|
2007-02-14 01:33:09 -07:00
|
|
|
/* reset the hardware and block queue progress */
|
2013-04-02 23:59:19 -06:00
|
|
|
if (as->use_dma) {
|
2016-11-24 04:25:01 -07:00
|
|
|
atmel_spi_stop_dma(master);
|
|
|
|
atmel_spi_release_dma(master);
|
2017-12-19 08:17:59 -07:00
|
|
|
if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) {
|
|
|
|
dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
|
|
|
|
as->addr_tx_bbuf,
|
|
|
|
as->dma_addr_tx_bbuf);
|
|
|
|
dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER,
|
|
|
|
as->addr_rx_bbuf,
|
|
|
|
as->dma_addr_rx_bbuf);
|
|
|
|
}
|
2013-04-02 23:59:19 -06:00
|
|
|
}
|
|
|
|
|
2017-12-15 08:40:17 -07:00
|
|
|
spin_lock_irq(&as->lock);
|
2007-02-14 01:33:09 -07:00
|
|
|
spi_writel(as, CR, SPI_BIT(SWRST));
|
2008-11-12 14:27:00 -07:00
|
|
|
spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
|
2007-02-14 01:33:09 -07:00
|
|
|
spi_readl(as, SR);
|
|
|
|
spin_unlock_irq(&as->lock);
|
|
|
|
|
2013-07-16 09:16:22 -06:00
|
|
|
clk_disable_unprepare(as->clk);
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2014-10-16 03:23:10 -06:00
|
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
|
2007-02-14 01:33:09 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-10-16 03:23:10 -06:00
|
|
|
#ifdef CONFIG_PM
|
2014-10-20 21:43:34 -06:00
|
|
|
static int atmel_spi_runtime_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
|
|
|
|
|
|
|
clk_disable_unprepare(as->clk);
|
|
|
|
pinctrl_pm_select_sleep_state(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int atmel_spi_runtime_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
|
|
|
|
|
|
|
pinctrl_pm_select_default_state(dev);
|
|
|
|
|
|
|
|
return clk_prepare_enable(as->clk);
|
|
|
|
}
|
|
|
|
|
2015-09-10 02:19:52 -06:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2013-09-09 02:54:12 -06:00
|
|
|
static int atmel_spi_suspend(struct device *dev)
|
2007-02-14 01:33:09 -07:00
|
|
|
{
|
2014-10-20 21:43:34 -06:00
|
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
2014-03-04 20:29:01 -07:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Stop the queue running */
|
|
|
|
ret = spi_master_suspend(master);
|
2018-09-05 02:51:57 -06:00
|
|
|
if (ret)
|
2014-03-04 20:29:01 -07:00
|
|
|
return ret;
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2014-10-20 21:43:34 -06:00
|
|
|
if (!pm_runtime_suspended(dev))
|
|
|
|
atmel_spi_runtime_suspend(dev);
|
2014-03-04 18:58:49 -07:00
|
|
|
|
2007-02-14 01:33:09 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-09-09 02:54:12 -06:00
|
|
|
static int atmel_spi_resume(struct device *dev)
|
2007-02-14 01:33:09 -07:00
|
|
|
{
|
2014-10-20 21:43:34 -06:00
|
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
2017-04-14 02:22:43 -06:00
|
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
2014-03-04 20:29:01 -07:00
|
|
|
int ret;
|
2007-02-14 01:33:09 -07:00
|
|
|
|
2017-04-14 02:22:43 -06:00
|
|
|
ret = clk_prepare_enable(as->clk);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
atmel_spi_init(as);
|
|
|
|
|
|
|
|
clk_disable_unprepare(as->clk);
|
|
|
|
|
2014-10-16 03:23:10 -06:00
|
|
|
if (!pm_runtime_suspended(dev)) {
|
2014-10-20 21:43:34 -06:00
|
|
|
ret = atmel_spi_runtime_resume(dev);
|
2014-10-16 03:23:10 -06:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
2014-03-04 20:29:01 -07:00
|
|
|
|
|
|
|
/* Start the queue running */
|
2018-09-05 02:51:57 -06:00
|
|
|
return spi_master_resume(master);
|
2007-02-14 01:33:09 -07:00
|
|
|
}
|
2015-09-10 02:19:52 -06:00
|
|
|
#endif
|
2014-10-16 03:23:10 -06:00
|
|
|
|
|
|
|
static const struct dev_pm_ops atmel_spi_pm_ops = {
|
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume)
|
|
|
|
SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend,
|
|
|
|
atmel_spi_runtime_resume, NULL)
|
|
|
|
};
|
2013-09-09 02:54:12 -06:00
|
|
|
#define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops)
|
2007-02-14 01:33:09 -07:00
|
|
|
#else
|
2013-09-09 02:54:12 -06:00
|
|
|
#define ATMEL_SPI_PM_OPS NULL
|
2007-02-14 01:33:09 -07:00
|
|
|
#endif
|
|
|
|
|
2012-11-23 05:44:39 -07:00
|
|
|
#if defined(CONFIG_OF)
|
|
|
|
static const struct of_device_id atmel_spi_dt_ids[] = {
|
|
|
|
{ .compatible = "atmel,at91rm9200-spi" },
|
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
|
|
|
|
|
|
|
MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids);
|
|
|
|
#endif
|
2007-02-14 01:33:09 -07:00
|
|
|
|
|
|
|
static struct platform_driver atmel_spi_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "atmel_spi",
|
2013-09-09 02:54:12 -06:00
|
|
|
.pm = ATMEL_SPI_PM_OPS,
|
2012-11-23 05:44:39 -07:00
|
|
|
.of_match_table = of_match_ptr(atmel_spi_dt_ids),
|
2007-02-14 01:33:09 -07:00
|
|
|
},
|
2011-11-03 11:20:21 -06:00
|
|
|
.probe = atmel_spi_probe,
|
2013-02-05 06:27:35 -07:00
|
|
|
.remove = atmel_spi_remove,
|
2007-02-14 01:33:09 -07:00
|
|
|
};
|
2011-10-05 11:29:49 -06:00
|
|
|
module_platform_driver(atmel_spi_driver);
|
2007-02-14 01:33:09 -07:00
|
|
|
|
|
|
|
MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
|
2011-05-18 08:49:24 -06:00
|
|
|
MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
|
2007-02-14 01:33:09 -07:00
|
|
|
MODULE_LICENSE("GPL");
|
2008-04-10 22:29:20 -06:00
|
|
|
MODULE_ALIAS("platform:atmel_spi");
|