2012-06-22 03:40:49 -06:00
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/*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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2013-06-03 08:12:22 -06:00
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#include "am33xx.dtsi"
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2015-05-03 06:19:28 -06:00
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#include <dt-bindings/interrupt-controller/irq.h>
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2012-06-22 03:40:49 -06:00
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/ {
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model = "TI AM335x EVM";
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compatible = "ti,am335x-evm", "ti,am33xx";
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2012-08-31 03:37:20 -06:00
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cpus {
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cpu@0 {
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cpu0-supply = <&vdd1_reg>;
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};
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};
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2016-08-31 04:35:30 -06:00
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memory@80000000 {
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2012-06-22 03:40:49 -06:00
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device_type = "memory";
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reg = <0x80000000 0x10000000>; /* 256 MB */
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};
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2012-08-15 05:23:25 -06:00
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2017-01-17 21:03:23 -07:00
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chosen {
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stdout-path = &uart0;
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};
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2016-08-01 10:46:58 -06:00
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vbat: fixedregulator0 {
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2012-08-21 05:17:29 -06:00
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compatible = "regulator-fixed";
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regulator-name = "vbat";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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};
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2012-09-19 15:19:29 -06:00
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2016-08-01 10:46:58 -06:00
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lis3_reg: fixedregulator1 {
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2012-09-19 15:19:29 -06:00
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compatible = "regulator-fixed";
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regulator-name = "lis3_reg";
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regulator-boot-on;
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};
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2012-11-06 06:48:30 -07:00
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2016-08-01 10:46:58 -06:00
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wlan_en_reg: fixedregulator2 {
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2015-05-03 06:19:28 -06:00
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compatible = "regulator-fixed";
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regulator-name = "wlan-en-regulator";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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/* WLAN_EN GPIO for this board - Bank1, pin16 */
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gpio = <&gpio1 16 0>;
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/* WLAN card specific delay */
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startup-delay-us = <70000>;
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enable-active-high;
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};
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2019-03-15 04:59:09 -06:00
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/* TPS79501 */
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v1_8d_reg: fixedregulator-v1_8d {
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compatible = "regulator-fixed";
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regulator-name = "v1_8d";
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vin-supply = <&vbat>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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/* TPS79501 */
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v3_3d_reg: fixedregulator-v3_3d {
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compatible = "regulator-fixed";
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regulator-name = "v3_3d";
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vin-supply = <&vbat>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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2016-08-01 10:46:57 -06:00
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matrix_keypad: matrix_keypad0 {
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2012-11-06 06:48:30 -07:00
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compatible = "gpio-matrix-keypad";
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debounce-delay-ms = <5>;
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col-scan-delay-us = <2>;
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2013-06-03 08:12:23 -06:00
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row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
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&gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
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&gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
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2012-11-06 06:48:30 -07:00
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2013-06-03 08:12:23 -06:00
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col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
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&gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
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2012-11-06 06:48:30 -07:00
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linux,keymap = <0x0000008b /* MENU */
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0x0100009e /* BACK */
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0x02000069 /* LEFT */
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0x0001006a /* RIGHT */
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0x0101001c /* ENTER */
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0x0201006c>; /* DOWN */
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};
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2012-11-06 06:48:32 -07:00
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2016-08-01 10:47:01 -06:00
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gpio_keys: volume_keys0 {
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2012-11-06 06:48:32 -07:00
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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autorepeat;
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2016-08-01 10:47:01 -06:00
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switch9 {
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2012-11-06 06:48:32 -07:00
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label = "volume-up";
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linux,code = <115>;
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2013-06-03 08:12:23 -06:00
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gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
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2015-10-21 04:10:06 -06:00
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wakeup-source;
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2012-11-06 06:48:32 -07:00
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};
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2016-08-01 10:47:01 -06:00
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switch10 {
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2012-11-06 06:48:32 -07:00
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label = "volume-down";
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linux,code = <114>;
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2013-06-03 08:12:23 -06:00
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gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
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2015-10-21 04:10:06 -06:00
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wakeup-source;
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2012-11-06 06:48:32 -07:00
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};
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};
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2013-06-06 07:52:38 -06:00
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backlight {
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compatible = "pwm-backlight";
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pwms = <&ecap0 0 50000 0>;
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brightness-levels = <0 51 53 56 62 75 101 152 255>;
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default-brightness-level = <8>;
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};
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2013-08-08 17:28:14 -06:00
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panel {
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compatible = "ti,tilcdc,panel";
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&lcd_pins_s0>;
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panel-info {
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ac-bias = <255>;
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ac-bias-intrpt = <0>;
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dma-burst-sz = <16>;
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bpp = <32>;
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fdd = <0x80>;
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sync-edge = <0>;
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sync-ctrl = <1>;
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raster-order = <0>;
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fifo-th = <0>;
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};
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display-timings {
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800x480p62 {
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clock-frequency = <30000000>;
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hactive = <800>;
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vactive = <480>;
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hfront-porch = <39>;
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hback-porch = <39>;
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hsync-len = <47>;
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vback-porch = <29>;
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vfront-porch = <13>;
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vsync-len = <2>;
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hsync-active = <1>;
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vsync-active = <1>;
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};
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};
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};
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2013-10-20 11:04:10 -06:00
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sound {
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2015-07-02 08:06:35 -06:00
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compatible = "simple-audio-card";
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simple-audio-card,name = "AM335x-EVM";
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simple-audio-card,widgets =
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"Headphone", "Headphone Jack",
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"Line", "Line In";
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simple-audio-card,routing =
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"Headphone Jack", "HPLOUT",
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"Headphone Jack", "HPROUT",
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"LINE1L", "Line In",
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"LINE1R", "Line In";
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simple-audio-card,format = "dsp_b";
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simple-audio-card,bitclock-master = <&sound_master>;
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simple-audio-card,frame-master = <&sound_master>;
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simple-audio-card,bitclock-inversion;
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simple-audio-card,cpu {
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sound-dai = <&mcasp1>;
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};
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sound_master: simple-audio-card,codec {
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sound-dai = <&tlv320aic3106>;
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system-clock-frequency = <12000000>;
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};
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2013-10-20 11:04:10 -06:00
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};
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2012-08-21 05:17:29 -06:00
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};
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2013-09-20 09:00:00 -06:00
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&am33xx_pinmux {
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pinctrl-names = "default";
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pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
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matrix_keypad_s0: matrix_keypad_s0 {
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pinctrl-single,pins = <
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2015-11-12 21:53:46 -07:00
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AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
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AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
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AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
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AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
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AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
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2013-09-20 09:00:00 -06:00
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>;
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};
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volume_keys_s0: volume_keys_s0 {
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pinctrl-single,pins = <
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2015-11-12 21:53:46 -07:00
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AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
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AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
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2013-09-20 09:00:00 -06:00
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>;
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};
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i2c0_pins: pinmux_i2c0_pins {
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pinctrl-single,pins = <
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2015-11-12 21:53:46 -07:00
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AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
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AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
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2013-09-20 09:00:00 -06:00
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>;
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};
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i2c1_pins: pinmux_i2c1_pins {
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pinctrl-single,pins = <
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2015-11-12 21:53:46 -07:00
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AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
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AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
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2013-09-20 09:00:00 -06:00
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>;
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};
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uart0_pins: pinmux_uart0_pins {
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pinctrl-single,pins = <
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2015-11-12 21:53:46 -07:00
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AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
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AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
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2013-09-20 09:00:00 -06:00
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>;
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};
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2015-05-04 06:41:13 -06:00
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uart1_pins: pinmux_uart1_pins {
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pinctrl-single,pins = <
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2015-11-12 21:53:46 -07:00
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AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
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AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
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AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
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AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
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2015-05-04 06:41:13 -06:00
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>;
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};
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2013-09-20 09:00:00 -06:00
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clkout2_pin: pinmux_clkout2_pin {
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pinctrl-single,pins = <
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2015-11-12 21:53:46 -07:00
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AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
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2013-09-20 09:00:00 -06:00
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>;
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};
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nandflash_pins_s0: nandflash_pins_s0 {
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pinctrl-single,pins = <
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2015-11-12 21:53:46 -07:00
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AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
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AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
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AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
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AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
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AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
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AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
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AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
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AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
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AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
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AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
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AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
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AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
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AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
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AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
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AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
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2013-09-20 09:00:00 -06:00
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>;
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};
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ecap0_pins: backlight_pins {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-12 21:53:46 -07:00
|
|
|
AM33XX_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
|
2013-09-20 09:00:00 -06:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpsw_default: cpsw_default {
|
|
|
|
|
pinctrl-single,pins = <
|
|
|
|
|
/* Slave 1 */
|
2015-11-12 21:53:46 -07:00
|
|
|
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
|
|
|
|
|
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
|
|
|
|
|
AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
|
|
|
|
|
AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
|
|
|
|
|
AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
|
|
|
|
|
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
|
|
|
|
|
AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
|
|
|
|
|
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
|
|
|
|
|
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
|
|
|
|
|
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
|
|
|
|
|
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
|
|
|
|
|
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
|
2013-09-20 09:00:00 -06:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpsw_sleep: cpsw_sleep {
|
|
|
|
|
pinctrl-single,pins = <
|
|
|
|
|
/* Slave 1 reset value */
|
2015-11-12 21:53:46 -07:00
|
|
|
AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
|
|
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
|
|
AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
|
|
AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
|
|
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
|
|
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
|
|
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
|
|
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
|
|
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
|
|
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
|
|
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
|
|
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
2013-09-20 09:00:00 -06:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
davinci_mdio_default: davinci_mdio_default {
|
|
|
|
|
pinctrl-single,pins = <
|
|
|
|
|
/* MDIO */
|
2015-11-12 21:53:46 -07:00
|
|
|
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
|
|
|
|
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
2013-09-20 09:00:00 -06:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
davinci_mdio_sleep: davinci_mdio_sleep {
|
|
|
|
|
pinctrl-single,pins = <
|
|
|
|
|
/* MDIO reset value */
|
2015-11-12 21:53:46 -07:00
|
|
|
AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
|
|
AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
2013-09-20 09:00:00 -06:00
|
|
|
>;
|
|
|
|
|
};
|
2013-08-08 17:28:14 -06:00
|
|
|
|
2014-03-03 07:50:19 -07:00
|
|
|
mmc1_pins: pinmux_mmc1_pins {
|
|
|
|
|
pinctrl-single,pins = <
|
2018-04-11 05:48:24 -06:00
|
|
|
AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
|
|
|
|
|
AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
|
|
|
|
|
AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
|
|
|
|
|
AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
|
|
|
|
|
AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
|
|
|
|
|
AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
|
|
|
|
|
AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
|
|
|
|
|
AM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */
|
2014-03-03 07:50:19 -07:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2015-05-03 06:19:28 -06:00
|
|
|
mmc3_pins: pinmux_mmc3_pins {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-12 21:53:46 -07:00
|
|
|
AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
|
|
|
|
|
AM33XX_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
|
|
|
|
|
AM33XX_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
|
|
|
|
|
AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
|
|
|
|
|
AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
|
|
|
|
|
AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
|
2015-05-03 06:19:28 -06:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
wlan_pins: pinmux_wlan_pins {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-12 21:53:46 -07:00
|
|
|
AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */
|
|
|
|
|
AM33XX_IOPAD(0x99c, PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */
|
|
|
|
|
AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
|
2015-05-03 06:19:28 -06:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-08-08 17:28:14 -06:00
|
|
|
lcd_pins_s0: lcd_pins_s0 {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-12 21:53:46 -07:00
|
|
|
AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
|
|
|
|
|
AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
|
|
|
|
|
AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
|
|
|
|
|
AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
|
|
|
|
|
AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
|
|
|
|
|
AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
|
|
|
|
|
AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
|
|
|
|
|
AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
|
|
|
|
|
AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
|
|
|
|
|
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
|
|
|
|
|
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
|
|
|
|
|
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
|
|
|
|
|
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
|
|
|
|
|
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
|
|
|
|
|
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
|
|
|
|
|
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
|
|
|
|
|
AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
|
|
|
|
|
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
|
|
|
|
|
AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
|
|
|
|
|
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
|
|
|
|
|
AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
|
|
|
|
|
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
|
|
|
|
|
AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
|
|
|
|
|
AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
|
|
|
|
|
AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
|
|
|
|
|
AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
|
|
|
|
|
AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
|
|
|
|
|
AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
|
2013-08-08 17:28:14 -06:00
|
|
|
>;
|
|
|
|
|
};
|
2013-10-20 11:04:10 -06:00
|
|
|
|
2015-07-02 08:06:33 -06:00
|
|
|
mcasp1_pins: mcasp1_pins {
|
2013-10-20 11:04:10 -06:00
|
|
|
pinctrl-single,pins = <
|
2015-11-12 21:53:46 -07:00
|
|
|
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
|
|
|
|
|
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
|
|
|
|
|
AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
|
|
|
|
|
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
|
2013-10-20 11:04:10 -06:00
|
|
|
>;
|
|
|
|
|
};
|
2014-10-29 09:52:57 -06:00
|
|
|
|
2015-07-02 08:06:34 -06:00
|
|
|
mcasp1_pins_sleep: mcasp1_pins_sleep {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-12 21:53:46 -07:00
|
|
|
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
|
|
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
|
|
AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
|
|
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
2015-07-02 08:06:34 -06:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-10-29 09:52:57 -06:00
|
|
|
dcan1_pins_default: dcan1_pins_default {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-12 21:53:46 -07:00
|
|
|
AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
|
|
|
|
|
AM33XX_IOPAD(0x96c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
|
2014-10-29 09:52:57 -06:00
|
|
|
>;
|
|
|
|
|
};
|
2013-09-20 09:00:00 -06:00
|
|
|
};
|
|
|
|
|
|
2013-09-20 09:42:19 -06:00
|
|
|
&uart0 {
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&uart0_pins>;
|
|
|
|
|
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2015-05-04 06:41:13 -06:00
|
|
|
&uart1 {
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&uart1_pins>;
|
|
|
|
|
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2013-09-20 09:42:19 -06:00
|
|
|
&i2c0 {
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&i2c0_pins>;
|
|
|
|
|
|
|
|
|
|
status = "okay";
|
|
|
|
|
clock-frequency = <400000>;
|
|
|
|
|
|
|
|
|
|
tps: tps@2d {
|
|
|
|
|
reg = <0x2d>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&usb {
|
|
|
|
|
status = "okay";
|
2014-04-28 14:54:33 -06:00
|
|
|
};
|
2013-09-20 09:42:19 -06:00
|
|
|
|
2014-04-28 14:54:33 -06:00
|
|
|
&usb_ctrl_mod {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
2013-09-20 09:42:19 -06:00
|
|
|
|
2014-04-28 14:54:33 -06:00
|
|
|
&usb0_phy {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
2013-09-20 09:42:19 -06:00
|
|
|
|
2014-04-28 14:54:33 -06:00
|
|
|
&usb1_phy {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
2013-09-20 09:42:19 -06:00
|
|
|
|
2014-04-28 14:54:33 -06:00
|
|
|
&usb0 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
2013-09-20 09:42:19 -06:00
|
|
|
|
2014-04-28 14:54:33 -06:00
|
|
|
&usb1 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
dr_mode = "host";
|
|
|
|
|
};
|
2013-09-20 09:42:19 -06:00
|
|
|
|
2014-04-28 14:54:33 -06:00
|
|
|
&cppi41dma {
|
|
|
|
|
status = "okay";
|
2013-09-20 09:42:19 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&i2c1 {
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&i2c1_pins>;
|
|
|
|
|
|
|
|
|
|
status = "okay";
|
|
|
|
|
clock-frequency = <100000>;
|
|
|
|
|
|
|
|
|
|
lis331dlh: lis331dlh@18 {
|
|
|
|
|
compatible = "st,lis331dlh", "st,lis3lv02d";
|
|
|
|
|
reg = <0x18>;
|
|
|
|
|
Vdd-supply = <&lis3_reg>;
|
|
|
|
|
Vdd_IO-supply = <&lis3_reg>;
|
|
|
|
|
|
|
|
|
|
st,click-single-x;
|
|
|
|
|
st,click-single-y;
|
|
|
|
|
st,click-single-z;
|
|
|
|
|
st,click-thresh-x = <10>;
|
|
|
|
|
st,click-thresh-y = <10>;
|
|
|
|
|
st,click-thresh-z = <10>;
|
|
|
|
|
st,irq1-click;
|
|
|
|
|
st,irq2-click;
|
|
|
|
|
st,wakeup-x-lo;
|
|
|
|
|
st,wakeup-x-hi;
|
|
|
|
|
st,wakeup-y-lo;
|
|
|
|
|
st,wakeup-y-hi;
|
|
|
|
|
st,wakeup-z-lo;
|
|
|
|
|
st,wakeup-z-hi;
|
|
|
|
|
st,min-limit-x = <120>;
|
|
|
|
|
st,min-limit-y = <120>;
|
|
|
|
|
st,min-limit-z = <140>;
|
|
|
|
|
st,max-limit-x = <550>;
|
|
|
|
|
st,max-limit-y = <550>;
|
|
|
|
|
st,max-limit-z = <750>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
tsl2550: tsl2550@39 {
|
|
|
|
|
compatible = "taos,tsl2550";
|
|
|
|
|
reg = <0x39>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
tmp275: tmp275@48 {
|
|
|
|
|
compatible = "ti,tmp275";
|
|
|
|
|
reg = <0x48>;
|
|
|
|
|
};
|
2013-10-20 11:04:10 -06:00
|
|
|
|
|
|
|
|
tlv320aic3106: tlv320aic3106@1b {
|
2015-07-02 08:06:35 -06:00
|
|
|
#sound-dai-cells = <0>;
|
2013-10-20 11:04:10 -06:00
|
|
|
compatible = "ti,tlv320aic3106";
|
|
|
|
|
reg = <0x1b>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
/* Regulators */
|
2019-03-15 04:59:09 -06:00
|
|
|
AVDD-supply = <&v3_3d_reg>;
|
|
|
|
|
IOVDD-supply = <&v3_3d_reg>;
|
|
|
|
|
DRVDD-supply = <&v3_3d_reg>;
|
|
|
|
|
DVDD-supply = <&v1_8d_reg>;
|
2013-10-20 11:04:10 -06:00
|
|
|
};
|
2013-09-20 09:42:19 -06:00
|
|
|
};
|
|
|
|
|
|
2013-08-08 17:28:14 -06:00
|
|
|
&lcdc {
|
|
|
|
|
status = "okay";
|
2016-09-16 05:50:11 -06:00
|
|
|
|
|
|
|
|
blue-and-red-wiring = "crossed";
|
2013-08-08 17:28:14 -06:00
|
|
|
};
|
|
|
|
|
|
2013-09-20 09:42:19 -06:00
|
|
|
&elm {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&epwmss0 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
2018-12-10 14:43:11 -07:00
|
|
|
ecap0: ecap@100 {
|
2013-09-20 09:42:19 -06:00
|
|
|
status = "okay";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&ecap0_pins>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&gpmc {
|
|
|
|
|
status = "okay";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&nandflash_pins_s0>;
|
2014-10-29 18:16:47 -06:00
|
|
|
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
|
2013-09-20 09:42:19 -06:00
|
|
|
nand@0,0 {
|
2016-02-23 09:37:21 -07:00
|
|
|
compatible = "ti,omap2-nand";
|
2014-10-29 18:16:47 -06:00
|
|
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
2016-02-23 09:37:21 -07:00
|
|
|
interrupt-parent = <&gpmc>;
|
|
|
|
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
|
|
|
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
2016-04-07 04:25:39 -06:00
|
|
|
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
|
2017-07-25 20:15:50 -06:00
|
|
|
ti,nand-xfer-type = "prefetch-dma";
|
2013-09-20 09:42:19 -06:00
|
|
|
ti,nand-ecc-opt = "bch8";
|
2014-02-05 06:28:32 -07:00
|
|
|
ti,elm-id = <&elm>;
|
|
|
|
|
nand-bus-width = <8>;
|
2013-09-20 09:42:19 -06:00
|
|
|
gpmc,device-width = <1>;
|
|
|
|
|
gpmc,sync-clk-ps = <0>;
|
|
|
|
|
gpmc,cs-on-ns = <0>;
|
|
|
|
|
gpmc,cs-rd-off-ns = <44>;
|
|
|
|
|
gpmc,cs-wr-off-ns = <44>;
|
|
|
|
|
gpmc,adv-on-ns = <6>;
|
|
|
|
|
gpmc,adv-rd-off-ns = <34>;
|
|
|
|
|
gpmc,adv-wr-off-ns = <44>;
|
|
|
|
|
gpmc,we-on-ns = <0>;
|
|
|
|
|
gpmc,we-off-ns = <40>;
|
|
|
|
|
gpmc,oe-on-ns = <0>;
|
|
|
|
|
gpmc,oe-off-ns = <54>;
|
|
|
|
|
gpmc,access-ns = <64>;
|
|
|
|
|
gpmc,rd-cycle-ns = <82>;
|
|
|
|
|
gpmc,wr-cycle-ns = <82>;
|
|
|
|
|
gpmc,bus-turnaround-ns = <0>;
|
|
|
|
|
gpmc,cycle2cycle-delay-ns = <0>;
|
|
|
|
|
gpmc,clk-activation-ns = <0>;
|
|
|
|
|
gpmc,wr-access-ns = <40>;
|
|
|
|
|
gpmc,wr-data-mux-bus-ns = <0>;
|
|
|
|
|
/* MTD partition table */
|
2014-02-05 06:28:31 -07:00
|
|
|
/* All SPL-* partitions are sized to minimal length
|
|
|
|
|
* which can be independently programmable. For
|
|
|
|
|
* NAND flash this is equal to size of erase-block */
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
2013-09-20 09:42:19 -06:00
|
|
|
partition@0 {
|
2014-02-05 06:28:31 -07:00
|
|
|
label = "NAND.SPL";
|
2013-09-20 09:42:19 -06:00
|
|
|
reg = <0x00000000 0x000020000>;
|
|
|
|
|
};
|
|
|
|
|
partition@1 {
|
2014-02-05 06:28:31 -07:00
|
|
|
label = "NAND.SPL.backup1";
|
2013-09-20 09:42:19 -06:00
|
|
|
reg = <0x00020000 0x00020000>;
|
|
|
|
|
};
|
|
|
|
|
partition@2 {
|
2014-02-05 06:28:31 -07:00
|
|
|
label = "NAND.SPL.backup2";
|
2013-09-20 09:42:19 -06:00
|
|
|
reg = <0x00040000 0x00020000>;
|
|
|
|
|
};
|
|
|
|
|
partition@3 {
|
2014-02-05 06:28:31 -07:00
|
|
|
label = "NAND.SPL.backup3";
|
2013-09-20 09:42:19 -06:00
|
|
|
reg = <0x00060000 0x00020000>;
|
|
|
|
|
};
|
|
|
|
|
partition@4 {
|
2014-10-21 05:25:45 -06:00
|
|
|
label = "NAND.u-boot-spl-os";
|
2014-02-05 06:28:31 -07:00
|
|
|
reg = <0x00080000 0x00040000>;
|
2013-09-20 09:42:19 -06:00
|
|
|
};
|
|
|
|
|
partition@5 {
|
2014-02-05 06:28:31 -07:00
|
|
|
label = "NAND.u-boot";
|
|
|
|
|
reg = <0x000C0000 0x00100000>;
|
2013-09-20 09:42:19 -06:00
|
|
|
};
|
|
|
|
|
partition@6 {
|
2014-02-05 06:28:31 -07:00
|
|
|
label = "NAND.u-boot-env";
|
|
|
|
|
reg = <0x001C0000 0x00020000>;
|
2013-09-20 09:42:19 -06:00
|
|
|
};
|
|
|
|
|
partition@7 {
|
2014-02-05 06:28:31 -07:00
|
|
|
label = "NAND.u-boot-env.backup1";
|
|
|
|
|
reg = <0x001E0000 0x00020000>;
|
|
|
|
|
};
|
|
|
|
|
partition@8 {
|
|
|
|
|
label = "NAND.kernel";
|
|
|
|
|
reg = <0x00200000 0x00800000>;
|
|
|
|
|
};
|
|
|
|
|
partition@9 {
|
|
|
|
|
label = "NAND.file-system";
|
|
|
|
|
reg = <0x00A00000 0x0F600000>;
|
2013-09-20 09:42:19 -06:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2013-06-03 08:12:22 -06:00
|
|
|
#include "tps65910.dtsi"
|
2012-08-21 05:17:29 -06:00
|
|
|
|
2013-10-20 11:04:10 -06:00
|
|
|
&mcasp1 {
|
2015-07-02 08:06:35 -06:00
|
|
|
#sound-dai-cells = <0>;
|
2015-07-02 08:06:34 -06:00
|
|
|
pinctrl-names = "default", "sleep";
|
2015-07-02 08:06:33 -06:00
|
|
|
pinctrl-0 = <&mcasp1_pins>;
|
2015-07-02 08:06:34 -06:00
|
|
|
pinctrl-1 = <&mcasp1_pins_sleep>;
|
2013-10-20 11:04:10 -06:00
|
|
|
|
2015-07-02 08:06:32 -06:00
|
|
|
status = "okay";
|
2013-10-20 11:04:10 -06:00
|
|
|
|
2015-07-02 08:06:32 -06:00
|
|
|
op-mode = <0>; /* MCASP_IIS_MODE */
|
|
|
|
|
tdm-slots = <2>;
|
|
|
|
|
/* 4 serializers */
|
|
|
|
|
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
|
|
|
|
|
0 0 1 2
|
|
|
|
|
>;
|
|
|
|
|
tx-num-evt = <32>;
|
|
|
|
|
rx-num-evt = <32>;
|
2013-10-20 11:04:10 -06:00
|
|
|
};
|
|
|
|
|
|
2012-08-21 05:17:29 -06:00
|
|
|
&tps {
|
|
|
|
|
vcc1-supply = <&vbat>;
|
|
|
|
|
vcc2-supply = <&vbat>;
|
|
|
|
|
vcc3-supply = <&vbat>;
|
|
|
|
|
vcc4-supply = <&vbat>;
|
|
|
|
|
vcc5-supply = <&vbat>;
|
|
|
|
|
vcc6-supply = <&vbat>;
|
|
|
|
|
vcc7-supply = <&vbat>;
|
|
|
|
|
vccio-supply = <&vbat>;
|
|
|
|
|
|
|
|
|
|
regulators {
|
|
|
|
|
vrtc_reg: regulator@0 {
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vio_reg: regulator@1 {
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vdd1_reg: regulator@2 {
|
|
|
|
|
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
|
|
|
|
regulator-name = "vdd_mpu";
|
|
|
|
|
regulator-min-microvolt = <912500>;
|
2016-05-18 17:36:26 -06:00
|
|
|
regulator-max-microvolt = <1351500>;
|
2012-08-21 05:17:29 -06:00
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vdd2_reg: regulator@3 {
|
|
|
|
|
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
|
|
|
|
regulator-name = "vdd_core";
|
|
|
|
|
regulator-min-microvolt = <912500>;
|
|
|
|
|
regulator-max-microvolt = <1150000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vdd3_reg: regulator@4 {
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vdig1_reg: regulator@5 {
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vdig2_reg: regulator@6 {
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vpll_reg: regulator@7 {
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vdac_reg: regulator@8 {
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vaux1_reg: regulator@9 {
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vaux2_reg: regulator@10 {
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vaux33_reg: regulator@11 {
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vmmc_reg: regulator@12 {
|
2013-09-10 13:24:39 -06:00
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
2012-08-21 05:17:29 -06:00
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
2012-08-15 05:23:25 -06:00
|
|
|
};
|
2012-06-22 03:40:49 -06:00
|
|
|
};
|
2012-11-14 02:08:00 -07:00
|
|
|
|
2013-06-07 05:32:54 -06:00
|
|
|
&mac {
|
|
|
|
|
pinctrl-names = "default", "sleep";
|
|
|
|
|
pinctrl-0 = <&cpsw_default>;
|
|
|
|
|
pinctrl-1 = <&cpsw_sleep>;
|
2014-05-08 02:57:36 -06:00
|
|
|
status = "okay";
|
2018-09-08 16:33:40 -06:00
|
|
|
slaves = <1>;
|
2013-06-07 05:32:54 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&davinci_mdio {
|
|
|
|
|
pinctrl-names = "default", "sleep";
|
|
|
|
|
pinctrl-0 = <&davinci_mdio_default>;
|
|
|
|
|
pinctrl-1 = <&davinci_mdio_sleep>;
|
2014-05-08 02:57:36 -06:00
|
|
|
status = "okay";
|
2013-06-07 05:32:54 -06:00
|
|
|
|
2018-09-08 16:33:40 -06:00
|
|
|
ethphy0: ethernet-phy@0 {
|
|
|
|
|
reg = <0>;
|
|
|
|
|
};
|
2012-11-14 02:08:00 -07:00
|
|
|
};
|
|
|
|
|
|
2018-09-08 16:33:40 -06:00
|
|
|
&cpsw_emac0 {
|
|
|
|
|
phy-handle = <ðphy0>;
|
2019-02-19 09:46:33 -07:00
|
|
|
phy-mode = "rgmii-id";
|
2012-11-14 02:08:00 -07:00
|
|
|
};
|
2013-01-23 20:45:12 -07:00
|
|
|
|
|
|
|
|
&tscadc {
|
|
|
|
|
status = "okay";
|
|
|
|
|
tsc {
|
|
|
|
|
ti,wires = <4>;
|
|
|
|
|
ti,x-plate-resistance = <200>;
|
2013-11-11 00:56:43 -07:00
|
|
|
ti,coordinate-readouts = <5>;
|
2013-01-23 20:45:12 -07:00
|
|
|
ti,wire-config = <0x00 0x11 0x22 0x33>;
|
2015-02-03 12:46:36 -07:00
|
|
|
ti,charge-delay = <0x400>;
|
2013-01-23 20:45:12 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
adc {
|
2013-05-29 09:39:02 -06:00
|
|
|
ti,adc-channels = <4 5 6 7>;
|
2013-01-23 20:45:12 -07:00
|
|
|
};
|
|
|
|
|
};
|
2013-09-10 13:24:39 -06:00
|
|
|
|
|
|
|
|
&mmc1 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
vmmc-supply = <&vmmc_reg>;
|
2013-09-27 05:35:10 -06:00
|
|
|
bus-width = <4>;
|
2014-03-03 07:50:19 -07:00
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&mmc1_pins>;
|
2015-10-12 03:07:10 -06:00
|
|
|
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
|
2013-09-10 13:24:39 -06:00
|
|
|
};
|
2013-08-23 15:12:35 -06:00
|
|
|
|
2015-05-03 06:19:28 -06:00
|
|
|
&mmc3 {
|
|
|
|
|
/* these are on the crossbar and are outlined in the
|
|
|
|
|
xbar-event-map element */
|
2015-12-17 06:33:36 -07:00
|
|
|
dmas = <&edma_xbar 12 0 1
|
|
|
|
|
&edma_xbar 13 0 2>;
|
2015-05-03 06:19:28 -06:00
|
|
|
dma-names = "tx", "rx";
|
|
|
|
|
status = "okay";
|
|
|
|
|
vmmc-supply = <&wlan_en_reg>;
|
|
|
|
|
bus-width = <4>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&mmc3_pins &wlan_pins>;
|
|
|
|
|
ti,non-removable;
|
|
|
|
|
ti,needs-special-hs-handling;
|
|
|
|
|
cap-power-off-card;
|
|
|
|
|
keep-power-in-suspend;
|
|
|
|
|
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
wlcore: wlcore@0 {
|
|
|
|
|
compatible = "ti,wl1835";
|
|
|
|
|
reg = <2>;
|
|
|
|
|
interrupt-parent = <&gpio3>;
|
2018-07-03 00:57:20 -06:00
|
|
|
interrupts = <17 IRQ_TYPE_EDGE_RISING>;
|
2015-05-03 06:19:28 -06:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2013-08-23 15:12:35 -06:00
|
|
|
&sham {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
2013-08-23 15:12:36 -06:00
|
|
|
|
|
|
|
|
&aes {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
2014-10-29 09:52:57 -06:00
|
|
|
|
|
|
|
|
&dcan1 {
|
|
|
|
|
status = "disabled"; /* Enable only if Profile 1 is selected */
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&dcan1_pins_default>;
|
|
|
|
|
};
|
2016-10-26 23:48:07 -06:00
|
|
|
|
|
|
|
|
&rtc {
|
2018-08-31 09:14:49 -06:00
|
|
|
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
|
2016-10-26 23:48:07 -06:00
|
|
|
clock-names = "ext-clk", "int-clk";
|
|
|
|
|
};
|
