191 lines
5.4 KiB
ArmAsm
191 lines
5.4 KiB
ArmAsm
![]() |
/*
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* tbictxfpu.S
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*
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* Copyright (C) 2009, 2012 Imagination Technologies.
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*
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* This program is free software; you can redistribute it and/or modify it under
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* the terms of the GNU General Public License version 2 as published by the
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* Free Software Foundation.
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*
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* Explicit state save and restore routines forming part of the thread binary
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* interface for META processors
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*/
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.file "tbifpuctx.S"
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#include <asm/metag_regs.h>
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#include <asm/tbx.h>
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#ifdef TBI_1_4
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/*
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* void *__TBICtxFPUSave( TBIRES State, void *pExt )
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*
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* D0Ar2 contains TBICTX_*_BIT values that control what
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* extended data is to be saved.
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* These bits must be ored into the SaveMask of this structure.
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*
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* Virtually all possible scratch registers are used.
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*/
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.text
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.balign 4
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.global ___TBICtxFPUSave
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.type ___TBICtxFPUSave,function
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___TBICtxFPUSave:
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/* D1Ar1:D0Ar2 - State
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* D1Ar3 - pExt
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* D0Ar4 - Value of METAC_CORE_ID
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* D1Ar5 - Scratch
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* D0Ar6 - Scratch
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*/
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/* If the FPAC bit isnt set then there is nothing to do */
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TSTT D0Ar2,#TBICTX_FPAC_BIT
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MOVZ PC, D1RtP
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/* Obtain the Core config */
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MOVT D0Ar4, #HI(METAC_CORE_ID)
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ADD D0Ar4, D0Ar4, #LO(METAC_CORE_ID)
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GETD D0Ar4, [D0Ar4]
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/* Detect FX.8 - FX.15 and add to core config */
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MOV D0Ar6, TXENABLE
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AND D0Ar6, D0Ar6, #(TXENABLE_CLASSALT_FPUR8 << TXENABLE_CLASS_S)
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AND D0Ar4, D0Ar4, #LO(0x0000FFFF)
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ORT D0Ar4, D0Ar4, #HI(TBICTX_CFGFPU_FX16_BIT)
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XOR D0Ar4, D0Ar4, D0Ar6
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/* Save the relevant bits to the buffer */
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SETD [D1Ar3++], D0Ar4
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/* Save the relevant bits of TXDEFR (Assumes TXDEFR is coherent) ... */
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MOV D0Ar6, TXDEFR
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LSR D0Re0, D0Ar6, #8
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AND D0Re0, D0Re0, #LO(TXDEFR_FPE_FE_BITS>>8)
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AND D0Ar6, D0Ar6, #LO(TXDEFR_FPE_ICTRL_BITS)
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OR D0Re0, D0Re0, D0Ar6
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/* ... along with relevant bits of TXMODE to buffer */
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MOV D0Ar6, TXMODE
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ANDT D0Ar6, D0Ar6, #HI(TXMODE_FPURMODE_BITS)
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ORT D0Ar6, D0Ar6, #HI(TXMODE_FPURMODEWRITE_BIT)
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OR D0Ar6, D0Ar6, D0Re0
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SETD [D1Ar3++], D0Ar6
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GETD D0Ar6,[D1Ar1+#TBICTX_SaveMask-2] /* Get the current SaveMask */
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/* D0Ar6 - pCtx->SaveMask */
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TSTT D0Ar4, #HI(TBICTX_CFGFPU_FX16_BIT) /* Perform test here for extended FPU registers
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* to avoid stalls
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*/
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/* Save the standard FPU registers */
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F MSETL [D1Ar3++], FX.0, FX.2, FX.4, FX.6
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/* Save the extended FPU registers if they are present */
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BZ $Lskip_save_fx8_fx16
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F MSETL [D1Ar3++], FX.8, FX.10, FX.12, FX.14
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$Lskip_save_fx8_fx16:
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/* Save the FPU Accumulator if it is present */
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TST D0Ar4, #METAC_COREID_NOFPACC_BIT
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BNZ $Lskip_save_fpacc
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F SETL [D1Ar3++], ACF.0
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F SETL [D1Ar3++], ACF.1
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F SETL [D1Ar3++], ACF.2
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$Lskip_save_fpacc:
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/* Update pCtx->SaveMask */
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ANDT D0Ar2, D0Ar2, #TBICTX_FPAC_BIT
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OR D0Ar6, D0Ar6, D0Ar2
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SETD [D1Ar1+#TBICTX_SaveMask-2],D0Ar6/* Add in XCBF bit to TBICTX */
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MOV D0Re0, D1Ar3 /* Return end of save area */
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MOV PC, D1RtP
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.size ___TBICtxFPUSave,.-___TBICtxFPUSave
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/*
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* void *__TBICtxFPURestore( TBIRES State, void *pExt )
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*
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* D0Ar2 contains TBICTX_*_BIT values that control what
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* extended data is to be recovered from D1Ar3 (pExt).
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*
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* Virtually all possible scratch registers are used.
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*/
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/*
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* If TBICTX_XEXT_BIT is specified in State. Then the saved state of
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* the orginal A0.2 and A1.2 is restored from pExt and the XEXT
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* related flags are removed from State.pCtx->SaveMask.
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*
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*/
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.balign 4
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.global ___TBICtxFPURestore
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.type ___TBICtxFPURestore,function
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___TBICtxFPURestore:
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/* D1Ar1:D0Ar2 - State
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* D1Ar3 - pExt
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* D0Ar4 - Value of METAC_CORE_ID
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* D1Ar5 - Scratch
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* D0Ar6 - Scratch
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* D1Re0 - Scratch
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*/
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/* If the FPAC bit isnt set then there is nothing to do */
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TSTT D0Ar2,#TBICTX_FPAC_BIT
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MOVZ PC, D1RtP
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/* Obtain the relevant bits of the Core config */
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GETD D0Ar4, [D1Ar3++]
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/* Restore FPU related parts of TXDEFR. Assumes TXDEFR is coherent */
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GETD D1Ar5, [D1Ar3++]
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MOV D0Ar6, D1Ar5
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LSL D1Re0, D1Ar5, #8
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ANDT D1Re0, D1Re0, #HI(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS)
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AND D1Ar5, D1Ar5, #LO(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS)
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OR D1Re0, D1Re0, D1Ar5
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MOV D1Ar5, TXDEFR
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ANDMT D1Ar5, D1Ar5, #HI(~(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS))
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ANDMB D1Ar5, D1Ar5, #LO(~(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS))
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OR D1Re0, D1Re0, D1Ar5
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MOV TXDEFR, D1Re0
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/* Restore relevant bits of TXMODE */
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MOV D1Ar5, TXMODE
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ANDMT D1Ar5, D1Ar5, #HI(~TXMODE_FPURMODE_BITS)
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ANDT D0Ar6, D0Ar6, #HI(TXMODE_FPURMODE_BITS|TXMODE_FPURMODEWRITE_BIT)
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OR D0Ar6, D0Ar6, D1Ar5
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MOV TXMODE, D0Ar6
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TSTT D0Ar4, #HI(TBICTX_CFGFPU_FX16_BIT) /* Perform test here for extended FPU registers
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* to avoid stalls
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*/
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/* Save the standard FPU registers */
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F MGETL FX.0, FX.2, FX.4, FX.6, [D1Ar3++]
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/* Save the extended FPU registers if they are present */
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BZ $Lskip_restore_fx8_fx16
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F MGETL FX.8, FX.10, FX.12, FX.14, [D1Ar3++]
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$Lskip_restore_fx8_fx16:
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/* Save the FPU Accumulator if it is present */
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TST D0Ar4, #METAC_COREID_NOFPACC_BIT
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BNZ $Lskip_restore_fpacc
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F GETL ACF.0, [D1Ar3++]
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F GETL ACF.1, [D1Ar3++]
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F GETL ACF.2, [D1Ar3++]
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$Lskip_restore_fpacc:
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MOV D0Re0, D1Ar3 /* Return end of save area */
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MOV PC, D1RtP
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.size ___TBICtxFPURestore,.-___TBICtxFPURestore
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#endif /* TBI_1_4 */
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/*
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* End of tbictx.S
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*/
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