2019-05-28 11:10:04 -06:00
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// SPDX-License-Identifier: GPL-2.0-only
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2014-06-12 09:36:37 -06:00
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/*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <soc/tegra/fuse.h>
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2015-05-04 05:30:50 -06:00
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#include <soc/tegra/common.h>
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2014-06-12 09:36:37 -06:00
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#include "fuse.h"
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#define FUSE_SKU_INFO 0x10
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2015-03-12 08:47:55 -06:00
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#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT 4
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#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG \
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(0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
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#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \
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(0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
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static bool long_ram_code;
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static u32 strapping;
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static u32 chipid;
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2014-06-12 09:36:37 -06:00
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u32 tegra_read_chipid(void)
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{
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2020-07-17 07:41:42 -06:00
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WARN(!chipid, "Tegra APB MISC not yet available\n");
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2014-06-12 09:36:37 -06:00
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2019-12-18 11:23:01 -07:00
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return chipid;
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2017-06-26 09:21:17 -06:00
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}
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u8 tegra_get_chip_id(void)
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{
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2014-07-11 03:13:30 -06:00
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return (tegra_read_chipid() >> 8) & 0xff;
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2014-06-12 09:36:37 -06:00
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}
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soc/tegra: fuse: Add custom SoC attributes
Add a custom SoC attribute for Tegra to expose the HIDREV register
fields to userspace via the sysfs. This register provides additional
details about the type of device (eg, silicon, FPGA, etc) as well as
revision. Exposing this information is useful for identifying the
exact device revision and device type.
For Tegra devices up until Tegra186, the majorrev and minorrev fields of
the HIDREV register are used to determine the device revision and device
type. For Tegra194, the majorrev and minorrev fields only determine the
revision. Starting with Tegra194, there is an additional field,
pre_si_platform (which occupies bits 20-23), that now determines device
type. Therefore, for all Tegra devices, add a custom SoC attribute for
the majorrev and minorrev fields and for Tegra194 add an additional
attribute for the pre_si_platform field.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-04-17 06:39:48 -06:00
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u8 tegra_get_major_rev(void)
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{
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return (tegra_read_chipid() >> 4) & 0xf;
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}
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u8 tegra_get_minor_rev(void)
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{
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return (tegra_read_chipid() >> 16) & 0xf;
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}
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2020-09-17 04:07:45 -06:00
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u8 tegra_get_platform(void)
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{
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return (tegra_read_chipid() >> 20) & 0xf;
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}
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2020-09-17 04:07:46 -06:00
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bool tegra_is_silicon(void)
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{
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switch (tegra_get_chip_id()) {
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case TEGRA194:
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case TEGRA234:
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if (tegra_get_platform() == 0)
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return true;
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return false;
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}
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/*
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* Chips prior to Tegra194 have a different way of determining whether
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* they are silicon or not. Since we never supported simulation on the
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* older Tegra chips, don't bother extracting the information and just
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* report that we're running on silicon.
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*/
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return true;
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}
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u32 tegra_read_straps(void)
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{
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WARN(!chipid, "Tegra ABP MISC not yet available\n");
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2019-12-18 11:23:01 -07:00
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return strapping;
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}
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2015-03-12 08:47:55 -06:00
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u32 tegra_read_ram_code(void)
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{
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u32 straps = tegra_read_straps();
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if (long_ram_code)
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straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;
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else
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straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;
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return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;
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}
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2014-06-12 09:36:37 -06:00
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static const struct of_device_id apbmisc_match[] __initconst = {
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{ .compatible = "nvidia,tegra20-apbmisc", },
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{ .compatible = "nvidia,tegra186-misc", },
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2020-01-03 01:30:17 -07:00
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{ .compatible = "nvidia,tegra194-misc", },
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2020-09-17 04:07:48 -06:00
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{ .compatible = "nvidia,tegra234-misc", },
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{},
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};
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void __init tegra_init_revision(void)
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{
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u8 chip_id, minor_rev;
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2020-04-17 06:39:49 -06:00
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chip_id = tegra_get_chip_id();
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minor_rev = tegra_get_minor_rev();
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2014-06-12 09:36:37 -06:00
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switch (minor_rev) {
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case 1:
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tegra_sku_info.revision = TEGRA_REVISION_A01;
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break;
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case 2:
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tegra_sku_info.revision = TEGRA_REVISION_A02;
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break;
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case 3:
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if (chip_id == TEGRA20 && (tegra_fuse_read_spare(18) ||
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tegra_fuse_read_spare(19)))
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tegra_sku_info.revision = TEGRA_REVISION_A03p;
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else
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tegra_sku_info.revision = TEGRA_REVISION_A03;
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break;
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case 4:
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tegra_sku_info.revision = TEGRA_REVISION_A04;
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break;
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default:
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tegra_sku_info.revision = TEGRA_REVISION_UNKNOWN;
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}
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2015-04-29 08:54:04 -06:00
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tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO);
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}
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void __init tegra_init_apbmisc(void)
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{
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void __iomem *apbmisc_base, *strapping_base;
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struct resource apbmisc, straps;
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struct device_node *np;
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np = of_find_matching_node(NULL, apbmisc_match);
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if (!np) {
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/*
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* Fall back to legacy initialization for 32-bit ARM only. All
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* 64-bit ARM device tree files for Tegra are required to have
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* an APBMISC node.
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*
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* This is for backwards-compatibility with old device trees
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* that didn't contain an APBMISC node.
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*/
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if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
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/* APBMISC registers (chip revision, ...) */
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apbmisc.start = 0x70000800;
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apbmisc.end = 0x70000863;
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apbmisc.flags = IORESOURCE_MEM;
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/* strapping options */
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if (of_machine_is_compatible("nvidia,tegra124")) {
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straps.start = 0x7000e864;
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straps.end = 0x7000e867;
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} else {
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straps.start = 0x70000008;
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straps.end = 0x7000000b;
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}
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straps.flags = IORESOURCE_MEM;
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pr_warn("Using APBMISC region %pR\n", &apbmisc);
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pr_warn("Using strapping options registers %pR\n",
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&straps);
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} else {
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/*
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* At this point we're not running on Tegra, so play
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* nice with multi-platform kernels.
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*/
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return;
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}
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} else {
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/*
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* Extract information from the device tree if we've found a
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* matching node.
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*/
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if (of_address_to_resource(np, 0, &apbmisc) < 0) {
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pr_err("failed to get APBMISC registers\n");
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return;
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}
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if (of_address_to_resource(np, 1, &straps) < 0) {
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pr_err("failed to get strapping options registers\n");
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return;
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}
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}
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2020-01-06 01:43:50 -07:00
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apbmisc_base = ioremap(apbmisc.start, resource_size(&apbmisc));
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if (!apbmisc_base) {
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pr_err("failed to map APBMISC registers\n");
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} else {
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chipid = readl_relaxed(apbmisc_base + 4);
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iounmap(apbmisc_base);
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}
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2015-05-04 05:30:50 -06:00
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2020-01-06 01:43:50 -07:00
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strapping_base = ioremap(straps.start, resource_size(&straps));
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if (!strapping_base) {
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pr_err("failed to map strapping options registers\n");
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2019-12-18 11:23:04 -07:00
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} else {
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strapping = readl_relaxed(strapping_base);
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2019-12-18 11:23:04 -07:00
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iounmap(strapping_base);
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}
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2015-03-12 08:47:55 -06:00
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long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
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2014-06-12 09:36:37 -06:00
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}
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