2007-10-18 10:48:11 -06:00
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2007 MIPS Technologies, Inc.
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* Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
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*/
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/percpu.h>
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2009-06-19 07:05:26 -06:00
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#include <linux/smp.h>
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2010-10-07 07:08:54 -06:00
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#include <linux/irq.h>
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2007-10-18 10:48:11 -06:00
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#include <asm/time.h>
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2008-09-09 13:48:52 -06:00
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#include <asm/cevt-r4k.h>
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2007-10-18 10:48:11 -06:00
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static int mips_next_event(unsigned long delta,
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2013-01-22 04:59:30 -07:00
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struct clock_event_device *evt)
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2007-10-18 10:48:11 -06:00
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{
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unsigned int cnt;
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int res;
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cnt = read_c0_count();
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cnt += delta;
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write_c0_compare(cnt);
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2010-11-23 11:26:44 -07:00
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res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0;
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2007-10-18 10:48:11 -06:00
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return res;
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}
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2008-09-09 13:48:52 -06:00
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DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
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int cp0_timer_irq_installed;
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2007-10-18 10:48:11 -06:00
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2015-01-27 14:45:47 -07:00
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/*
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* Possibly handle a performance counter interrupt.
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* Return true if the timer interrupt should not be checked
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*/
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static inline int handle_perf_irq(int r2)
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{
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/*
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* The performance counter overflow interrupt may be shared with the
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* timer interrupt (cp0_perfcount_irq < 0). If it is and a
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* performance counter has overflowed (perf_irq() == IRQ_HANDLED)
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* and we can't reliably determine if a counter interrupt has also
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* happened (!r2) then don't check for a timer interrupt.
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*/
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return (cp0_perfcount_irq < 0) &&
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perf_irq() == IRQ_HANDLED &&
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!r2;
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}
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2008-09-09 13:48:52 -06:00
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irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
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2007-10-18 10:48:11 -06:00
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{
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2014-11-13 06:39:39 -07:00
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const int r2 = cpu_has_mips_r2_r6;
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2007-10-18 10:48:11 -06:00
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struct clock_event_device *cd;
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int cpu = smp_processor_id();
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/*
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* Suckage alert:
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* Before R2 of the architecture there was no way to see if a
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* performance counter interrupt was pending, so we have to run
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* the performance counter interrupt handler anyway.
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*/
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if (handle_perf_irq(r2))
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2015-03-20 12:45:09 -06:00
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return IRQ_HANDLED;
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2007-10-18 10:48:11 -06:00
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/*
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2013-01-22 04:59:30 -07:00
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* The same applies to performance counter interrupts. But with the
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2007-10-18 10:48:11 -06:00
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* above we now know that the reason we got here must be a timer
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* interrupt. Being the paranoiacs we are we check anyway.
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*/
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2015-01-27 14:45:48 -07:00
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if (!r2 || (read_c0_cause() & CAUSEF_TI)) {
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2008-09-09 13:48:52 -06:00
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/* Clear Count/Compare Interrupt */
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write_c0_compare(read_c0_compare());
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2007-10-18 10:48:11 -06:00
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cd = &per_cpu(mips_clockevent_device, cpu);
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cd->event_handler(cd);
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2015-03-20 12:45:09 -06:00
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return IRQ_HANDLED;
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2007-10-18 10:48:11 -06:00
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}
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2015-03-20 12:45:09 -06:00
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return IRQ_NONE;
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2007-10-18 10:48:11 -06:00
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}
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2008-09-09 13:48:52 -06:00
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struct irqaction c0_compare_irqaction = {
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2007-10-18 10:48:11 -06:00
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.handler = c0_compare_interrupt,
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2015-01-27 14:45:52 -07:00
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/*
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* IRQF_SHARED: The timer interrupt may be shared with other interrupts
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* such as perf counter and FDC interrupts.
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*/
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.flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED,
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2007-10-18 10:48:11 -06:00
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.name = "timer",
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};
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2008-09-09 13:48:52 -06:00
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void mips_event_handler(struct clock_event_device *dev)
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2007-10-18 10:48:11 -06:00
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{
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}
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/*
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* FIXME: This doesn't hold for the relocated E9000 compare interrupt.
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*/
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static int c0_compare_int_pending(void)
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{
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2015-01-19 05:00:55 -07:00
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/* When cpu_has_mips_r2, this checks Cause.TI instead of Cause.IP7 */
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2009-12-21 18:49:22 -07:00
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return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
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2007-10-18 10:48:11 -06:00
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}
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2008-09-09 13:48:52 -06:00
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/*
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* Compare interrupt can be routed and latched outside the core,
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2011-11-08 07:59:01 -07:00
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* so wait up to worst case number of cycle counter ticks for timer interrupt
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* changes to propagate to the cause register.
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2008-09-09 13:48:52 -06:00
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*/
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2011-11-08 07:59:01 -07:00
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#define COMPARE_INT_SEEN_TICKS 50
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2008-09-09 13:48:52 -06:00
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int c0_compare_int_usable(void)
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2007-10-18 10:48:11 -06:00
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{
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2007-10-23 06:55:42 -06:00
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unsigned int delta;
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2007-10-18 10:48:11 -06:00
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unsigned int cnt;
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2012-11-21 19:34:03 -07:00
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#ifdef CONFIG_KVM_GUEST
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return 1;
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#endif
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2007-10-18 10:48:11 -06:00
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/*
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2013-01-22 04:59:30 -07:00
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* IP7 already pending? Try to clear it by acking the timer.
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2007-10-18 10:48:11 -06:00
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*/
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if (c0_compare_int_pending()) {
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2011-11-08 07:59:01 -07:00
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cnt = read_c0_count();
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write_c0_compare(cnt);
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back_to_back_c0_hazard();
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while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
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if (!c0_compare_int_pending())
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break;
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2007-10-18 10:48:11 -06:00
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if (c0_compare_int_pending())
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return 0;
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}
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2007-10-23 06:55:42 -06:00
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for (delta = 0x10; delta <= 0x400000; delta <<= 1) {
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cnt = read_c0_count();
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cnt += delta;
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write_c0_compare(cnt);
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2011-11-08 07:59:01 -07:00
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back_to_back_c0_hazard();
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2007-10-23 06:55:42 -06:00
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if ((int)(read_c0_count() - cnt) < 0)
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break;
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/* increase delta if the timer was already expired */
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}
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2007-10-18 10:48:11 -06:00
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2007-10-23 06:51:19 -06:00
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while ((int)(read_c0_count() - cnt) <= 0)
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2007-10-18 10:48:11 -06:00
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; /* Wait for expiry */
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2011-11-08 07:59:01 -07:00
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while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
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if (c0_compare_int_pending())
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break;
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2007-10-18 10:48:11 -06:00
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if (!c0_compare_int_pending())
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return 0;
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2011-11-08 07:59:01 -07:00
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cnt = read_c0_count();
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write_c0_compare(cnt);
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back_to_back_c0_hazard();
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while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
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if (!c0_compare_int_pending())
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break;
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2007-10-18 10:48:11 -06:00
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if (c0_compare_int_pending())
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return 0;
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/*
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* Feels like a real count / compare timer.
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*/
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return 1;
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}
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2015-07-12 17:11:38 -06:00
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unsigned int __weak get_c0_compare_int(void)
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{
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return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
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}
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MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code
commit 3747069b25e419f6b51395f48127e9812abc3596 upstream.
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
Here, we remove all the MIPS __cpuinit from C code and __CPUINIT
from asm files. MIPS is interesting in this respect, because there
are also uasm users hiding behind their own renamed versions of the
__cpuinit macros.
[1] https://lkml.org/lkml/2013/5/20/589
[ralf@linux-mips.org: Folded in Paul's followup fix.]
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5494/
Patchwork: https://patchwork.linux-mips.org/patch/5495/
Patchwork: https://patchwork.linux-mips.org/patch/5509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-18 07:38:59 -06:00
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int r4k_clockevent_init(void)
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2007-10-18 10:48:11 -06:00
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{
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unsigned int cpu = smp_processor_id();
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struct clock_event_device *cd;
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2007-10-29 08:23:43 -06:00
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unsigned int irq;
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2007-10-18 10:48:11 -06:00
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2007-10-26 07:27:05 -06:00
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if (!cpu_has_counter || !mips_hpt_frequency)
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2007-11-21 09:39:44 -07:00
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return -ENXIO;
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2007-10-18 10:48:11 -06:00
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if (!c0_compare_int_usable())
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2007-11-21 09:39:44 -07:00
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return -ENXIO;
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2007-10-18 10:48:11 -06:00
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2007-10-29 08:23:43 -06:00
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/*
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* With vectored interrupts things are getting platform specific.
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* get_c0_compare_int is a hook to allow a platform to return the
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2015-07-12 17:11:38 -06:00
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* interrupt number of its liking.
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2007-10-29 08:23:43 -06:00
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*/
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2015-07-12 17:11:38 -06:00
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irq = get_c0_compare_int();
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2007-10-29 08:23:43 -06:00
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2007-10-18 10:48:11 -06:00
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cd = &per_cpu(mips_clockevent_device, cpu);
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cd->name = "MIPS";
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2014-02-14 02:20:15 -07:00
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cd->features = CLOCK_EVT_FEAT_ONESHOT |
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2014-04-15 05:05:24 -06:00
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CLOCK_EVT_FEAT_C3STOP |
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CLOCK_EVT_FEAT_PERCPU;
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2007-10-18 10:48:11 -06:00
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2010-05-19 11:40:53 -06:00
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clockevent_set_clock(cd, mips_hpt_frequency);
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2007-10-18 10:48:11 -06:00
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/* Calculate the min / max delta */
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cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
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cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
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cd->rating = 300;
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cd->irq = irq;
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2008-12-13 03:50:26 -07:00
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cd->cpumask = cpumask_of(cpu);
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2007-10-18 10:48:11 -06:00
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cd->set_next_event = mips_next_event;
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cd->event_handler = mips_event_handler;
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clockevents_register_device(cd);
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2007-10-29 20:21:08 -06:00
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if (cp0_timer_irq_installed)
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2007-11-21 09:39:44 -07:00
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return 0;
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2007-10-29 08:23:43 -06:00
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cp0_timer_irq_installed = 1;
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setup_irq(irq, &c0_compare_irqaction);
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2007-11-21 09:39:44 -07:00
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return 0;
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2007-10-18 10:48:11 -06:00
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}
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2008-09-09 13:48:52 -06:00
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