2005-10-10 06:36:14 -06:00
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/*
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* This file contains miscellaneous low-level functions.
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
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* and Paul Mackerras.
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* Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
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2006-06-27 19:55:49 -06:00
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* PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
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*
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2005-10-10 06:36:14 -06:00
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/sys.h>
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#include <asm/unistd.h>
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#include <asm/errno.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cache.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cputable.h>
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[PATCH] powerpc: Merge thread_info.h
Merge ppc32 and ppc64 versions of thread_info.h. They were pretty
similar already, the chief changes are:
- Instead of inline asm to implement current_thread_info(),
which needs to be different for ppc32 and ppc64, we use C with an
asm("r1") register variable. gcc turns it into the same asm as we
used to have for both platforms.
- We replace ppc32's 'local_flags' with the ppc64
'syscall_noerror' field. The noerror flag was in fact the only thing
in the local_flags field anyway, so the ppc64 approach is simpler, and
means we only need a load-immediate/store instead of load/mask/store
when clearing the flag.
- In readiness for 64k pages, when THREAD_SIZE will be less
than a page, ppc64 used kmalloc() rather than get_free_pages() to
allocate the kernel stack. With this patch we do the same for ppc32,
since there's no strong reason not to.
- For ppc64, we no longer export THREAD_SHIFT and THREAD_SIZE
via asm-offsets, thread_info.h can now be safely included in asm, as
on ppc32.
Built and booted on G4 Powerbook (ARCH=ppc and ARCH=powerpc) and
Power5 (ARCH=ppc64 and ARCH=powerpc).
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-10-20 23:45:50 -06:00
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#include <asm/thread_info.h>
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2005-10-10 06:36:14 -06:00
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.text
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_GLOBAL(get_msr)
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mfmsr r3
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blr
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_GLOBAL(get_srr0)
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mfsrr0 r3
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blr
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_GLOBAL(get_srr1)
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mfsrr1 r3
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blr
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#ifdef CONFIG_IRQSTACKS
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_GLOBAL(call_do_softirq)
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mflr r0
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std r0,16(r1)
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stdu r1,THREAD_SIZE-112(r3)
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mr r1,r3
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bl .__do_softirq
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ld r1,0(r1)
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ld r0,16(r1)
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mtlr r0
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blr
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2006-07-03 03:32:51 -06:00
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_GLOBAL(call_handle_irq)
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IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 07:55:46 -06:00
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ld r8,0(r6)
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2005-10-10 06:36:14 -06:00
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mflr r0
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std r0,16(r1)
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2006-07-03 03:32:51 -06:00
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mtctr r8
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IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 07:55:46 -06:00
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stdu r1,THREAD_SIZE-112(r5)
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mr r1,r5
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2006-07-03 03:32:51 -06:00
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bctrl
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2005-10-10 06:36:14 -06:00
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ld r1,0(r1)
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ld r0,16(r1)
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mtlr r0
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blr
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#endif /* CONFIG_IRQSTACKS */
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.section ".toc","aw"
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PPC64_CACHES:
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.tc ppc64_caches[TC],ppc64_caches
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.section ".text"
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/*
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* Write any modified data cache blocks out to memory
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* and invalidate the corresponding instruction cache blocks.
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*
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* flush_icache_range(unsigned long start, unsigned long stop)
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*
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* flush all bytes from start through stop-1 inclusive
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*/
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_KPROBE(__flush_icache_range)
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/*
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* Flush the data cache to memory
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*
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* Different systems have different cache line sizes
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* and in some cases i-cache and d-cache line sizes differ from
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* each other.
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*/
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ld r10,PPC64_CACHES@toc(r2)
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lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */
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addi r5,r7,-1
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andc r6,r3,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5 /* ensure we get enough */
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lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */
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srw. r8,r8,r9 /* compute line count */
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beqlr /* nothing to do? */
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mtctr r8
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1: dcbst 0,r6
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add r6,r6,r7
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bdnz 1b
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sync
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/* Now invalidate the instruction cache */
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lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */
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addi r5,r7,-1
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andc r6,r3,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5
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lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */
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srw. r8,r8,r9 /* compute line count */
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beqlr /* nothing to do? */
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mtctr r8
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2: icbi 0,r6
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add r6,r6,r7
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bdnz 2b
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isync
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blr
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.previous .text
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/*
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* Like above, but only do the D-cache.
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*
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* flush_dcache_range(unsigned long start, unsigned long stop)
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*
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* flush all bytes from start to stop-1 inclusive
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*/
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_GLOBAL(flush_dcache_range)
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/*
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* Flush the data cache to memory
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*
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* Different systems have different cache line sizes
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*/
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ld r10,PPC64_CACHES@toc(r2)
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lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
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addi r5,r7,-1
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andc r6,r3,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5 /* ensure we get enough */
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lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
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srw. r8,r8,r9 /* compute line count */
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beqlr /* nothing to do? */
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mtctr r8
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0: dcbst 0,r6
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add r6,r6,r7
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bdnz 0b
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sync
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blr
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/*
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* Like above, but works on non-mapped physical addresses.
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* Use only for non-LPAR setups ! It also assumes real mode
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* is cacheable. Used for flushing out the DART before using
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* it as uncacheable memory
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*
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* flush_dcache_phys_range(unsigned long start, unsigned long stop)
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*
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* flush all bytes from start to stop-1 inclusive
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*/
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_GLOBAL(flush_dcache_phys_range)
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ld r10,PPC64_CACHES@toc(r2)
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lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
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addi r5,r7,-1
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andc r6,r3,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5 /* ensure we get enough */
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lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
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srw. r8,r8,r9 /* compute line count */
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beqlr /* nothing to do? */
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mfmsr r5 /* Disable MMU Data Relocation */
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ori r0,r5,MSR_DR
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xori r0,r0,MSR_DR
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sync
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mtmsr r0
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sync
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isync
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mtctr r8
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0: dcbst 0,r6
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add r6,r6,r7
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bdnz 0b
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sync
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isync
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mtmsr r5 /* Re-enable MMU Data Relocation */
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sync
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isync
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blr
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_GLOBAL(flush_inval_dcache_range)
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ld r10,PPC64_CACHES@toc(r2)
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lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
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addi r5,r7,-1
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andc r6,r3,r5 /* round low to line bdy */
|
|
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|
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subf r8,r6,r4 /* compute length */
|
|
|
|
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add r8,r8,r5 /* ensure we get enough */
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lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */
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srw. r8,r8,r9 /* compute line count */
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beqlr /* nothing to do? */
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sync
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isync
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mtctr r8
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0: dcbf 0,r6
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add r6,r6,r7
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bdnz 0b
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sync
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isync
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blr
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/*
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* Flush a particular page from the data cache to RAM.
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* Note: this is necessary because the instruction cache does *not*
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* snoop from the data cache.
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*
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* void __flush_dcache_icache(void *page)
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*/
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_GLOBAL(__flush_dcache_icache)
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/*
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* Flush the data cache to memory
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*
|
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* Different systems have different cache line sizes
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*/
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/* Flush the dcache */
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ld r7,PPC64_CACHES@toc(r2)
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clrrdi r3,r3,PAGE_SHIFT /* Page align */
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lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */
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|
lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */
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mr r6,r3
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mtctr r4
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0: dcbst 0,r6
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add r6,r6,r5
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bdnz 0b
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sync
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/* Now invalidate the icache */
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lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */
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|
lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */
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|
|
|
|
mtctr r4
|
|
|
|
|
1: icbi 0,r3
|
|
|
|
|
add r3,r3,r5
|
|
|
|
|
bdnz 1b
|
|
|
|
|
isync
|
|
|
|
|
blr
|
|
|
|
|
|
2006-09-25 02:19:00 -06:00
|
|
|
|
2005-10-10 06:36:14 -06:00
|
|
|
#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
|
|
|
|
|
/*
|
|
|
|
|
* Do an IO access in real mode
|
|
|
|
|
*/
|
|
|
|
|
_GLOBAL(real_readb)
|
|
|
|
|
mfmsr r7
|
|
|
|
|
ori r0,r7,MSR_DR
|
|
|
|
|
xori r0,r0,MSR_DR
|
|
|
|
|
sync
|
|
|
|
|
mtmsrd r0
|
|
|
|
|
sync
|
|
|
|
|
isync
|
|
|
|
|
mfspr r6,SPRN_HID4
|
|
|
|
|
rldicl r5,r6,32,0
|
|
|
|
|
ori r5,r5,0x100
|
|
|
|
|
rldicl r5,r5,32,0
|
|
|
|
|
sync
|
|
|
|
|
mtspr SPRN_HID4,r5
|
|
|
|
|
isync
|
|
|
|
|
slbia
|
|
|
|
|
isync
|
|
|
|
|
lbz r3,0(r3)
|
|
|
|
|
sync
|
|
|
|
|
mtspr SPRN_HID4,r6
|
|
|
|
|
isync
|
|
|
|
|
slbia
|
|
|
|
|
isync
|
|
|
|
|
mtmsrd r7
|
|
|
|
|
sync
|
|
|
|
|
isync
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Do an IO access in real mode
|
|
|
|
|
*/
|
|
|
|
|
_GLOBAL(real_writeb)
|
|
|
|
|
mfmsr r7
|
|
|
|
|
ori r0,r7,MSR_DR
|
|
|
|
|
xori r0,r0,MSR_DR
|
|
|
|
|
sync
|
|
|
|
|
mtmsrd r0
|
|
|
|
|
sync
|
|
|
|
|
isync
|
|
|
|
|
mfspr r6,SPRN_HID4
|
|
|
|
|
rldicl r5,r6,32,0
|
|
|
|
|
ori r5,r5,0x100
|
|
|
|
|
rldicl r5,r5,32,0
|
|
|
|
|
sync
|
|
|
|
|
mtspr SPRN_HID4,r5
|
|
|
|
|
isync
|
|
|
|
|
slbia
|
|
|
|
|
isync
|
|
|
|
|
stb r3,0(r4)
|
|
|
|
|
sync
|
|
|
|
|
mtspr SPRN_HID4,r6
|
|
|
|
|
isync
|
|
|
|
|
slbia
|
|
|
|
|
isync
|
|
|
|
|
mtmsrd r7
|
|
|
|
|
sync
|
|
|
|
|
isync
|
|
|
|
|
blr
|
|
|
|
|
#endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
|
|
|
|
|
|
2007-02-04 15:36:49 -07:00
|
|
|
#ifdef CONFIG_PPC_PASEMI
|
|
|
|
|
|
|
|
|
|
/* No support in all binutils for these yet, so use defines */
|
|
|
|
|
#define LBZCIX(RT,RA,RB) .long (0x7c0006aa|(RT<<21)|(RA<<16)|(RB << 11))
|
|
|
|
|
#define STBCIX(RS,RA,RB) .long (0x7c0007aa|(RS<<21)|(RA<<16)|(RB << 11))
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
_GLOBAL(real_205_readb)
|
|
|
|
|
mfmsr r7
|
|
|
|
|
ori r0,r7,MSR_DR
|
|
|
|
|
xori r0,r0,MSR_DR
|
|
|
|
|
sync
|
|
|
|
|
mtmsrd r0
|
|
|
|
|
sync
|
|
|
|
|
isync
|
|
|
|
|
LBZCIX(r3,0,r3)
|
|
|
|
|
isync
|
|
|
|
|
mtmsrd r7
|
|
|
|
|
sync
|
|
|
|
|
isync
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
_GLOBAL(real_205_writeb)
|
|
|
|
|
mfmsr r7
|
|
|
|
|
ori r0,r7,MSR_DR
|
|
|
|
|
xori r0,r0,MSR_DR
|
|
|
|
|
sync
|
|
|
|
|
mtmsrd r0
|
|
|
|
|
sync
|
|
|
|
|
isync
|
|
|
|
|
STBCIX(r3,0,r4)
|
|
|
|
|
isync
|
|
|
|
|
mtmsrd r7
|
|
|
|
|
sync
|
|
|
|
|
isync
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
#endif /* CONFIG_PPC_PASEMI */
|
|
|
|
|
|
|
|
|
|
|
2006-06-27 19:55:49 -06:00
|
|
|
#ifdef CONFIG_CPU_FREQ_PMAC64
|
2005-11-06 20:27:33 -07:00
|
|
|
/*
|
|
|
|
|
* SCOM access functions for 970 (FX only for now)
|
|
|
|
|
*
|
|
|
|
|
* unsigned long scom970_read(unsigned int address);
|
|
|
|
|
* void scom970_write(unsigned int address, unsigned long value);
|
|
|
|
|
*
|
|
|
|
|
* The address passed in is the 24 bits register address. This code
|
|
|
|
|
* is 970 specific and will not check the status bits, so you should
|
|
|
|
|
* know what you are doing.
|
|
|
|
|
*/
|
|
|
|
|
_GLOBAL(scom970_read)
|
|
|
|
|
/* interrupts off */
|
|
|
|
|
mfmsr r4
|
|
|
|
|
ori r0,r4,MSR_EE
|
|
|
|
|
xori r0,r0,MSR_EE
|
|
|
|
|
mtmsrd r0,1
|
|
|
|
|
|
|
|
|
|
/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
|
|
|
|
|
* (including parity). On current CPUs they must be 0'd,
|
|
|
|
|
* and finally or in RW bit
|
|
|
|
|
*/
|
|
|
|
|
rlwinm r3,r3,8,0,15
|
|
|
|
|
ori r3,r3,0x8000
|
|
|
|
|
|
|
|
|
|
/* do the actual scom read */
|
|
|
|
|
sync
|
|
|
|
|
mtspr SPRN_SCOMC,r3
|
|
|
|
|
isync
|
|
|
|
|
mfspr r3,SPRN_SCOMD
|
|
|
|
|
isync
|
|
|
|
|
mfspr r0,SPRN_SCOMC
|
|
|
|
|
isync
|
|
|
|
|
|
|
|
|
|
/* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
|
|
|
|
|
* that's the best we can do). Not implemented yet as we don't use
|
|
|
|
|
* the scom on any of the bogus CPUs yet, but may have to be done
|
|
|
|
|
* ultimately
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/* restore interrupts */
|
|
|
|
|
mtmsrd r4,1
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
_GLOBAL(scom970_write)
|
|
|
|
|
/* interrupts off */
|
|
|
|
|
mfmsr r5
|
|
|
|
|
ori r0,r5,MSR_EE
|
|
|
|
|
xori r0,r0,MSR_EE
|
|
|
|
|
mtmsrd r0,1
|
|
|
|
|
|
|
|
|
|
/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
|
|
|
|
|
* (including parity). On current CPUs they must be 0'd.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
rlwinm r3,r3,8,0,15
|
|
|
|
|
|
|
|
|
|
sync
|
|
|
|
|
mtspr SPRN_SCOMD,r4 /* write data */
|
|
|
|
|
isync
|
|
|
|
|
mtspr SPRN_SCOMC,r3 /* write command */
|
|
|
|
|
isync
|
|
|
|
|
mfspr 3,SPRN_SCOMC
|
|
|
|
|
isync
|
|
|
|
|
|
|
|
|
|
/* restore interrupts */
|
|
|
|
|
mtmsrd r5,1
|
|
|
|
|
blr
|
2006-06-27 19:55:49 -06:00
|
|
|
#endif /* CONFIG_CPU_FREQ_PMAC64 */
|
2005-11-06 20:27:33 -07:00
|
|
|
|
|
|
|
|
|
2005-10-10 06:36:14 -06:00
|
|
|
/*
|
|
|
|
|
* Create a kernel thread
|
|
|
|
|
* kernel_thread(fn, arg, flags)
|
|
|
|
|
*/
|
|
|
|
|
_GLOBAL(kernel_thread)
|
|
|
|
|
std r29,-24(r1)
|
|
|
|
|
std r30,-16(r1)
|
|
|
|
|
stdu r1,-STACK_FRAME_OVERHEAD(r1)
|
|
|
|
|
mr r29,r3
|
|
|
|
|
mr r30,r4
|
|
|
|
|
ori r3,r5,CLONE_VM /* flags */
|
|
|
|
|
oris r3,r3,(CLONE_UNTRACED>>16)
|
|
|
|
|
li r4,0 /* new sp (unused) */
|
|
|
|
|
li r0,__NR_clone
|
|
|
|
|
sc
|
|
|
|
|
cmpdi 0,r3,0 /* parent or child? */
|
|
|
|
|
bne 1f /* return if parent */
|
|
|
|
|
li r0,0
|
|
|
|
|
stdu r0,-STACK_FRAME_OVERHEAD(r1)
|
|
|
|
|
ld r2,8(r29)
|
|
|
|
|
ld r29,0(r29)
|
|
|
|
|
mtlr r29 /* fn addr in lr */
|
|
|
|
|
mr r3,r30 /* load arg and call fn */
|
|
|
|
|
blrl
|
|
|
|
|
li r0,__NR_exit /* exit after child exits */
|
|
|
|
|
li r3,0
|
|
|
|
|
sc
|
|
|
|
|
1: addi r1,r1,STACK_FRAME_OVERHEAD
|
|
|
|
|
ld r29,-24(r1)
|
|
|
|
|
ld r30,-16(r1)
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* disable_kernel_fp()
|
|
|
|
|
* Disable the FPU.
|
|
|
|
|
*/
|
|
|
|
|
_GLOBAL(disable_kernel_fp)
|
|
|
|
|
mfmsr r3
|
|
|
|
|
rldicl r0,r3,(63-MSR_FP_LG),1
|
|
|
|
|
rldicl r3,r0,(MSR_FP_LG+1),0
|
|
|
|
|
mtmsrd r3 /* disable use of fpu now */
|
|
|
|
|
isync
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
|
|
|
|
|
|
|
|
#if 0 /* this has no callers for now */
|
|
|
|
|
/*
|
|
|
|
|
* disable_kernel_altivec()
|
|
|
|
|
* Disable the VMX.
|
|
|
|
|
*/
|
|
|
|
|
_GLOBAL(disable_kernel_altivec)
|
|
|
|
|
mfmsr r3
|
|
|
|
|
rldicl r0,r3,(63-MSR_VEC_LG),1
|
|
|
|
|
rldicl r3,r0,(MSR_VEC_LG+1),0
|
|
|
|
|
mtmsrd r3 /* disable use of VMX now */
|
|
|
|
|
isync
|
|
|
|
|
blr
|
|
|
|
|
#endif /* 0 */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* giveup_altivec(tsk)
|
|
|
|
|
* Disable VMX for the task given as the argument,
|
|
|
|
|
* and save the vector registers in its thread_struct.
|
|
|
|
|
* Enables the VMX for use in the kernel on return.
|
|
|
|
|
*/
|
|
|
|
|
_GLOBAL(giveup_altivec)
|
|
|
|
|
mfmsr r5
|
|
|
|
|
oris r5,r5,MSR_VEC@h
|
|
|
|
|
mtmsrd r5 /* enable use of VMX now */
|
|
|
|
|
isync
|
|
|
|
|
cmpdi 0,r3,0
|
|
|
|
|
beqlr- /* if no previous owner, done */
|
|
|
|
|
addi r3,r3,THREAD /* want THREAD of task */
|
|
|
|
|
ld r5,PT_REGS(r3)
|
|
|
|
|
cmpdi 0,r5,0
|
|
|
|
|
SAVE_32VRS(0,r4,r3)
|
|
|
|
|
mfvscr vr0
|
|
|
|
|
li r4,THREAD_VSCR
|
|
|
|
|
stvx vr0,r4,r3
|
|
|
|
|
beq 1f
|
|
|
|
|
ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
|
|
|
|
|
lis r3,MSR_VEC@h
|
|
|
|
|
andc r4,r4,r3 /* disable FP for previous task */
|
|
|
|
|
std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
|
|
|
|
|
1:
|
|
|
|
|
#ifndef CONFIG_SMP
|
|
|
|
|
li r5,0
|
|
|
|
|
ld r4,last_task_used_altivec@got(r2)
|
|
|
|
|
std r5,0(r4)
|
|
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
#endif /* CONFIG_ALTIVEC */
|
|
|
|
|
|
2006-10-02 03:18:31 -06:00
|
|
|
_GLOBAL(kernel_execve)
|
2005-10-10 06:36:14 -06:00
|
|
|
li r0,__NR_execve
|
|
|
|
|
sc
|
|
|
|
|
bnslr
|
|
|
|
|
neg r3,r3
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
/* kexec_wait(phys_cpu)
|
|
|
|
|
*
|
|
|
|
|
* wait for the flag to change, indicating this kernel is going away but
|
|
|
|
|
* the slave code for the next one is at addresses 0 to 100.
|
|
|
|
|
*
|
|
|
|
|
* This is used by all slaves.
|
|
|
|
|
*
|
|
|
|
|
* Physical (hardware) cpu id should be in r3.
|
|
|
|
|
*/
|
|
|
|
|
_GLOBAL(kexec_wait)
|
|
|
|
|
bl 1f
|
|
|
|
|
1: mflr r5
|
|
|
|
|
addi r5,r5,kexec_flag-1b
|
|
|
|
|
|
|
|
|
|
99: HMT_LOW
|
|
|
|
|
#ifdef CONFIG_KEXEC /* use no memory without kexec */
|
|
|
|
|
lwz r4,0(r5)
|
|
|
|
|
cmpwi 0,r4,0
|
|
|
|
|
bnea 0x60
|
|
|
|
|
#endif
|
|
|
|
|
b 99b
|
|
|
|
|
|
|
|
|
|
/* this can be in text because we won't change it until we are
|
|
|
|
|
* running in real anyways
|
|
|
|
|
*/
|
|
|
|
|
kexec_flag:
|
|
|
|
|
.long 0
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_KEXEC
|
|
|
|
|
|
|
|
|
|
/* kexec_smp_wait(void)
|
|
|
|
|
*
|
|
|
|
|
* call with interrupts off
|
|
|
|
|
* note: this is a terminal routine, it does not save lr
|
|
|
|
|
*
|
|
|
|
|
* get phys id from paca
|
|
|
|
|
* set paca id to -1 to say we got here
|
|
|
|
|
* switch to real mode
|
|
|
|
|
* join other cpus in kexec_wait(phys_id)
|
|
|
|
|
*/
|
|
|
|
|
_GLOBAL(kexec_smp_wait)
|
|
|
|
|
lhz r3,PACAHWCPUID(r13)
|
|
|
|
|
li r4,-1
|
|
|
|
|
sth r4,PACAHWCPUID(r13) /* let others know we left */
|
|
|
|
|
bl real_mode
|
|
|
|
|
b .kexec_wait
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* switch to real mode (turn mmu off)
|
|
|
|
|
* we use the early kernel trick that the hardware ignores bits
|
|
|
|
|
* 0 and 1 (big endian) of the effective address in real mode
|
|
|
|
|
*
|
|
|
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* don't overwrite r3 here, it is live for kexec_wait above.
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*/
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real_mode: /* assume normal blr return */
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1: li r9,MSR_RI
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li r10,MSR_DR|MSR_IR
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mflr r11 /* return address to SRR0 */
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mfmsr r12
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andc r9,r12,r9
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andc r10,r12,r10
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mtmsrd r9,1
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mtspr SPRN_SRR1,r10
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mtspr SPRN_SRR0,r11
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rfid
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/*
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* kexec_sequence(newstack, start, image, control, clear_all())
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*
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* does the grungy work with stack switching and real mode switches
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* also does simple calls to other code
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*/
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_GLOBAL(kexec_sequence)
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mflr r0
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std r0,16(r1)
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/* switch stacks to newstack -- &kexec_stack.stack */
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stdu r1,THREAD_SIZE-112(r3)
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mr r1,r3
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li r0,0
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std r0,16(r1)
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/* save regs for local vars on new stack.
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* yes, we won't go back, but ...
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*/
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std r31,-8(r1)
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std r30,-16(r1)
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std r29,-24(r1)
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std r28,-32(r1)
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std r27,-40(r1)
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std r26,-48(r1)
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std r25,-56(r1)
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stdu r1,-112-64(r1)
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/* save args into preserved regs */
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mr r31,r3 /* newstack (both) */
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mr r30,r4 /* start (real) */
|
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mr r29,r5 /* image (virt) */
|
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mr r28,r6 /* control, unused */
|
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|
|
mr r27,r7 /* clear_all() fn desc */
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|
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mr r26,r8 /* spare */
|
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|
|
lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */
|
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|
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|
|
/* disable interrupts, we are overwriting kernel data next */
|
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|
|
|
mfmsr r3
|
|
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|
|
rlwinm r3,r3,0,17,15
|
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|
|
mtmsrd r3,1
|
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|
|
|
|
|
|
|
|
/* copy dest pages, flush whole dest image */
|
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|
|
|
mr r3,r29
|
|
|
|
|
bl .kexec_copy_flush /* (image) */
|
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|
|
|
|
|
|
|
|
/* turn off mmu */
|
|
|
|
|
bl real_mode
|
|
|
|
|
|
2007-04-11 02:32:17 -06:00
|
|
|
/* copy 0x100 bytes starting at start to 0 */
|
|
|
|
|
li r3,0
|
|
|
|
|
mr r4,r30 /* start, aka phys mem offset */
|
|
|
|
|
li r5,0x100
|
|
|
|
|
li r6,0
|
|
|
|
|
bl .copy_and_flush /* (dest, src, copy limit, start offset) */
|
|
|
|
|
1: /* assume normal blr return */
|
|
|
|
|
|
|
|
|
|
/* release other cpus to the new kernel secondary start at 0x60 */
|
|
|
|
|
mflr r5
|
|
|
|
|
li r6,1
|
|
|
|
|
stw r6,kexec_flag-1b(5)
|
|
|
|
|
|
2005-10-10 06:36:14 -06:00
|
|
|
/* clear out hardware hash page table and tlb */
|
|
|
|
|
ld r5,0(r27) /* deref function descriptor */
|
|
|
|
|
mtctr r5
|
2006-07-25 15:05:01 -06:00
|
|
|
bctrl /* ppc_md.hpte_clear_all(void); */
|
2005-10-10 06:36:14 -06:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* kexec image calling is:
|
|
|
|
|
* the first 0x100 bytes of the entry point are copied to 0
|
|
|
|
|
*
|
|
|
|
|
* all slaves branch to slave = 0x60 (absolute)
|
|
|
|
|
* slave(phys_cpu_id);
|
|
|
|
|
*
|
|
|
|
|
* master goes to start = entry point
|
|
|
|
|
* start(phys_cpu_id, start, 0);
|
|
|
|
|
*
|
|
|
|
|
*
|
|
|
|
|
* a wrapper is needed to call existing kernels, here is an approximate
|
|
|
|
|
* description of one method:
|
|
|
|
|
*
|
|
|
|
|
* v2: (2.6.10)
|
|
|
|
|
* start will be near the boot_block (maybe 0x100 bytes before it?)
|
|
|
|
|
* it will have a 0x60, which will b to boot_block, where it will wait
|
|
|
|
|
* and 0 will store phys into struct boot-block and load r3 from there,
|
|
|
|
|
* copy kernel 0-0x100 and tell slaves to back down to 0x60 again
|
|
|
|
|
*
|
|
|
|
|
* v1: (2.6.9)
|
|
|
|
|
* boot block will have all cpus scanning device tree to see if they
|
|
|
|
|
* are the boot cpu ?????
|
|
|
|
|
* other device tree differences (prop sizes, va vs pa, etc)...
|
|
|
|
|
*/
|
|
|
|
|
mr r3,r25 # my phys cpu
|
|
|
|
|
mr r4,r30 # start, aka phys mem offset
|
|
|
|
|
mtlr 4
|
|
|
|
|
li r5,0
|
|
|
|
|
blr /* image->start(physid, image->start, 0); */
|
|
|
|
|
#endif /* CONFIG_KEXEC */
|