2012-08-02 02:16:29 -06:00
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/*
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* Coherency fabric (Aurora) support for Armada 370 and XP platforms.
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*
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* Copyright (C) 2012 Marvell
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*
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* Yehuda Yitschak <yehuday@marvell.com>
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* Gregory Clement <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* The Armada 370 and Armada XP SOCs have a coherency fabric which is
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* responsible for ensuring hardware coherency between all CPUs and between
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* CPUs and I/O masters. This file initializes the coherency fabric and
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* supplies basic routines for configuring and controlling hardware coherency
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*/
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2014-04-14 07:47:05 -06:00
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#define pr_fmt(fmt) "mvebu-coherency: " fmt
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2012-08-02 02:16:29 -06:00
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <linux/smp.h>
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2012-10-12 11:20:36 -06:00
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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2014-04-14 07:47:05 -06:00
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#include <linux/slab.h>
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#include <linux/mbus.h>
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#include <linux/clk.h>
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2014-05-13 10:04:30 -06:00
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#include <linux/pci.h>
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2012-08-02 02:16:29 -06:00
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#include <asm/smp_plat.h>
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2013-06-06 04:24:28 -06:00
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#include <asm/cacheflush.h>
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2014-05-15 08:59:34 -06:00
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#include <asm/mach/map.h>
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2012-08-02 02:16:29 -06:00
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#include "armada-370-xp.h"
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2013-11-07 02:02:38 -07:00
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#include "coherency.h"
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2014-05-05 09:05:26 -06:00
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#include "mvebu-soc-id.h"
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2012-08-02 02:16:29 -06:00
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2013-06-17 13:43:14 -06:00
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unsigned long coherency_phys_base;
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2014-04-14 09:10:05 -06:00
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void __iomem *coherency_base;
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2012-10-12 11:20:36 -06:00
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static void __iomem *coherency_cpu_base;
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2012-08-02 02:16:29 -06:00
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/* Coherency fabric registers */
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#define COHERENCY_FABRIC_CFG_OFFSET 0x4
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2012-10-12 11:20:36 -06:00
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#define IO_SYNC_BARRIER_CTL_OFFSET 0x0
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2014-04-14 07:46:59 -06:00
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enum {
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2014-04-14 07:47:00 -06:00
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COHERENCY_FABRIC_TYPE_NONE,
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2014-04-14 07:46:59 -06:00
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COHERENCY_FABRIC_TYPE_ARMADA_370_XP,
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ARM: mvebu: add Armada 375 support to the coherency code
The Armada 375, like the Armada 370 and Armada XP, has a coherency
unit. However, unlike the coherency unit of 370/XP which does both CPU
and I/O coherency, the one on Armada 735 only does I/O
coherency. Therefore, instead of having two sets of registers (the
first one being used mainly to register each CPU in the coherency
fabric, the second one being used for the I/O coherency barrier), it
has only one set of register (for the I/O coherency barrier).
This commit adds a new "marvell,armada-375-coherency-fabric"
compatible string for this variant of the coherency fabric. The custom
DMA operations, and the way of triggering an I/O barrier is the same
as Armada 370/XP, so the code changes are minimal. However, the
set_cpu_coherent() function is not needed on Armada 375 and will not
work.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-7-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-14 07:47:04 -06:00
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COHERENCY_FABRIC_TYPE_ARMADA_375,
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2014-04-14 07:47:06 -06:00
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COHERENCY_FABRIC_TYPE_ARMADA_380,
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2014-04-14 07:46:59 -06:00
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};
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2012-08-02 02:16:29 -06:00
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static struct of_device_id of_coherency_table[] = {
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2014-04-14 07:46:59 -06:00
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{.compatible = "marvell,coherency-fabric",
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.data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP },
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ARM: mvebu: add Armada 375 support to the coherency code
The Armada 375, like the Armada 370 and Armada XP, has a coherency
unit. However, unlike the coherency unit of 370/XP which does both CPU
and I/O coherency, the one on Armada 735 only does I/O
coherency. Therefore, instead of having two sets of registers (the
first one being used mainly to register each CPU in the coherency
fabric, the second one being used for the I/O coherency barrier), it
has only one set of register (for the I/O coherency barrier).
This commit adds a new "marvell,armada-375-coherency-fabric"
compatible string for this variant of the coherency fabric. The custom
DMA operations, and the way of triggering an I/O barrier is the same
as Armada 370/XP, so the code changes are minimal. However, the
set_cpu_coherent() function is not needed on Armada 375 and will not
work.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-7-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-14 07:47:04 -06:00
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{.compatible = "marvell,armada-375-coherency-fabric",
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.data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 },
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2014-04-14 07:47:06 -06:00
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{.compatible = "marvell,armada-380-coherency-fabric",
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.data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_380 },
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2012-08-02 02:16:29 -06:00
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{ /* end of list */ },
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};
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2014-04-14 09:10:08 -06:00
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/* Functions defined in coherency_ll.S */
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int ll_enable_coherency(void);
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void ll_add_cpu_to_smp_group(void);
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2012-08-02 02:16:29 -06:00
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2014-04-14 09:10:07 -06:00
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int set_cpu_coherent(void)
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2012-08-02 02:16:29 -06:00
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{
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if (!coherency_base) {
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2014-04-14 09:10:06 -06:00
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pr_warn("Can't make current CPU cache coherent.\n");
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2012-08-02 02:16:29 -06:00
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pr_warn("Coherency fabric is not initialized\n");
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return 1;
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}
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2014-04-14 09:10:08 -06:00
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ll_add_cpu_to_smp_group();
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return ll_enable_coherency();
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2012-08-02 02:16:29 -06:00
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}
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2014-04-14 07:47:05 -06:00
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/*
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* The below code implements the I/O coherency workaround on Armada
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* 375. This workaround consists in using the two channels of the
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* first XOR engine to trigger a XOR transaction that serves as the
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* I/O coherency barrier.
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*/
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static void __iomem *xor_base, *xor_high_base;
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static dma_addr_t coherency_wa_buf_phys[CONFIG_NR_CPUS];
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static void *coherency_wa_buf[CONFIG_NR_CPUS];
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static bool coherency_wa_enabled;
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#define XOR_CONFIG(chan) (0x10 + (chan * 4))
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#define XOR_ACTIVATION(chan) (0x20 + (chan * 4))
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#define WINDOW_BAR_ENABLE(chan) (0x240 + ((chan) << 2))
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#define WINDOW_BASE(w) (0x250 + ((w) << 2))
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#define WINDOW_SIZE(w) (0x270 + ((w) << 2))
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#define WINDOW_REMAP_HIGH(w) (0x290 + ((w) << 2))
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#define WINDOW_OVERRIDE_CTRL(chan) (0x2A0 + ((chan) << 2))
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#define XOR_DEST_POINTER(chan) (0x2B0 + (chan * 4))
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#define XOR_BLOCK_SIZE(chan) (0x2C0 + (chan * 4))
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#define XOR_INIT_VALUE_LOW 0x2E0
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#define XOR_INIT_VALUE_HIGH 0x2E4
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static inline void mvebu_hwcc_armada375_sync_io_barrier_wa(void)
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{
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int idx = smp_processor_id();
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/* Write '1' to the first word of the buffer */
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writel(0x1, coherency_wa_buf[idx]);
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/* Wait until the engine is idle */
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while ((readl(xor_base + XOR_ACTIVATION(idx)) >> 4) & 0x3)
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;
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dmb();
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/* Trigger channel */
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writel(0x1, xor_base + XOR_ACTIVATION(idx));
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/* Poll the data until it is cleared by the XOR transaction */
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while (readl(coherency_wa_buf[idx]))
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;
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}
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static void __init armada_375_coherency_init_wa(void)
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{
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const struct mbus_dram_target_info *dram;
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struct device_node *xor_node;
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struct property *xor_status;
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struct clk *xor_clk;
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u32 win_enable = 0;
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int i;
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pr_warn("enabling coherency workaround for Armada 375 Z1, one XOR engine disabled\n");
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/*
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* Since the workaround uses one XOR engine, we grab a
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* reference to its Device Tree node first.
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*/
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xor_node = of_find_compatible_node(NULL, NULL, "marvell,orion-xor");
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BUG_ON(!xor_node);
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/*
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* Then we mark it as disabled so that the real XOR driver
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* will not use it.
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*/
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xor_status = kzalloc(sizeof(struct property), GFP_KERNEL);
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BUG_ON(!xor_status);
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xor_status->value = kstrdup("disabled", GFP_KERNEL);
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BUG_ON(!xor_status->value);
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xor_status->length = 8;
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xor_status->name = kstrdup("status", GFP_KERNEL);
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BUG_ON(!xor_status->name);
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of_update_property(xor_node, xor_status);
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/*
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* And we remap the registers, get the clock, and do the
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* initial configuration of the XOR engine.
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*/
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xor_base = of_iomap(xor_node, 0);
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xor_high_base = of_iomap(xor_node, 1);
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xor_clk = of_clk_get_by_name(xor_node, NULL);
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BUG_ON(!xor_clk);
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clk_prepare_enable(xor_clk);
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dram = mv_mbus_dram_info();
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for (i = 0; i < 8; i++) {
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writel(0, xor_base + WINDOW_BASE(i));
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writel(0, xor_base + WINDOW_SIZE(i));
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if (i < 4)
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writel(0, xor_base + WINDOW_REMAP_HIGH(i));
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}
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for (i = 0; i < dram->num_cs; i++) {
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const struct mbus_dram_window *cs = dram->cs + i;
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writel((cs->base & 0xffff0000) |
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(cs->mbus_attr << 8) |
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dram->mbus_dram_target_id, xor_base + WINDOW_BASE(i));
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writel((cs->size - 1) & 0xffff0000, xor_base + WINDOW_SIZE(i));
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win_enable |= (1 << i);
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win_enable |= 3 << (16 + (2 * i));
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}
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writel(win_enable, xor_base + WINDOW_BAR_ENABLE(0));
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writel(win_enable, xor_base + WINDOW_BAR_ENABLE(1));
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writel(0, xor_base + WINDOW_OVERRIDE_CTRL(0));
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writel(0, xor_base + WINDOW_OVERRIDE_CTRL(1));
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for (i = 0; i < CONFIG_NR_CPUS; i++) {
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coherency_wa_buf[i] = kzalloc(PAGE_SIZE, GFP_KERNEL);
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BUG_ON(!coherency_wa_buf[i]);
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/*
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* We can't use the DMA mapping API, since we don't
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* have a valid 'struct device' pointer
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*/
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coherency_wa_buf_phys[i] =
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virt_to_phys(coherency_wa_buf[i]);
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BUG_ON(!coherency_wa_buf_phys[i]);
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/*
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* Configure the XOR engine for memset operation, with
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* a 128 bytes block size
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*/
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writel(0x444, xor_base + XOR_CONFIG(i));
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writel(128, xor_base + XOR_BLOCK_SIZE(i));
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writel(coherency_wa_buf_phys[i],
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xor_base + XOR_DEST_POINTER(i));
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}
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writel(0x0, xor_base + XOR_INIT_VALUE_LOW);
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writel(0x0, xor_base + XOR_INIT_VALUE_HIGH);
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coherency_wa_enabled = true;
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}
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2012-10-12 11:20:36 -06:00
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static inline void mvebu_hwcc_sync_io_barrier(void)
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{
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2014-04-14 07:47:05 -06:00
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if (coherency_wa_enabled) {
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mvebu_hwcc_armada375_sync_io_barrier_wa();
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return;
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}
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2012-10-12 11:20:36 -06:00
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writel(0x1, coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET);
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while (readl(coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET) & 0x1);
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}
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static dma_addr_t mvebu_hwcc_dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir,
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struct dma_attrs *attrs)
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{
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if (dir != DMA_TO_DEVICE)
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mvebu_hwcc_sync_io_barrier();
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return pfn_to_dma(dev, page_to_pfn(page)) + offset;
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}
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static void mvebu_hwcc_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction dir,
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struct dma_attrs *attrs)
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{
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if (dir != DMA_TO_DEVICE)
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mvebu_hwcc_sync_io_barrier();
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}
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static void mvebu_hwcc_dma_sync(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction dir)
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{
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if (dir != DMA_TO_DEVICE)
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mvebu_hwcc_sync_io_barrier();
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}
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static struct dma_map_ops mvebu_hwcc_dma_ops = {
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.alloc = arm_dma_alloc,
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.free = arm_dma_free,
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.mmap = arm_dma_mmap,
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.map_page = mvebu_hwcc_dma_map_page,
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.unmap_page = mvebu_hwcc_dma_unmap_page,
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.get_sgtable = arm_dma_get_sgtable,
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.map_sg = arm_dma_map_sg,
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.unmap_sg = arm_dma_unmap_sg,
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.sync_single_for_cpu = mvebu_hwcc_dma_sync,
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.sync_single_for_device = mvebu_hwcc_dma_sync,
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.sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
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.sync_sg_for_device = arm_dma_sync_sg_for_device,
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.set_dma_mask = arm_dma_set_mask,
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};
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2014-05-13 10:04:30 -06:00
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static int mvebu_hwcc_notifier(struct notifier_block *nb,
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unsigned long event, void *__dev)
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2012-10-12 11:20:36 -06:00
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{
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struct device *dev = __dev;
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if (event != BUS_NOTIFY_ADD_DEVICE)
|
|
|
|
return NOTIFY_DONE;
|
|
|
|
set_dma_ops(dev, &mvebu_hwcc_dma_ops);
|
|
|
|
|
|
|
|
return NOTIFY_OK;
|
|
|
|
}
|
|
|
|
|
2014-05-13 10:04:30 -06:00
|
|
|
static struct notifier_block mvebu_hwcc_nb = {
|
|
|
|
.notifier_call = mvebu_hwcc_notifier,
|
2012-10-12 11:20:36 -06:00
|
|
|
};
|
|
|
|
|
2014-07-08 07:37:37 -06:00
|
|
|
static struct notifier_block mvebu_hwcc_pci_nb = {
|
|
|
|
.notifier_call = mvebu_hwcc_notifier,
|
|
|
|
};
|
|
|
|
|
2014-04-14 07:46:59 -06:00
|
|
|
static void __init armada_370_coherency_init(struct device_node *np)
|
|
|
|
{
|
|
|
|
struct resource res;
|
|
|
|
|
|
|
|
of_address_to_resource(np, 0, &res);
|
|
|
|
coherency_phys_base = res.start;
|
|
|
|
/*
|
|
|
|
* Ensure secondary CPUs will see the updated value,
|
|
|
|
* which they read before they join the coherency
|
|
|
|
* fabric, and therefore before they are coherent with
|
|
|
|
* the boot CPU cache.
|
|
|
|
*/
|
|
|
|
sync_cache_w(&coherency_phys_base);
|
|
|
|
coherency_base = of_iomap(np, 0);
|
|
|
|
coherency_cpu_base = of_iomap(np, 1);
|
2014-04-14 09:10:07 -06:00
|
|
|
set_cpu_coherent();
|
2014-04-14 07:46:59 -06:00
|
|
|
}
|
|
|
|
|
2014-05-15 08:59:34 -06:00
|
|
|
/*
|
|
|
|
* This ioremap hook is used on Armada 375/38x to ensure that PCIe
|
|
|
|
* memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This
|
|
|
|
* is needed as a workaround for a deadlock issue between the PCIe
|
|
|
|
* interface and the cache controller.
|
|
|
|
*/
|
|
|
|
static void __iomem *
|
|
|
|
armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
|
|
|
|
unsigned int mtype, void *caller)
|
|
|
|
{
|
|
|
|
struct resource pcie_mem;
|
|
|
|
|
|
|
|
mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);
|
|
|
|
|
|
|
|
if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)
|
|
|
|
mtype = MT_UNCACHED;
|
|
|
|
|
|
|
|
return __arm_ioremap_caller(phys_addr, size, mtype, caller);
|
|
|
|
}
|
|
|
|
|
2014-04-14 07:47:06 -06:00
|
|
|
static void __init armada_375_380_coherency_init(struct device_node *np)
|
ARM: mvebu: add Armada 375 support to the coherency code
The Armada 375, like the Armada 370 and Armada XP, has a coherency
unit. However, unlike the coherency unit of 370/XP which does both CPU
and I/O coherency, the one on Armada 735 only does I/O
coherency. Therefore, instead of having two sets of registers (the
first one being used mainly to register each CPU in the coherency
fabric, the second one being used for the I/O coherency barrier), it
has only one set of register (for the I/O coherency barrier).
This commit adds a new "marvell,armada-375-coherency-fabric"
compatible string for this variant of the coherency fabric. The custom
DMA operations, and the way of triggering an I/O barrier is the same
as Armada 370/XP, so the code changes are minimal. However, the
set_cpu_coherent() function is not needed on Armada 375 and will not
work.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-7-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-14 07:47:04 -06:00
|
|
|
{
|
2014-05-15 08:59:34 -06:00
|
|
|
struct device_node *cache_dn;
|
|
|
|
|
ARM: mvebu: add Armada 375 support to the coherency code
The Armada 375, like the Armada 370 and Armada XP, has a coherency
unit. However, unlike the coherency unit of 370/XP which does both CPU
and I/O coherency, the one on Armada 735 only does I/O
coherency. Therefore, instead of having two sets of registers (the
first one being used mainly to register each CPU in the coherency
fabric, the second one being used for the I/O coherency barrier), it
has only one set of register (for the I/O coherency barrier).
This commit adds a new "marvell,armada-375-coherency-fabric"
compatible string for this variant of the coherency fabric. The custom
DMA operations, and the way of triggering an I/O barrier is the same
as Armada 370/XP, so the code changes are minimal. However, the
set_cpu_coherent() function is not needed on Armada 375 and will not
work.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-7-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-14 07:47:04 -06:00
|
|
|
coherency_cpu_base = of_iomap(np, 0);
|
2014-05-15 08:59:34 -06:00
|
|
|
arch_ioremap_caller = armada_pcie_wa_ioremap_caller;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Add the PL310 property "arm,io-coherent". This makes sure the
|
|
|
|
* outer sync operation is not used, which allows to
|
|
|
|
* workaround the system erratum that causes deadlocks when
|
|
|
|
* doing PCIe in an SMP situation on Armada 375 and Armada
|
|
|
|
* 38x.
|
|
|
|
*/
|
|
|
|
for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") {
|
|
|
|
struct property *p;
|
|
|
|
|
|
|
|
p = kzalloc(sizeof(*p), GFP_KERNEL);
|
|
|
|
p->name = kstrdup("arm,io-coherent", GFP_KERNEL);
|
|
|
|
of_add_property(cache_dn, p);
|
|
|
|
}
|
ARM: mvebu: add Armada 375 support to the coherency code
The Armada 375, like the Armada 370 and Armada XP, has a coherency
unit. However, unlike the coherency unit of 370/XP which does both CPU
and I/O coherency, the one on Armada 735 only does I/O
coherency. Therefore, instead of having two sets of registers (the
first one being used mainly to register each CPU in the coherency
fabric, the second one being used for the I/O coherency barrier), it
has only one set of register (for the I/O coherency barrier).
This commit adds a new "marvell,armada-375-coherency-fabric"
compatible string for this variant of the coherency fabric. The custom
DMA operations, and the way of triggering an I/O barrier is the same
as Armada 370/XP, so the code changes are minimal. However, the
set_cpu_coherent() function is not needed on Armada 375 and will not
work.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-7-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-14 07:47:04 -06:00
|
|
|
}
|
|
|
|
|
2014-04-14 07:47:00 -06:00
|
|
|
static int coherency_type(void)
|
2012-08-02 02:16:29 -06:00
|
|
|
{
|
|
|
|
struct device_node *np;
|
2014-04-14 07:47:02 -06:00
|
|
|
const struct of_device_id *match;
|
2012-08-02 02:16:29 -06:00
|
|
|
|
2014-04-14 07:47:02 -06:00
|
|
|
np = of_find_matching_node_and_match(NULL, of_coherency_table, &match);
|
2012-08-02 02:16:29 -06:00
|
|
|
if (np) {
|
2014-04-14 07:47:02 -06:00
|
|
|
int type = (int) match->data;
|
2014-04-14 07:46:59 -06:00
|
|
|
|
2014-04-14 07:47:00 -06:00
|
|
|
/* Armada 370/XP coherency works in both UP and SMP */
|
2014-04-14 07:46:59 -06:00
|
|
|
if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
|
2014-04-14 07:47:00 -06:00
|
|
|
return type;
|
2014-04-14 07:46:59 -06:00
|
|
|
|
ARM: mvebu: add Armada 375 support to the coherency code
The Armada 375, like the Armada 370 and Armada XP, has a coherency
unit. However, unlike the coherency unit of 370/XP which does both CPU
and I/O coherency, the one on Armada 735 only does I/O
coherency. Therefore, instead of having two sets of registers (the
first one being used mainly to register each CPU in the coherency
fabric, the second one being used for the I/O coherency barrier), it
has only one set of register (for the I/O coherency barrier).
This commit adds a new "marvell,armada-375-coherency-fabric"
compatible string for this variant of the coherency fabric. The custom
DMA operations, and the way of triggering an I/O barrier is the same
as Armada 370/XP, so the code changes are minimal. However, the
set_cpu_coherent() function is not needed on Armada 375 and will not
work.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-7-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-14 07:47:04 -06:00
|
|
|
/* Armada 375 coherency works only on SMP */
|
|
|
|
else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 && is_smp())
|
|
|
|
return type;
|
|
|
|
|
2014-04-14 07:47:06 -06:00
|
|
|
/* Armada 380 coherency works only on SMP */
|
|
|
|
else if (type == COHERENCY_FABRIC_TYPE_ARMADA_380 && is_smp())
|
|
|
|
return type;
|
2012-08-02 02:16:29 -06:00
|
|
|
}
|
|
|
|
|
2014-04-14 07:47:00 -06:00
|
|
|
return COHERENCY_FABRIC_TYPE_NONE;
|
2012-08-02 02:16:29 -06:00
|
|
|
}
|
2013-06-05 01:04:55 -06:00
|
|
|
|
2014-04-14 07:47:00 -06:00
|
|
|
int coherency_available(void)
|
2013-06-05 01:04:55 -06:00
|
|
|
{
|
2014-04-14 07:47:00 -06:00
|
|
|
return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
|
|
|
|
}
|
|
|
|
|
|
|
|
int __init coherency_init(void)
|
|
|
|
{
|
|
|
|
int type = coherency_type();
|
2013-08-26 22:41:14 -06:00
|
|
|
struct device_node *np;
|
|
|
|
|
|
|
|
np = of_find_matching_node(NULL, of_coherency_table);
|
2014-04-14 07:47:00 -06:00
|
|
|
|
|
|
|
if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
|
|
|
|
armada_370_coherency_init(np);
|
2014-04-14 07:47:06 -06:00
|
|
|
else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 ||
|
|
|
|
type == COHERENCY_FABRIC_TYPE_ARMADA_380)
|
|
|
|
armada_375_380_coherency_init(np);
|
2014-04-14 07:47:00 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __init coherency_late_init(void)
|
|
|
|
{
|
2014-04-14 07:47:05 -06:00
|
|
|
int type = coherency_type();
|
|
|
|
|
|
|
|
if (type == COHERENCY_FABRIC_TYPE_NONE)
|
|
|
|
return 0;
|
|
|
|
|
2014-05-05 09:05:26 -06:00
|
|
|
if (type == COHERENCY_FABRIC_TYPE_ARMADA_375) {
|
|
|
|
u32 dev, rev;
|
|
|
|
|
|
|
|
if (mvebu_get_soc_id(&dev, &rev) == 0 &&
|
|
|
|
rev == ARMADA_375_Z1_REV)
|
|
|
|
armada_375_coherency_init_wa();
|
|
|
|
}
|
2014-04-14 07:47:05 -06:00
|
|
|
|
|
|
|
bus_register_notifier(&platform_bus_type,
|
2014-05-13 10:04:30 -06:00
|
|
|
&mvebu_hwcc_nb);
|
2014-04-14 07:47:05 -06:00
|
|
|
|
2013-06-05 01:04:55 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
postcore_initcall(coherency_late_init);
|
2014-05-13 10:04:30 -06:00
|
|
|
|
2014-05-20 09:13:03 -06:00
|
|
|
#if IS_ENABLED(CONFIG_PCI)
|
2014-05-13 10:04:30 -06:00
|
|
|
static int __init coherency_pci_init(void)
|
|
|
|
{
|
|
|
|
if (coherency_available())
|
|
|
|
bus_register_notifier(&pci_bus_type,
|
2014-07-08 07:37:37 -06:00
|
|
|
&mvebu_hwcc_pci_nb);
|
2014-05-13 10:04:30 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
arch_initcall(coherency_pci_init);
|
2014-05-20 09:13:03 -06:00
|
|
|
#endif
|