2019-03-26 09:17:51 -06:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* This driver adds support for perf events to use the Performance
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* Monitor Counter Groups (PMCG) associated with an SMMUv3 node
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* to monitor that node.
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*
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* SMMUv3 PMCG devices are named as smmuv3_pmcg_<phys_addr_page> where
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* <phys_addr_page> is the physical page address of the SMMU PMCG wrapped
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* to 4K boundary. For example, the PMCG at 0xff88840000 is named
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* smmuv3_pmcg_ff88840
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*
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* Filtering by stream id is done by specifying filtering parameters
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* with the event. options are:
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* filter_enable - 0 = no filtering, 1 = filtering enabled
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* filter_span - 0 = exact match, 1 = pattern match
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* filter_stream_id - pattern to filter against
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*
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* To match a partial StreamID where the X most-significant bits must match
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* but the Y least-significant bits might differ, STREAMID is programmed
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* with a value that contains:
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* STREAMID[Y - 1] == 0.
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* STREAMID[Y - 2:0] == 1 (where Y > 1).
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* The remainder of implemented bits of STREAMID (X bits, from bit Y upwards)
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* contain a value to match from the corresponding bits of event StreamID.
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*
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* Example: perf stat -e smmuv3_pmcg_ff88840/transaction,filter_enable=1,
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* filter_span=1,filter_stream_id=0x42/ -a netperf
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* Applies filter pattern 0x42 to transaction events, which means events
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* matching stream ids 0x42 and 0x43 are counted. Further filtering
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* information is available in the SMMU documentation.
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*
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* SMMU events are not attributable to a CPU, so task mode and sampling
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* are not supported.
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*/
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#include <linux/acpi.h>
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2019-03-26 09:17:53 -06:00
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#include <linux/acpi_iort.h>
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2019-03-26 09:17:51 -06:00
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/cpuhotplug.h>
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#include <linux/cpumask.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/msi.h>
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#include <linux/perf_event.h>
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#include <linux/platform_device.h>
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#include <linux/smp.h>
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#include <linux/sysfs.h>
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#include <linux/types.h>
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#define SMMU_PMCG_EVCNTR0 0x0
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#define SMMU_PMCG_EVCNTR(n, stride) (SMMU_PMCG_EVCNTR0 + (n) * (stride))
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#define SMMU_PMCG_EVTYPER0 0x400
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#define SMMU_PMCG_EVTYPER(n) (SMMU_PMCG_EVTYPER0 + (n) * 4)
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#define SMMU_PMCG_SID_SPAN_SHIFT 29
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#define SMMU_PMCG_SMR0 0xA00
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#define SMMU_PMCG_SMR(n) (SMMU_PMCG_SMR0 + (n) * 4)
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#define SMMU_PMCG_CNTENSET0 0xC00
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#define SMMU_PMCG_CNTENCLR0 0xC20
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#define SMMU_PMCG_INTENSET0 0xC40
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#define SMMU_PMCG_INTENCLR0 0xC60
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#define SMMU_PMCG_OVSCLR0 0xC80
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#define SMMU_PMCG_OVSSET0 0xCC0
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#define SMMU_PMCG_CFGR 0xE00
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#define SMMU_PMCG_CFGR_SID_FILTER_TYPE BIT(23)
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#define SMMU_PMCG_CFGR_MSI BIT(21)
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#define SMMU_PMCG_CFGR_RELOC_CTRS BIT(20)
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#define SMMU_PMCG_CFGR_SIZE GENMASK(13, 8)
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#define SMMU_PMCG_CFGR_NCTR GENMASK(5, 0)
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#define SMMU_PMCG_CR 0xE04
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#define SMMU_PMCG_CR_ENABLE BIT(0)
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#define SMMU_PMCG_CEID0 0xE20
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#define SMMU_PMCG_CEID1 0xE28
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#define SMMU_PMCG_IRQ_CTRL 0xE50
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#define SMMU_PMCG_IRQ_CTRL_IRQEN BIT(0)
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#define SMMU_PMCG_IRQ_CFG0 0xE58
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#define SMMU_PMCG_IRQ_CFG1 0xE60
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#define SMMU_PMCG_IRQ_CFG2 0xE64
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/* MSI config fields */
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#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2)
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#define MSI_CFG2_MEMATTR_DEVICE_nGnRE 0x1
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#define SMMU_PMCG_DEFAULT_FILTER_SPAN 1
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#define SMMU_PMCG_DEFAULT_FILTER_SID GENMASK(31, 0)
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#define SMMU_PMCG_MAX_COUNTERS 64
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#define SMMU_PMCG_ARCH_MAX_EVENTS 128
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#define SMMU_PMCG_PA_SHIFT 12
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2019-03-26 09:17:53 -06:00
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#define SMMU_PMCG_EVCNTR_RDONLY BIT(0)
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2019-03-26 09:17:51 -06:00
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static int cpuhp_state_num;
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struct smmu_pmu {
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struct hlist_node node;
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struct perf_event *events[SMMU_PMCG_MAX_COUNTERS];
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DECLARE_BITMAP(used_counters, SMMU_PMCG_MAX_COUNTERS);
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DECLARE_BITMAP(supported_events, SMMU_PMCG_ARCH_MAX_EVENTS);
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unsigned int irq;
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unsigned int on_cpu;
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struct pmu pmu;
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unsigned int num_counters;
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struct device *dev;
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void __iomem *reg_base;
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void __iomem *reloc_base;
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u64 counter_mask;
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u32 options;
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2019-03-26 09:17:51 -06:00
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bool global_filter;
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};
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#define to_smmu_pmu(p) (container_of(p, struct smmu_pmu, pmu))
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#define SMMU_PMU_EVENT_ATTR_EXTRACTOR(_name, _config, _start, _end) \
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static inline u32 get_##_name(struct perf_event *event) \
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{ \
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return FIELD_GET(GENMASK_ULL(_end, _start), \
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event->attr._config); \
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} \
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SMMU_PMU_EVENT_ATTR_EXTRACTOR(event, config, 0, 15);
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SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_stream_id, config1, 0, 31);
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SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_span, config1, 32, 32);
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SMMU_PMU_EVENT_ATTR_EXTRACTOR(filter_enable, config1, 33, 33);
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static inline void smmu_pmu_enable(struct pmu *pmu)
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{
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struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
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writel(SMMU_PMCG_IRQ_CTRL_IRQEN,
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smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
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writel(SMMU_PMCG_CR_ENABLE, smmu_pmu->reg_base + SMMU_PMCG_CR);
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}
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static inline void smmu_pmu_disable(struct pmu *pmu)
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{
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struct smmu_pmu *smmu_pmu = to_smmu_pmu(pmu);
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writel(0, smmu_pmu->reg_base + SMMU_PMCG_CR);
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writel(0, smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
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}
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static inline void smmu_pmu_counter_set_value(struct smmu_pmu *smmu_pmu,
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u32 idx, u64 value)
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{
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if (smmu_pmu->counter_mask & BIT(32))
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writeq(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 8));
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else
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writel(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 4));
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}
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static inline u64 smmu_pmu_counter_get_value(struct smmu_pmu *smmu_pmu, u32 idx)
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{
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u64 value;
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if (smmu_pmu->counter_mask & BIT(32))
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value = readq(smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 8));
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else
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value = readl(smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 4));
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return value;
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}
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static inline void smmu_pmu_counter_enable(struct smmu_pmu *smmu_pmu, u32 idx)
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{
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writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENSET0);
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}
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static inline void smmu_pmu_counter_disable(struct smmu_pmu *smmu_pmu, u32 idx)
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{
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writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);
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}
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static inline void smmu_pmu_interrupt_enable(struct smmu_pmu *smmu_pmu, u32 idx)
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{
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writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENSET0);
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}
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static inline void smmu_pmu_interrupt_disable(struct smmu_pmu *smmu_pmu,
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u32 idx)
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{
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writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0);
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}
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static inline void smmu_pmu_set_evtyper(struct smmu_pmu *smmu_pmu, u32 idx,
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u32 val)
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{
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writel(val, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx));
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}
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static inline void smmu_pmu_set_smr(struct smmu_pmu *smmu_pmu, u32 idx, u32 val)
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{
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writel(val, smmu_pmu->reg_base + SMMU_PMCG_SMR(idx));
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}
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static void smmu_pmu_event_update(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
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u64 delta, prev, now;
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u32 idx = hwc->idx;
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do {
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prev = local64_read(&hwc->prev_count);
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now = smmu_pmu_counter_get_value(smmu_pmu, idx);
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} while (local64_cmpxchg(&hwc->prev_count, prev, now) != prev);
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/* handle overflow. */
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delta = now - prev;
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delta &= smmu_pmu->counter_mask;
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local64_add(delta, &event->count);
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}
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static void smmu_pmu_set_period(struct smmu_pmu *smmu_pmu,
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struct hw_perf_event *hwc)
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{
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u32 idx = hwc->idx;
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u64 new;
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2019-03-26 09:17:53 -06:00
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if (smmu_pmu->options & SMMU_PMCG_EVCNTR_RDONLY) {
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/*
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* On platforms that require this quirk, if the counter starts
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* at < half_counter value and wraps, the current logic of
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* handling the overflow may not work. It is expected that,
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* those platforms will have full 64 counter bits implemented
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* so that such a possibility is remote(eg: HiSilicon HIP08).
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*/
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new = smmu_pmu_counter_get_value(smmu_pmu, idx);
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} else {
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/*
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* We limit the max period to half the max counter value
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* of the counter size, so that even in the case of extreme
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* interrupt latency the counter will (hopefully) not wrap
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* past its initial value.
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*/
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new = smmu_pmu->counter_mask >> 1;
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smmu_pmu_counter_set_value(smmu_pmu, idx, new);
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}
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2019-03-26 09:17:51 -06:00
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local64_set(&hwc->prev_count, new);
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}
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static void smmu_pmu_set_event_filter(struct perf_event *event,
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int idx, u32 span, u32 sid)
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{
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struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
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u32 evtyper;
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evtyper = get_event(event) | span << SMMU_PMCG_SID_SPAN_SHIFT;
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smmu_pmu_set_evtyper(smmu_pmu, idx, evtyper);
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smmu_pmu_set_smr(smmu_pmu, idx, sid);
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}
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2019-08-01 09:22:45 -06:00
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static bool smmu_pmu_check_global_filter(struct perf_event *curr,
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struct perf_event *new)
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{
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if (get_filter_enable(new) != get_filter_enable(curr))
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return false;
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if (!get_filter_enable(new))
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return true;
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return get_filter_span(new) == get_filter_span(curr) &&
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get_filter_stream_id(new) == get_filter_stream_id(curr);
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}
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2019-03-26 09:17:51 -06:00
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static int smmu_pmu_apply_event_filter(struct smmu_pmu *smmu_pmu,
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struct perf_event *event, int idx)
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{
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u32 span, sid;
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unsigned int num_ctrs = smmu_pmu->num_counters;
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bool filter_en = !!get_filter_enable(event);
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span = filter_en ? get_filter_span(event) :
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SMMU_PMCG_DEFAULT_FILTER_SPAN;
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sid = filter_en ? get_filter_stream_id(event) :
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SMMU_PMCG_DEFAULT_FILTER_SID;
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/* Support individual filter settings */
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if (!smmu_pmu->global_filter) {
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smmu_pmu_set_event_filter(event, idx, span, sid);
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return 0;
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}
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/* Requested settings same as current global settings*/
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idx = find_first_bit(smmu_pmu->used_counters, num_ctrs);
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if (idx == num_ctrs ||
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smmu_pmu_check_global_filter(smmu_pmu->events[idx], event)) {
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smmu_pmu_set_event_filter(event, 0, span, sid);
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return 0;
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}
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2019-03-26 09:17:51 -06:00
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2019-08-01 09:22:45 -06:00
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return -EAGAIN;
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2019-03-26 09:17:51 -06:00
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}
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static int smmu_pmu_get_event_idx(struct smmu_pmu *smmu_pmu,
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struct perf_event *event)
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{
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int idx, err;
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unsigned int num_ctrs = smmu_pmu->num_counters;
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idx = find_first_zero_bit(smmu_pmu->used_counters, num_ctrs);
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if (idx == num_ctrs)
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/* The counters are all in use. */
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return -EAGAIN;
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|
|
|
|
|
|
err = smmu_pmu_apply_event_filter(smmu_pmu, event, idx);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
set_bit(idx, smmu_pmu->used_counters);
|
|
|
|
|
|
|
|
return idx;
|
|
|
|
}
|
|
|
|
|
2019-08-01 09:22:45 -06:00
|
|
|
static bool smmu_pmu_events_compatible(struct perf_event *curr,
|
|
|
|
struct perf_event *new)
|
|
|
|
{
|
|
|
|
if (new->pmu != curr->pmu)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (to_smmu_pmu(new->pmu)->global_filter &&
|
|
|
|
!smmu_pmu_check_global_filter(curr, new))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2019-03-26 09:17:51 -06:00
|
|
|
/*
|
|
|
|
* Implementation of abstract pmu functionality required by
|
|
|
|
* the core perf events code.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int smmu_pmu_event_init(struct perf_event *event)
|
|
|
|
{
|
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
|
|
|
|
struct device *dev = smmu_pmu->dev;
|
|
|
|
struct perf_event *sibling;
|
2019-08-01 09:22:44 -06:00
|
|
|
int group_num_events = 1;
|
2019-03-26 09:17:51 -06:00
|
|
|
u16 event_id;
|
|
|
|
|
|
|
|
if (event->attr.type != event->pmu->type)
|
|
|
|
return -ENOENT;
|
|
|
|
|
|
|
|
if (hwc->sample_period) {
|
|
|
|
dev_dbg(dev, "Sampling not supported\n");
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (event->cpu < 0) {
|
|
|
|
dev_dbg(dev, "Per-task mode not supported\n");
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Verify specified event is supported on this PMU */
|
|
|
|
event_id = get_event(event);
|
|
|
|
if (event_id < SMMU_PMCG_ARCH_MAX_EVENTS &&
|
|
|
|
(!test_bit(event_id, smmu_pmu->supported_events))) {
|
|
|
|
dev_dbg(dev, "Invalid event %d for this PMU\n", event_id);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Don't allow groups with mixed PMUs, except for s/w events */
|
2019-08-01 09:22:44 -06:00
|
|
|
if (!is_software_event(event->group_leader)) {
|
2019-08-01 09:22:45 -06:00
|
|
|
if (!smmu_pmu_events_compatible(event->group_leader, event))
|
2019-08-01 09:22:44 -06:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (++group_num_events > smmu_pmu->num_counters)
|
|
|
|
return -EINVAL;
|
2019-03-26 09:17:51 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
for_each_sibling_event(sibling, event->group_leader) {
|
2019-08-01 09:22:44 -06:00
|
|
|
if (is_software_event(sibling))
|
|
|
|
continue;
|
|
|
|
|
2019-08-01 09:22:45 -06:00
|
|
|
if (!smmu_pmu_events_compatible(sibling, event))
|
2019-08-01 09:22:44 -06:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (++group_num_events > smmu_pmu->num_counters)
|
2019-03-26 09:17:51 -06:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
hwc->idx = -1;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Ensure all events are on the same cpu so all events are in the
|
|
|
|
* same cpu context, to avoid races on pmu_enable etc.
|
|
|
|
*/
|
|
|
|
event->cpu = smmu_pmu->on_cpu;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void smmu_pmu_event_start(struct perf_event *event, int flags)
|
|
|
|
{
|
|
|
|
struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
|
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
int idx = hwc->idx;
|
|
|
|
|
|
|
|
hwc->state = 0;
|
|
|
|
|
|
|
|
smmu_pmu_set_period(smmu_pmu, hwc);
|
|
|
|
|
|
|
|
smmu_pmu_counter_enable(smmu_pmu, idx);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void smmu_pmu_event_stop(struct perf_event *event, int flags)
|
|
|
|
{
|
|
|
|
struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
|
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
int idx = hwc->idx;
|
|
|
|
|
|
|
|
if (hwc->state & PERF_HES_STOPPED)
|
|
|
|
return;
|
|
|
|
|
|
|
|
smmu_pmu_counter_disable(smmu_pmu, idx);
|
|
|
|
/* As the counter gets updated on _start, ignore PERF_EF_UPDATE */
|
|
|
|
smmu_pmu_event_update(event);
|
|
|
|
hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int smmu_pmu_event_add(struct perf_event *event, int flags)
|
|
|
|
{
|
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
int idx;
|
|
|
|
struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
|
|
|
|
|
|
|
|
idx = smmu_pmu_get_event_idx(smmu_pmu, event);
|
|
|
|
if (idx < 0)
|
|
|
|
return idx;
|
|
|
|
|
|
|
|
hwc->idx = idx;
|
|
|
|
hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
|
|
|
|
smmu_pmu->events[idx] = event;
|
|
|
|
local64_set(&hwc->prev_count, 0);
|
|
|
|
|
|
|
|
smmu_pmu_interrupt_enable(smmu_pmu, idx);
|
|
|
|
|
|
|
|
if (flags & PERF_EF_START)
|
|
|
|
smmu_pmu_event_start(event, flags);
|
|
|
|
|
|
|
|
/* Propagate changes to the userspace mapping. */
|
|
|
|
perf_event_update_userpage(event);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void smmu_pmu_event_del(struct perf_event *event, int flags)
|
|
|
|
{
|
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
struct smmu_pmu *smmu_pmu = to_smmu_pmu(event->pmu);
|
|
|
|
int idx = hwc->idx;
|
|
|
|
|
|
|
|
smmu_pmu_event_stop(event, flags | PERF_EF_UPDATE);
|
|
|
|
smmu_pmu_interrupt_disable(smmu_pmu, idx);
|
|
|
|
smmu_pmu->events[idx] = NULL;
|
|
|
|
clear_bit(idx, smmu_pmu->used_counters);
|
|
|
|
|
|
|
|
perf_event_update_userpage(event);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void smmu_pmu_event_read(struct perf_event *event)
|
|
|
|
{
|
|
|
|
smmu_pmu_event_update(event);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* cpumask */
|
|
|
|
|
|
|
|
static ssize_t smmu_pmu_cpumask_show(struct device *dev,
|
|
|
|
struct device_attribute *attr,
|
|
|
|
char *buf)
|
|
|
|
{
|
|
|
|
struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
|
|
|
|
|
|
|
|
return cpumap_print_to_pagebuf(true, buf, cpumask_of(smmu_pmu->on_cpu));
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct device_attribute smmu_pmu_cpumask_attr =
|
|
|
|
__ATTR(cpumask, 0444, smmu_pmu_cpumask_show, NULL);
|
|
|
|
|
|
|
|
static struct attribute *smmu_pmu_cpumask_attrs[] = {
|
|
|
|
&smmu_pmu_cpumask_attr.attr,
|
|
|
|
NULL
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct attribute_group smmu_pmu_cpumask_group = {
|
|
|
|
.attrs = smmu_pmu_cpumask_attrs,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Events */
|
|
|
|
|
|
|
|
static ssize_t smmu_pmu_event_show(struct device *dev,
|
|
|
|
struct device_attribute *attr, char *page)
|
|
|
|
{
|
|
|
|
struct perf_pmu_events_attr *pmu_attr;
|
|
|
|
|
|
|
|
pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
|
|
|
|
|
|
|
|
return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define SMMU_EVENT_ATTR(name, config) \
|
|
|
|
PMU_EVENT_ATTR(name, smmu_event_attr_##name, \
|
|
|
|
config, smmu_pmu_event_show)
|
|
|
|
SMMU_EVENT_ATTR(cycles, 0);
|
|
|
|
SMMU_EVENT_ATTR(transaction, 1);
|
|
|
|
SMMU_EVENT_ATTR(tlb_miss, 2);
|
|
|
|
SMMU_EVENT_ATTR(config_cache_miss, 3);
|
|
|
|
SMMU_EVENT_ATTR(trans_table_walk_access, 4);
|
|
|
|
SMMU_EVENT_ATTR(config_struct_access, 5);
|
|
|
|
SMMU_EVENT_ATTR(pcie_ats_trans_rq, 6);
|
|
|
|
SMMU_EVENT_ATTR(pcie_ats_trans_passed, 7);
|
|
|
|
|
|
|
|
static struct attribute *smmu_pmu_events[] = {
|
|
|
|
&smmu_event_attr_cycles.attr.attr,
|
|
|
|
&smmu_event_attr_transaction.attr.attr,
|
|
|
|
&smmu_event_attr_tlb_miss.attr.attr,
|
|
|
|
&smmu_event_attr_config_cache_miss.attr.attr,
|
|
|
|
&smmu_event_attr_trans_table_walk_access.attr.attr,
|
|
|
|
&smmu_event_attr_config_struct_access.attr.attr,
|
|
|
|
&smmu_event_attr_pcie_ats_trans_rq.attr.attr,
|
|
|
|
&smmu_event_attr_pcie_ats_trans_passed.attr.attr,
|
|
|
|
NULL
|
|
|
|
};
|
|
|
|
|
|
|
|
static umode_t smmu_pmu_event_is_visible(struct kobject *kobj,
|
|
|
|
struct attribute *attr, int unused)
|
|
|
|
{
|
|
|
|
struct device *dev = kobj_to_dev(kobj);
|
|
|
|
struct smmu_pmu *smmu_pmu = to_smmu_pmu(dev_get_drvdata(dev));
|
|
|
|
struct perf_pmu_events_attr *pmu_attr;
|
|
|
|
|
|
|
|
pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
|
|
|
|
|
|
|
|
if (test_bit(pmu_attr->id, smmu_pmu->supported_events))
|
|
|
|
return attr->mode;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct attribute_group smmu_pmu_events_group = {
|
|
|
|
.name = "events",
|
|
|
|
.attrs = smmu_pmu_events,
|
|
|
|
.is_visible = smmu_pmu_event_is_visible,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Formats */
|
|
|
|
PMU_FORMAT_ATTR(event, "config:0-15");
|
|
|
|
PMU_FORMAT_ATTR(filter_stream_id, "config1:0-31");
|
|
|
|
PMU_FORMAT_ATTR(filter_span, "config1:32");
|
|
|
|
PMU_FORMAT_ATTR(filter_enable, "config1:33");
|
|
|
|
|
|
|
|
static struct attribute *smmu_pmu_formats[] = {
|
|
|
|
&format_attr_event.attr,
|
|
|
|
&format_attr_filter_stream_id.attr,
|
|
|
|
&format_attr_filter_span.attr,
|
|
|
|
&format_attr_filter_enable.attr,
|
|
|
|
NULL
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct attribute_group smmu_pmu_format_group = {
|
|
|
|
.name = "format",
|
|
|
|
.attrs = smmu_pmu_formats,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct attribute_group *smmu_pmu_attr_grps[] = {
|
|
|
|
&smmu_pmu_cpumask_group,
|
|
|
|
&smmu_pmu_events_group,
|
|
|
|
&smmu_pmu_format_group,
|
|
|
|
NULL
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Generic device handlers
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int smmu_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
|
|
|
|
{
|
|
|
|
struct smmu_pmu *smmu_pmu;
|
|
|
|
unsigned int target;
|
|
|
|
|
|
|
|
smmu_pmu = hlist_entry_safe(node, struct smmu_pmu, node);
|
|
|
|
if (cpu != smmu_pmu->on_cpu)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
target = cpumask_any_but(cpu_online_mask, cpu);
|
|
|
|
if (target >= nr_cpu_ids)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
perf_pmu_migrate_context(&smmu_pmu->pmu, cpu, target);
|
|
|
|
smmu_pmu->on_cpu = target;
|
|
|
|
WARN_ON(irq_set_affinity_hint(smmu_pmu->irq, cpumask_of(target)));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t smmu_pmu_handle_irq(int irq_num, void *data)
|
|
|
|
{
|
|
|
|
struct smmu_pmu *smmu_pmu = data;
|
|
|
|
u64 ovsr;
|
|
|
|
unsigned int idx;
|
|
|
|
|
|
|
|
ovsr = readq(smmu_pmu->reloc_base + SMMU_PMCG_OVSSET0);
|
|
|
|
if (!ovsr)
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
writeq(ovsr, smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0);
|
|
|
|
|
|
|
|
for_each_set_bit(idx, (unsigned long *)&ovsr, smmu_pmu->num_counters) {
|
|
|
|
struct perf_event *event = smmu_pmu->events[idx];
|
|
|
|
struct hw_perf_event *hwc;
|
|
|
|
|
|
|
|
if (WARN_ON_ONCE(!event))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
smmu_pmu_event_update(event);
|
|
|
|
hwc = &event->hw;
|
|
|
|
|
|
|
|
smmu_pmu_set_period(smmu_pmu, hwc);
|
|
|
|
}
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2019-03-26 09:17:52 -06:00
|
|
|
static void smmu_pmu_free_msis(void *data)
|
|
|
|
{
|
|
|
|
struct device *dev = data;
|
|
|
|
|
|
|
|
platform_msi_domain_free_irqs(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void smmu_pmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
|
|
|
|
{
|
|
|
|
phys_addr_t doorbell;
|
|
|
|
struct device *dev = msi_desc_to_dev(desc);
|
|
|
|
struct smmu_pmu *pmu = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo;
|
|
|
|
doorbell &= MSI_CFG0_ADDR_MASK;
|
|
|
|
|
|
|
|
writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);
|
|
|
|
writel_relaxed(msg->data, pmu->reg_base + SMMU_PMCG_IRQ_CFG1);
|
|
|
|
writel_relaxed(MSI_CFG2_MEMATTR_DEVICE_nGnRE,
|
|
|
|
pmu->reg_base + SMMU_PMCG_IRQ_CFG2);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void smmu_pmu_setup_msi(struct smmu_pmu *pmu)
|
|
|
|
{
|
|
|
|
struct msi_desc *desc;
|
|
|
|
struct device *dev = pmu->dev;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Clear MSI address reg */
|
|
|
|
writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);
|
|
|
|
|
|
|
|
/* MSI supported or not */
|
|
|
|
if (!(readl(pmu->reg_base + SMMU_PMCG_CFGR) & SMMU_PMCG_CFGR_MSI))
|
|
|
|
return;
|
|
|
|
|
|
|
|
ret = platform_msi_domain_alloc_irqs(dev, 1, smmu_pmu_write_msi_msg);
|
|
|
|
if (ret) {
|
|
|
|
dev_warn(dev, "failed to allocate MSIs\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
desc = first_msi_entry(dev);
|
|
|
|
if (desc)
|
|
|
|
pmu->irq = desc->irq;
|
|
|
|
|
|
|
|
/* Add callback to free MSIs on teardown */
|
|
|
|
devm_add_action(dev, smmu_pmu_free_msis, dev);
|
|
|
|
}
|
|
|
|
|
2019-03-26 09:17:51 -06:00
|
|
|
static int smmu_pmu_setup_irq(struct smmu_pmu *pmu)
|
|
|
|
{
|
|
|
|
unsigned long flags = IRQF_NOBALANCING | IRQF_SHARED | IRQF_NO_THREAD;
|
|
|
|
int irq, ret = -ENXIO;
|
|
|
|
|
2019-03-26 09:17:52 -06:00
|
|
|
smmu_pmu_setup_msi(pmu);
|
|
|
|
|
2019-03-26 09:17:51 -06:00
|
|
|
irq = pmu->irq;
|
|
|
|
if (irq)
|
|
|
|
ret = devm_request_irq(pmu->dev, irq, smmu_pmu_handle_irq,
|
|
|
|
flags, "smmuv3-pmu", pmu);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void smmu_pmu_reset(struct smmu_pmu *smmu_pmu)
|
|
|
|
{
|
|
|
|
u64 counter_present_mask = GENMASK_ULL(smmu_pmu->num_counters - 1, 0);
|
|
|
|
|
|
|
|
smmu_pmu_disable(&smmu_pmu->pmu);
|
|
|
|
|
|
|
|
/* Disable counter and interrupt */
|
|
|
|
writeq_relaxed(counter_present_mask,
|
|
|
|
smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);
|
|
|
|
writeq_relaxed(counter_present_mask,
|
|
|
|
smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0);
|
|
|
|
writeq_relaxed(counter_present_mask,
|
|
|
|
smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0);
|
|
|
|
}
|
|
|
|
|
2019-03-26 09:17:53 -06:00
|
|
|
static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu)
|
|
|
|
{
|
|
|
|
u32 model;
|
|
|
|
|
|
|
|
model = *(u32 *)dev_get_platdata(smmu_pmu->dev);
|
|
|
|
|
|
|
|
switch (model) {
|
|
|
|
case IORT_SMMU_V3_PMCG_HISI_HIP08:
|
|
|
|
/* HiSilicon Erratum 162001800 */
|
|
|
|
smmu_pmu->options |= SMMU_PMCG_EVCNTR_RDONLY;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options);
|
|
|
|
}
|
|
|
|
|
2019-03-26 09:17:51 -06:00
|
|
|
static int smmu_pmu_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct smmu_pmu *smmu_pmu;
|
2019-09-08 19:22:57 -06:00
|
|
|
struct resource *res_0;
|
2019-03-26 09:17:51 -06:00
|
|
|
u32 cfgr, reg_size;
|
|
|
|
u64 ceid_64[2];
|
|
|
|
int irq, err;
|
|
|
|
char *name;
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
|
|
|
|
smmu_pmu = devm_kzalloc(dev, sizeof(*smmu_pmu), GFP_KERNEL);
|
|
|
|
if (!smmu_pmu)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
smmu_pmu->dev = dev;
|
|
|
|
platform_set_drvdata(pdev, smmu_pmu);
|
|
|
|
|
|
|
|
smmu_pmu->pmu = (struct pmu) {
|
|
|
|
.task_ctx_nr = perf_invalid_context,
|
|
|
|
.pmu_enable = smmu_pmu_enable,
|
|
|
|
.pmu_disable = smmu_pmu_disable,
|
|
|
|
.event_init = smmu_pmu_event_init,
|
|
|
|
.add = smmu_pmu_event_add,
|
|
|
|
.del = smmu_pmu_event_del,
|
|
|
|
.start = smmu_pmu_event_start,
|
|
|
|
.stop = smmu_pmu_event_stop,
|
|
|
|
.read = smmu_pmu_event_read,
|
|
|
|
.attr_groups = smmu_pmu_attr_grps,
|
|
|
|
.capabilities = PERF_PMU_CAP_NO_EXCLUDE,
|
|
|
|
};
|
|
|
|
|
|
|
|
res_0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
smmu_pmu->reg_base = devm_ioremap_resource(dev, res_0);
|
|
|
|
if (IS_ERR(smmu_pmu->reg_base))
|
|
|
|
return PTR_ERR(smmu_pmu->reg_base);
|
|
|
|
|
|
|
|
cfgr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CFGR);
|
|
|
|
|
|
|
|
/* Determine if page 1 is present */
|
|
|
|
if (cfgr & SMMU_PMCG_CFGR_RELOC_CTRS) {
|
2019-09-08 19:22:57 -06:00
|
|
|
smmu_pmu->reloc_base = devm_platform_ioremap_resource(pdev, 1);
|
2019-03-26 09:17:51 -06:00
|
|
|
if (IS_ERR(smmu_pmu->reloc_base))
|
|
|
|
return PTR_ERR(smmu_pmu->reloc_base);
|
|
|
|
} else {
|
|
|
|
smmu_pmu->reloc_base = smmu_pmu->reg_base;
|
|
|
|
}
|
|
|
|
|
2020-02-10 09:50:17 -07:00
|
|
|
irq = platform_get_irq_optional(pdev, 0);
|
2019-03-26 09:17:51 -06:00
|
|
|
if (irq > 0)
|
|
|
|
smmu_pmu->irq = irq;
|
|
|
|
|
|
|
|
ceid_64[0] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID0);
|
|
|
|
ceid_64[1] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID1);
|
|
|
|
bitmap_from_arr32(smmu_pmu->supported_events, (u32 *)ceid_64,
|
|
|
|
SMMU_PMCG_ARCH_MAX_EVENTS);
|
|
|
|
|
|
|
|
smmu_pmu->num_counters = FIELD_GET(SMMU_PMCG_CFGR_NCTR, cfgr) + 1;
|
|
|
|
|
|
|
|
smmu_pmu->global_filter = !!(cfgr & SMMU_PMCG_CFGR_SID_FILTER_TYPE);
|
|
|
|
|
|
|
|
reg_size = FIELD_GET(SMMU_PMCG_CFGR_SIZE, cfgr);
|
|
|
|
smmu_pmu->counter_mask = GENMASK_ULL(reg_size, 0);
|
|
|
|
|
|
|
|
smmu_pmu_reset(smmu_pmu);
|
|
|
|
|
|
|
|
err = smmu_pmu_setup_irq(smmu_pmu);
|
|
|
|
if (err) {
|
|
|
|
dev_err(dev, "Setup irq failed, PMU @%pa\n", &res_0->start);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "smmuv3_pmcg_%llx",
|
|
|
|
(res_0->start) >> SMMU_PMCG_PA_SHIFT);
|
|
|
|
if (!name) {
|
|
|
|
dev_err(dev, "Create name failed, PMU @%pa\n", &res_0->start);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2019-03-26 09:17:53 -06:00
|
|
|
smmu_pmu_get_acpi_options(smmu_pmu);
|
|
|
|
|
2019-03-26 09:17:51 -06:00
|
|
|
/* Pick one CPU to be the preferred one to use */
|
|
|
|
smmu_pmu->on_cpu = raw_smp_processor_id();
|
|
|
|
WARN_ON(irq_set_affinity_hint(smmu_pmu->irq,
|
|
|
|
cpumask_of(smmu_pmu->on_cpu)));
|
|
|
|
|
|
|
|
err = cpuhp_state_add_instance_nocalls(cpuhp_state_num,
|
|
|
|
&smmu_pmu->node);
|
|
|
|
if (err) {
|
|
|
|
dev_err(dev, "Error %d registering hotplug, PMU @%pa\n",
|
|
|
|
err, &res_0->start);
|
2019-12-10 23:43:06 -07:00
|
|
|
return err;
|
2019-03-26 09:17:51 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
err = perf_pmu_register(&smmu_pmu->pmu, name, -1);
|
|
|
|
if (err) {
|
|
|
|
dev_err(dev, "Error %d registering PMU @%pa\n",
|
|
|
|
err, &res_0->start);
|
|
|
|
goto out_unregister;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_info(dev, "Registered PMU @ %pa using %d counters with %s filter settings\n",
|
|
|
|
&res_0->start, smmu_pmu->num_counters,
|
|
|
|
smmu_pmu->global_filter ? "Global(Counter0)" :
|
|
|
|
"Individual");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
out_unregister:
|
|
|
|
cpuhp_state_remove_instance_nocalls(cpuhp_state_num, &smmu_pmu->node);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int smmu_pmu_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct smmu_pmu *smmu_pmu = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
perf_pmu_unregister(&smmu_pmu->pmu);
|
|
|
|
cpuhp_state_remove_instance_nocalls(cpuhp_state_num, &smmu_pmu->node);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void smmu_pmu_shutdown(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct smmu_pmu *smmu_pmu = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
smmu_pmu_disable(&smmu_pmu->pmu);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver smmu_pmu_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "arm-smmu-v3-pmcg",
|
|
|
|
},
|
|
|
|
.probe = smmu_pmu_probe,
|
|
|
|
.remove = smmu_pmu_remove,
|
|
|
|
.shutdown = smmu_pmu_shutdown,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init arm_smmu_pmu_init(void)
|
|
|
|
{
|
|
|
|
cpuhp_state_num = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
|
|
|
|
"perf/arm/pmcg:online",
|
|
|
|
NULL,
|
|
|
|
smmu_pmu_offline_cpu);
|
|
|
|
if (cpuhp_state_num < 0)
|
|
|
|
return cpuhp_state_num;
|
|
|
|
|
|
|
|
return platform_driver_register(&smmu_pmu_driver);
|
|
|
|
}
|
|
|
|
module_init(arm_smmu_pmu_init);
|
|
|
|
|
|
|
|
static void __exit arm_smmu_pmu_exit(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&smmu_pmu_driver);
|
|
|
|
cpuhp_remove_multi_state(cpuhp_state_num);
|
|
|
|
}
|
|
|
|
|
|
|
|
module_exit(arm_smmu_pmu_exit);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("PMU driver for ARM SMMUv3 Performance Monitors Extension");
|
|
|
|
MODULE_AUTHOR("Neil Leeder <nleeder@codeaurora.org>");
|
|
|
|
MODULE_AUTHOR("Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>");
|
|
|
|
MODULE_LICENSE("GPL v2");
|