2013-08-01 15:00:20 -06:00
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/*
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* Copyright 2003 Digi International (www.digi.com)
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* Scott H Kilau <Scott_Kilau at digi dot com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
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* implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* NOTE: THIS IS A SHARED HEADER. DO NOT CHANGE CODING STYLE!!!
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*
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*/
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#ifndef __DGNC_CLS_H
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#define __DGNC_CLS_H
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#include "dgnc_types.h"
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2013-08-21 09:08:01 -06:00
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/************************************************************************
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2013-08-01 15:00:20 -06:00
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* Per channel/port Classic UART structure *
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************************************************************************
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* Base Structure Entries Usage Meanings to Host *
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* *
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2013-08-21 09:08:01 -06:00
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* W = read write R = read only *
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* U = Unused. *
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************************************************************************/
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struct cls_uart_struct {
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2013-08-26 08:53:09 -06:00
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u8 txrx; /* WR RHR/THR - Holding Reg */
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u8 ier; /* WR IER - Interrupt Enable Reg */
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u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
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u8 lcr; /* WR LCR - Line Control Reg */
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u8 mcr; /* WR MCR - Modem Control Reg */
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u8 lsr; /* WR LSR - Line Status Reg */
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u8 msr; /* WR MSR - Modem Status Reg */
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u8 spr; /* WR SPR - Scratch Pad Reg */
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2013-08-01 15:00:20 -06:00
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};
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/* Where to read the interrupt register (8bits) */
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#define UART_CLASSIC_POLL_ADDR_OFFSET 0x40
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#define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF
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#define UART_16654_FCR_TXTRIGGER_8 0x0
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#define UART_16654_FCR_TXTRIGGER_16 0x10
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#define UART_16654_FCR_TXTRIGGER_32 0x20
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#define UART_16654_FCR_TXTRIGGER_56 0x30
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#define UART_16654_FCR_RXTRIGGER_8 0x0
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#define UART_16654_FCR_RXTRIGGER_16 0x40
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#define UART_16654_FCR_RXTRIGGER_56 0x80
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#define UART_16654_FCR_RXTRIGGER_60 0xC0
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#define UART_IIR_CTSRTS 0x20 /* Received CTS/RTS change of state */
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#define UART_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */
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/*
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* These are the EXTENDED definitions for the Exar 654's Interrupt
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* Enable Register.
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*/
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#define UART_EXAR654_EFR_ECB 0x10 /* Enhanced control bit */
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#define UART_EXAR654_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
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#define UART_EXAR654_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
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#define UART_EXAR654_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
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#define UART_EXAR654_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */
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#define UART_EXAR654_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */
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#define UART_EXAR654_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */
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#define UART_EXAR654_IER_XOFF 0x20 /* Xoff Interrupt Enable */
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#define UART_EXAR654_IER_RTSDTR 0x40 /* Output Interrupt Enable */
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#define UART_EXAR654_IER_CTSDSR 0x80 /* Input Interrupt Enable */
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2013-08-21 09:08:01 -06:00
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/*
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* Our Global Variables
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*/
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extern struct board_ops dgnc_cls_ops;
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#endif
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