2008-03-18 03:24:28 -06:00
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/*
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* OMAP3 clock framework
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*
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* Copyright (C) 2007-2008 Texas Instruments, Inc.
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* Copyright (C) 2007-2008 Nokia Corporation
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*
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* Written by Paul Walmsley
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2008-07-03 03:24:45 -06:00
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* With many device clock fixes by Kevin Hilman and Jouni Högander
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* DPLL bypass clock support added by Roman Tereshonkov
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*
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*/
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/*
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* Virtual clocks are introduced as convenient tools.
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* They are sources for other clocks and not supposed
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* to be requested from drivers directly.
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2008-03-18 03:24:28 -06:00
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
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#define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
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2009-10-20 10:40:47 -06:00
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#include <plat/control.h>
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2008-03-18 03:24:28 -06:00
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#include "clock.h"
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#include "cm.h"
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#include "cm-regbits-34xx.h"
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#include "prm.h"
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#include "prm-regbits-34xx.h"
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2009-05-25 12:26:46 -06:00
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#define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
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2009-02-12 03:12:59 -07:00
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static unsigned long omap3_dpll_recalc(struct clk *clk);
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static unsigned long omap3_clkoutx2_recalc(struct clk *clk);
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2008-07-03 03:24:45 -06:00
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static void omap3_dpll_allow_idle(struct clk *clk);
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static void omap3_dpll_deny_idle(struct clk *clk);
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static u32 omap3_dpll_autoidle_read(struct clk *clk);
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2009-01-27 19:12:47 -07:00
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static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
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static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate);
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2009-01-28 12:27:42 -07:00
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static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate);
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2008-03-18 03:24:28 -06:00
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ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
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/* Maximum DPLL multiplier, divider values for OMAP3 */
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#define OMAP3_MAX_DPLL_MULT 2048
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#define OMAP3_MAX_DPLL_DIV 128
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2008-03-18 03:24:28 -06:00
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/*
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* DPLL1 supplies clock to the MPU.
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* DPLL2 supplies clock to the IVA2.
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* DPLL3 supplies CORE domain clocks.
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* DPLL4 supplies peripheral clocks.
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* DPLL5 supplies other peripheral clocks (USBHOST, USIM).
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*/
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[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 06:29:22 -07:00
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/* Forward declarations for DPLL bypass clocks */
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static struct clk dpll1_fck;
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static struct clk dpll2_fck;
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2008-07-03 03:24:45 -06:00
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/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
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#define DPLL_LOW_POWER_STOP 0x1
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#define DPLL_LOW_POWER_BYPASS 0x5
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#define DPLL_LOCKED 0x7
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2008-03-18 03:24:28 -06:00
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/* PRM CLOCKS */
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/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
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static struct clk omap_32k_fck = {
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.name = "omap_32k_fck",
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2008-11-04 09:35:03 -07:00
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.ops = &clkops_null,
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2008-03-18 03:24:28 -06:00
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.rate = 32768,
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2009-01-31 03:05:51 -07:00
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.flags = RATE_FIXED,
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2008-03-18 03:24:28 -06:00
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};
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static struct clk secure_32k_fck = {
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.name = "secure_32k_fck",
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2008-11-04 09:35:03 -07:00
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.ops = &clkops_null,
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2008-03-18 03:24:28 -06:00
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.rate = 32768,
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2009-01-31 03:05:51 -07:00
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.flags = RATE_FIXED,
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2008-03-18 03:24:28 -06:00
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};
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/* Virtual source clocks for osc_sys_ck */
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static struct clk virt_12m_ck = {
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.name = "virt_12m_ck",
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2008-11-04 09:35:03 -07:00
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.ops = &clkops_null,
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2008-03-18 03:24:28 -06:00
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.rate = 12000000,
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2009-01-31 03:05:51 -07:00
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.flags = RATE_FIXED,
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2008-03-18 03:24:28 -06:00
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};
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static struct clk virt_13m_ck = {
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.name = "virt_13m_ck",
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2008-11-04 09:35:03 -07:00
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.ops = &clkops_null,
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2008-03-18 03:24:28 -06:00
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.rate = 13000000,
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2009-01-31 03:05:51 -07:00
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.flags = RATE_FIXED,
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2008-03-18 03:24:28 -06:00
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};
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static struct clk virt_16_8m_ck = {
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.name = "virt_16_8m_ck",
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2008-11-04 09:35:03 -07:00
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.ops = &clkops_null,
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2008-03-18 03:24:28 -06:00
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.rate = 16800000,
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2009-01-31 03:05:51 -07:00
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.flags = RATE_FIXED,
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2008-03-18 03:24:28 -06:00
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};
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static struct clk virt_19_2m_ck = {
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.name = "virt_19_2m_ck",
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2008-11-04 09:35:03 -07:00
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.ops = &clkops_null,
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2008-03-18 03:24:28 -06:00
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.rate = 19200000,
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2009-01-31 03:05:51 -07:00
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.flags = RATE_FIXED,
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2008-03-18 03:24:28 -06:00
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};
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static struct clk virt_26m_ck = {
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.name = "virt_26m_ck",
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2008-11-04 09:35:03 -07:00
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.ops = &clkops_null,
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2008-03-18 03:24:28 -06:00
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.rate = 26000000,
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2009-01-31 03:05:51 -07:00
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.flags = RATE_FIXED,
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2008-03-18 03:24:28 -06:00
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};
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static struct clk virt_38_4m_ck = {
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.name = "virt_38_4m_ck",
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2008-11-04 09:35:03 -07:00
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.ops = &clkops_null,
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2008-03-18 03:24:28 -06:00
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.rate = 38400000,
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2009-01-31 03:05:51 -07:00
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.flags = RATE_FIXED,
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2008-03-18 03:24:28 -06:00
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};
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static const struct clksel_rate osc_sys_12m_rates[] = {
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{ .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
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{ .div = 0 }
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};
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static const struct clksel_rate osc_sys_13m_rates[] = {
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{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
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{ .div = 0 }
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};
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static const struct clksel_rate osc_sys_16_8m_rates[] = {
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{ .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
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{ .div = 0 }
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};
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static const struct clksel_rate osc_sys_19_2m_rates[] = {
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{ .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
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{ .div = 0 }
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};
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static const struct clksel_rate osc_sys_26m_rates[] = {
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{ .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
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{ .div = 0 }
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};
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static const struct clksel_rate osc_sys_38_4m_rates[] = {
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{ .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
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{ .div = 0 }
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};
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static const struct clksel osc_sys_clksel[] = {
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{ .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
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{ .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
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{ .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
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{ .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
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{ .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
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{ .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
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{ .parent = NULL },
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};
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/* Oscillator clock */
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/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
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static struct clk osc_sys_ck = {
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.name = "osc_sys_ck",
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2008-11-04 09:35:03 -07:00
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.ops = &clkops_null,
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2008-03-18 03:24:28 -06:00
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.init = &omap2_init_clksel_parent,
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.clksel_reg = OMAP3430_PRM_CLKSEL,
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.clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
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.clksel = osc_sys_clksel,
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/* REVISIT: deal with autoextclkmode? */
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2009-01-31 03:05:51 -07:00
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.flags = RATE_FIXED,
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2008-03-18 03:24:28 -06:00
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.recalc = &omap2_clksel_recalc,
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};
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static const struct clksel_rate div2_rates[] = {
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{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
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{ .div = 2, .val = 2, .flags = RATE_IN_343X },
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{ .div = 0 }
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};
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static const struct clksel sys_clksel[] = {
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{ .parent = &osc_sys_ck, .rates = div2_rates },
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{ .parent = NULL }
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};
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/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
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/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
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static struct clk sys_ck = {
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.name = "sys_ck",
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2008-11-04 09:35:03 -07:00
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.ops = &clkops_null,
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2008-03-18 03:24:28 -06:00
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.parent = &osc_sys_ck,
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.init = &omap2_init_clksel_parent,
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.clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
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.clksel_mask = OMAP_SYSCLKDIV_MASK,
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.clksel = sys_clksel,
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.recalc = &omap2_clksel_recalc,
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};
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static struct clk sys_altclk = {
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.name = "sys_altclk",
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2008-11-04 09:35:03 -07:00
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.ops = &clkops_null,
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2008-03-18 03:24:28 -06:00
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};
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/* Optional external clock input for some McBSPs */
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static struct clk mcbsp_clks = {
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.name = "mcbsp_clks",
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2008-11-04 09:35:03 -07:00
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.ops = &clkops_null,
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2008-03-18 03:24:28 -06:00
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};
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/* PRM EXTERNAL CLOCK OUTPUT */
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static struct clk sys_clkout1 = {
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.name = "sys_clkout1",
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[ARM] omap: don't use clkops_omap2_dflt_wait for non-ICLK/FCLK clocks
The original code in omap2_clk_wait_ready() used to check the low 8
bits to determine whether they were within the FCLKEN or ICLKEN
registers. Specifically, the test is satisfied when these offsets
are used:
CM_FCLKEN, CM_FCLKEN1, CM_CLKEN, OMAP24XX_CM_FCLKEN2, CM_ICLKEN,
CM_ICLKEN1, CM_ICLKEN2, CM_ICLKEN3, OMAP24XX_CM_ICLKEN4
OMAP3430_CM_CLKEN_PLL, OMAP3430ES2_CM_CLKEN2
If one of these offsets isn't used, omap2_clk_wait_ready() merely
returns without doing anything. So we should use the non-wait clkops
version instead and eliminate that conditional.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 14:24:00 -07:00
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.ops = &clkops_omap2_dflt,
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2008-03-18 03:24:28 -06:00
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.parent = &osc_sys_ck,
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.enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
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.enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
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.recalc = &followparent_recalc,
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};
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/* DPLLS */
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/* CM CLOCKS */
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2008-03-13 13:35:09 -06:00
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static const struct clksel_rate div16_dpll_rates[] = {
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{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
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{ .div = 2, .val = 2, .flags = RATE_IN_343X },
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{ .div = 3, .val = 3, .flags = RATE_IN_343X },
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{ .div = 4, .val = 4, .flags = RATE_IN_343X },
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{ .div = 5, .val = 5, .flags = RATE_IN_343X },
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{ .div = 6, .val = 6, .flags = RATE_IN_343X },
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{ .div = 7, .val = 7, .flags = RATE_IN_343X },
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{ .div = 8, .val = 8, .flags = RATE_IN_343X },
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{ .div = 9, .val = 9, .flags = RATE_IN_343X },
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{ .div = 10, .val = 10, .flags = RATE_IN_343X },
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{ .div = 11, .val = 11, .flags = RATE_IN_343X },
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{ .div = 12, .val = 12, .flags = RATE_IN_343X },
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{ .div = 13, .val = 13, .flags = RATE_IN_343X },
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{ .div = 14, .val = 14, .flags = RATE_IN_343X },
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{ .div = 15, .val = 15, .flags = RATE_IN_343X },
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{ .div = 16, .val = 16, .flags = RATE_IN_343X },
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{ .div = 0 }
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};
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2008-03-18 03:24:28 -06:00
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/* DPLL1 */
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/* MPU clock source */
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/* Type: DPLL */
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ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
static struct dpll_data dpll1_dd = {
|
2008-03-18 03:24:28 -06:00
|
|
|
.mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
|
|
|
|
.mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
|
|
|
|
.div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
|
[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 06:29:22 -07:00
|
|
|
.clk_bypass = &dpll1_fck,
|
|
|
|
.clk_ref = &sys_ck,
|
2009-01-27 19:12:47 -07:00
|
|
|
.freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
|
2008-03-18 03:24:28 -06:00
|
|
|
.control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
|
|
|
|
.enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
|
2008-07-03 03:24:45 -06:00
|
|
|
.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
|
2008-03-18 03:24:28 -06:00
|
|
|
.auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
|
|
|
|
.recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
|
|
|
|
.recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
|
2008-07-03 03:24:45 -06:00
|
|
|
.autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
|
|
|
|
.autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
|
|
|
|
.idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
|
2009-01-28 12:08:17 -07:00
|
|
|
.idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
.max_multiplier = OMAP3_MAX_DPLL_MULT,
|
2009-01-28 12:08:44 -07:00
|
|
|
.min_divider = 1,
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
.max_divider = OMAP3_MAX_DPLL_DIV,
|
|
|
|
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
|
2008-03-18 03:24:28 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk dpll1_ck = {
|
|
|
|
.name = "dpll1_ck",
|
2008-11-04 09:35:03 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &sys_ck,
|
|
|
|
.dpll_data = &dpll1_dd,
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
.round_rate = &omap2_dpll_round_rate,
|
2009-01-27 19:12:47 -07:00
|
|
|
.set_rate = &omap3_noncore_dpll_set_rate,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll1_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap3_dpll_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
2008-03-13 13:35:09 -06:00
|
|
|
* This virtual clock provides the CLKOUTX2 output from the DPLL if the
|
|
|
|
* DPLL isn't bypassed.
|
2008-03-18 03:24:28 -06:00
|
|
|
*/
|
2008-03-13 13:35:09 -06:00
|
|
|
static struct clk dpll1_x2_ck = {
|
|
|
|
.name = "dpll1_x2_ck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &dpll1_ck,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll1_clkdm",
|
2008-03-13 13:35:09 -06:00
|
|
|
.recalc = &omap3_clkoutx2_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
|
|
|
|
static const struct clksel div16_dpll1_x2m2_clksel[] = {
|
|
|
|
{ .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Does not exist in the TRM - needed to separate the M2 divider from
|
|
|
|
* bypass selection in mpu_ck
|
|
|
|
*/
|
|
|
|
static struct clk dpll1_x2m2_ck = {
|
|
|
|
.name = "dpll1_x2m2_ck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &dpll1_x2_ck,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
|
|
|
|
.clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
|
|
|
|
.clksel = div16_dpll1_x2m2_clksel,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll1_clkdm",
|
2008-03-13 13:35:09 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
2008-03-18 03:24:28 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
/* DPLL2 */
|
|
|
|
/* IVA2 clock source */
|
|
|
|
/* Type: DPLL */
|
|
|
|
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
static struct dpll_data dpll2_dd = {
|
2008-03-18 03:24:28 -06:00
|
|
|
.mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
|
|
|
|
.mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
|
|
|
|
.div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
|
[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 06:29:22 -07:00
|
|
|
.clk_bypass = &dpll2_fck,
|
|
|
|
.clk_ref = &sys_ck,
|
2009-01-27 19:12:47 -07:00
|
|
|
.freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
|
2008-03-18 03:24:28 -06:00
|
|
|
.control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
|
|
|
|
.enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
|
2008-07-03 03:24:45 -06:00
|
|
|
.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
|
|
|
|
(1 << DPLL_LOW_POWER_BYPASS),
|
2008-03-18 03:24:28 -06:00
|
|
|
.auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
|
|
|
|
.recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
|
|
|
|
.recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
|
2008-07-03 03:24:45 -06:00
|
|
|
.autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
|
|
|
|
.autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
|
|
|
|
.idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
|
2009-01-28 12:08:17 -07:00
|
|
|
.idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
.max_multiplier = OMAP3_MAX_DPLL_MULT,
|
2009-01-28 12:08:44 -07:00
|
|
|
.min_divider = 1,
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
.max_divider = OMAP3_MAX_DPLL_DIV,
|
|
|
|
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
|
2008-03-18 03:24:28 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk dpll2_ck = {
|
|
|
|
.name = "dpll2_ck",
|
2008-11-04 07:02:46 -07:00
|
|
|
.ops = &clkops_noncore_dpll_ops,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &sys_ck,
|
|
|
|
.dpll_data = &dpll2_dd,
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
.round_rate = &omap2_dpll_round_rate,
|
2009-01-27 19:12:47 -07:00
|
|
|
.set_rate = &omap3_noncore_dpll_set_rate,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll2_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap3_dpll_recalc,
|
|
|
|
};
|
|
|
|
|
2008-03-13 13:35:09 -06:00
|
|
|
static const struct clksel div16_dpll2_m2x2_clksel[] = {
|
|
|
|
{ .parent = &dpll2_ck, .rates = div16_dpll_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
|
|
|
|
* or CLKOUTX2. CLKOUT seems most plausible.
|
|
|
|
*/
|
|
|
|
static struct clk dpll2_m2_ck = {
|
|
|
|
.name = "dpll2_m2_ck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &dpll2_ck,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
|
|
|
|
OMAP3430_CM_CLKSEL2_PLL),
|
|
|
|
.clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
|
|
|
|
.clksel = div16_dpll2_m2x2_clksel,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll2_clkdm",
|
2008-03-13 13:35:09 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
2008-07-03 03:24:45 -06:00
|
|
|
/*
|
|
|
|
* DPLL3
|
|
|
|
* Source clock for all interfaces and for some device fclks
|
|
|
|
* REVISIT: Also supports fast relock bypass - not included below
|
|
|
|
*/
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
static struct dpll_data dpll3_dd = {
|
2008-03-18 03:24:28 -06:00
|
|
|
.mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
|
|
|
|
.mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
|
|
|
|
.div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
|
[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 06:29:22 -07:00
|
|
|
.clk_bypass = &sys_ck,
|
|
|
|
.clk_ref = &sys_ck,
|
2009-01-27 19:12:47 -07:00
|
|
|
.freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
|
2008-03-18 03:24:28 -06:00
|
|
|
.control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
|
|
|
|
.enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
|
|
|
|
.auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
|
|
|
|
.recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
|
|
|
|
.recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
|
2008-07-03 03:24:45 -06:00
|
|
|
.autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
|
|
|
|
.autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
|
2009-01-28 12:08:17 -07:00
|
|
|
.idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
|
|
|
|
.idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
.max_multiplier = OMAP3_MAX_DPLL_MULT,
|
2009-01-28 12:08:44 -07:00
|
|
|
.min_divider = 1,
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
.max_divider = OMAP3_MAX_DPLL_DIV,
|
|
|
|
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
|
2008-03-18 03:24:28 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk dpll3_ck = {
|
|
|
|
.name = "dpll3_ck",
|
2008-11-04 09:35:03 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &sys_ck,
|
|
|
|
.dpll_data = &dpll3_dd,
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
.round_rate = &omap2_dpll_round_rate,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll3_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap3_dpll_recalc,
|
|
|
|
};
|
|
|
|
|
2008-03-13 13:35:09 -06:00
|
|
|
/*
|
|
|
|
* This virtual clock provides the CLKOUTX2 output from the DPLL if the
|
|
|
|
* DPLL isn't bypassed
|
|
|
|
*/
|
|
|
|
static struct clk dpll3_x2_ck = {
|
|
|
|
.name = "dpll3_x2_ck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &dpll3_ck,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll3_clkdm",
|
2008-03-13 13:35:09 -06:00
|
|
|
.recalc = &omap3_clkoutx2_recalc,
|
2008-03-18 03:24:28 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate div31_dpll3_rates[] = {
|
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 2, .val = 2, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
|
|
|
|
{ .div = 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel div31_dpll3m2_clksel[] = {
|
|
|
|
{ .parent = &dpll3_ck, .rates = div31_dpll3_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
2009-01-28 12:27:42 -07:00
|
|
|
/* DPLL3 output M2 - primary control point for CORE speed */
|
2008-03-18 03:24:28 -06:00
|
|
|
static struct clk dpll3_m2_ck = {
|
|
|
|
.name = "dpll3_m2_ck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &dpll3_ck,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
|
|
|
|
.clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
|
|
|
|
.clksel = div31_dpll3m2_clksel,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll3_clkdm",
|
2009-01-28 12:27:42 -07:00
|
|
|
.round_rate = &omap2_clksel_round_rate,
|
|
|
|
.set_rate = &omap3_core_dpll_m2_set_rate,
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk core_ck = {
|
|
|
|
.name = "core_ck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 06:29:22 -07:00
|
|
|
.parent = &dpll3_m2_ck,
|
|
|
|
.recalc = &followparent_recalc,
|
2008-03-18 03:24:28 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk dpll3_m2x2_ck = {
|
|
|
|
.name = "dpll3_m2x2_ck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2009-11-16 06:36:54 -07:00
|
|
|
.parent = &dpll3_m2_ck,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll3_clkdm",
|
2009-11-16 06:36:54 -07:00
|
|
|
.recalc = &omap3_clkoutx2_recalc,
|
2008-03-13 13:35:09 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
/* The PWRDN bit is apparently only available on 3430ES2 and above */
|
|
|
|
static const struct clksel div16_dpll3_clksel[] = {
|
|
|
|
{ .parent = &dpll3_ck, .rates = div16_dpll_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
|
|
|
/* This virtual clock is the source for dpll3_m3x2_ck */
|
|
|
|
static struct clk dpll3_m3_ck = {
|
|
|
|
.name = "dpll3_m3_ck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &dpll3_ck,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
|
|
|
|
.clksel_mask = OMAP3430_DIV_DPLL3_MASK,
|
|
|
|
.clksel = div16_dpll3_clksel,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll3_clkdm",
|
2008-03-13 13:35:09 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
2008-03-18 03:24:28 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
/* The PWRDN bit is apparently only available on 3430ES2 and above */
|
|
|
|
static struct clk dpll3_m3x2_ck = {
|
|
|
|
.name = "dpll3_m3x2_ck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &dpll3_m3_ck,
|
2008-03-18 03:24:28 -06:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
|
|
|
|
.enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
|
2009-01-31 03:05:51 -07:00
|
|
|
.flags = INVERT_ENABLE,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll3_clkdm",
|
2008-03-13 13:35:09 -06:00
|
|
|
.recalc = &omap3_clkoutx2_recalc,
|
2008-03-18 03:24:28 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk emu_core_alwon_ck = {
|
|
|
|
.name = "emu_core_alwon_ck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &dpll3_m3x2_ck,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll3_clkdm",
|
[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 06:29:22 -07:00
|
|
|
.recalc = &followparent_recalc,
|
2008-03-18 03:24:28 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
/* DPLL4 */
|
|
|
|
/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
|
|
|
|
/* Type: DPLL */
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
static struct dpll_data dpll4_dd = {
|
2008-03-18 03:24:28 -06:00
|
|
|
.mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
|
|
|
|
.mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
|
|
|
|
.div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
|
[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 06:29:22 -07:00
|
|
|
.clk_bypass = &sys_ck,
|
|
|
|
.clk_ref = &sys_ck,
|
2009-01-27 19:12:47 -07:00
|
|
|
.freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
|
2008-03-18 03:24:28 -06:00
|
|
|
.control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
|
|
|
|
.enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
|
2008-07-03 03:24:45 -06:00
|
|
|
.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
|
2008-03-18 03:24:28 -06:00
|
|
|
.auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
|
|
|
|
.recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
|
|
|
|
.recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
|
2008-07-03 03:24:45 -06:00
|
|
|
.autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
|
|
|
|
.autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
|
|
|
|
.idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
|
2009-01-28 12:08:17 -07:00
|
|
|
.idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
.max_multiplier = OMAP3_MAX_DPLL_MULT,
|
2009-01-28 12:08:44 -07:00
|
|
|
.min_divider = 1,
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
.max_divider = OMAP3_MAX_DPLL_DIV,
|
|
|
|
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
|
2008-03-18 03:24:28 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk dpll4_ck = {
|
|
|
|
.name = "dpll4_ck",
|
2008-11-04 07:02:46 -07:00
|
|
|
.ops = &clkops_noncore_dpll_ops,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &sys_ck,
|
|
|
|
.dpll_data = &dpll4_dd,
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
.round_rate = &omap2_dpll_round_rate,
|
2009-01-27 19:12:47 -07:00
|
|
|
.set_rate = &omap3_dpll4_set_rate,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap3_dpll_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This virtual clock provides the CLKOUTX2 output from the DPLL if the
|
2008-03-13 13:35:09 -06:00
|
|
|
* DPLL isn't bypassed --
|
|
|
|
* XXX does this serve any downstream clocks?
|
2008-03-18 03:24:28 -06:00
|
|
|
*/
|
|
|
|
static struct clk dpll4_x2_ck = {
|
|
|
|
.name = "dpll4_x2_ck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &dpll4_ck,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap3_clkoutx2_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel div16_dpll4_clksel[] = {
|
2008-03-13 13:35:09 -06:00
|
|
|
{ .parent = &dpll4_ck, .rates = div16_dpll_rates },
|
2008-03-18 03:24:28 -06:00
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
2008-03-13 13:35:09 -06:00
|
|
|
/* This virtual clock is the source for dpll4_m2x2_ck */
|
|
|
|
static struct clk dpll4_m2_ck = {
|
|
|
|
.name = "dpll4_m2_ck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &dpll4_ck,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
|
|
|
|
.clksel_mask = OMAP3430_DIV_96M_MASK,
|
|
|
|
.clksel = div16_dpll4_clksel,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll4_clkdm",
|
2008-03-13 13:35:09 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
2008-03-18 03:24:28 -06:00
|
|
|
/* The PWRDN bit is apparently only available on 3430ES2 and above */
|
|
|
|
static struct clk dpll4_m2x2_ck = {
|
|
|
|
.name = "dpll4_m2x2_ck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &dpll4_m2_ck,
|
2008-03-18 03:24:28 -06:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
|
|
|
|
.enable_bit = OMAP3430_PWRDN_96M_SHIFT,
|
2009-01-31 03:05:51 -07:00
|
|
|
.flags = INVERT_ENABLE,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll4_clkdm",
|
2008-03-13 13:35:09 -06:00
|
|
|
.recalc = &omap3_clkoutx2_recalc,
|
|
|
|
};
|
|
|
|
|
2009-01-27 19:13:02 -07:00
|
|
|
/*
|
|
|
|
* DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
|
|
|
|
* PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
|
|
|
|
* 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
|
|
|
|
* CM_96K_(F)CLK.
|
|
|
|
*/
|
2008-03-18 03:24:28 -06:00
|
|
|
static struct clk omap_96m_alwon_fck = {
|
|
|
|
.name = "omap_96m_alwon_fck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &dpll4_m2x2_ck,
|
[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 06:29:22 -07:00
|
|
|
.recalc = &followparent_recalc,
|
2008-03-18 03:24:28 -06:00
|
|
|
};
|
|
|
|
|
2009-01-27 19:13:02 -07:00
|
|
|
static struct clk cm_96m_fck = {
|
|
|
|
.name = "cm_96m_fck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &omap_96m_alwon_fck,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2009-01-27 19:13:02 -07:00
|
|
|
static const struct clksel_rate omap_96m_dpll_rates[] = {
|
|
|
|
{ .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate omap_96m_sys_rates[] = {
|
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel omap_96m_fck_clksel[] = {
|
|
|
|
{ .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
|
|
|
|
{ .parent = &sys_ck, .rates = omap_96m_sys_rates },
|
2008-03-13 13:35:09 -06:00
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
2009-01-27 19:13:02 -07:00
|
|
|
static struct clk omap_96m_fck = {
|
|
|
|
.name = "omap_96m_fck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2009-01-27 19:13:02 -07:00
|
|
|
.parent = &sys_ck,
|
2008-03-13 13:35:09 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
2009-01-27 19:13:02 -07:00
|
|
|
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
|
|
|
|
.clksel_mask = OMAP3430_SOURCE_96M_MASK,
|
|
|
|
.clksel = omap_96m_fck_clksel,
|
2008-03-13 13:35:09 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* This virtual clock is the source for dpll4_m3x2_ck */
|
|
|
|
static struct clk dpll4_m3_ck = {
|
|
|
|
.name = "dpll4_m3_ck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &dpll4_ck,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_TV_MASK,
|
|
|
|
.clksel = div16_dpll4_clksel,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll4_clkdm",
|
2008-03-13 13:35:09 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
2008-03-18 03:24:28 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
/* The PWRDN bit is apparently only available on 3430ES2 and above */
|
|
|
|
static struct clk dpll4_m3x2_ck = {
|
|
|
|
.name = "dpll4_m3x2_ck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &dpll4_m3_ck,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
|
|
|
|
.enable_bit = OMAP3430_PWRDN_TV_SHIFT,
|
2009-01-31 03:05:51 -07:00
|
|
|
.flags = INVERT_ENABLE,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll4_clkdm",
|
2008-03-13 13:35:09 -06:00
|
|
|
.recalc = &omap3_clkoutx2_recalc,
|
|
|
|
};
|
|
|
|
|
2008-03-18 03:24:28 -06:00
|
|
|
static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
|
|
|
|
{ .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate omap_54m_alt_rates[] = {
|
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel omap_54m_clksel[] = {
|
[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 06:29:22 -07:00
|
|
|
{ .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
|
2008-03-18 03:24:28 -06:00
|
|
|
{ .parent = &sys_altclk, .rates = omap_54m_alt_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk omap_54m_fck = {
|
|
|
|
.name = "omap_54m_fck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
|
2009-01-27 19:13:02 -07:00
|
|
|
.clksel_mask = OMAP3430_SOURCE_54M_MASK,
|
2008-03-18 03:24:28 -06:00
|
|
|
.clksel = omap_54m_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
2009-01-27 19:13:02 -07:00
|
|
|
static const struct clksel_rate omap_48m_cm96m_rates[] = {
|
2008-03-18 03:24:28 -06:00
|
|
|
{ .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate omap_48m_alt_rates[] = {
|
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel omap_48m_clksel[] = {
|
2009-01-27 19:13:02 -07:00
|
|
|
{ .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
|
2008-03-18 03:24:28 -06:00
|
|
|
{ .parent = &sys_altclk, .rates = omap_48m_alt_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk omap_48m_fck = {
|
|
|
|
.name = "omap_48m_fck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
|
2009-01-27 19:13:02 -07:00
|
|
|
.clksel_mask = OMAP3430_SOURCE_48M_MASK,
|
2008-03-18 03:24:28 -06:00
|
|
|
.clksel = omap_48m_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk omap_12m_fck = {
|
|
|
|
.name = "omap_12m_fck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &omap_48m_fck,
|
|
|
|
.fixed_div = 4,
|
|
|
|
.recalc = &omap2_fixed_divisor_recalc,
|
|
|
|
};
|
|
|
|
|
2008-03-13 13:35:09 -06:00
|
|
|
/* This virstual clock is the source for dpll4_m4x2_ck */
|
|
|
|
static struct clk dpll4_m4_ck = {
|
|
|
|
.name = "dpll4_m4_ck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &dpll4_ck,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
|
|
|
|
.clksel = div16_dpll4_clksel,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll4_clkdm",
|
2008-03-13 13:35:09 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
2009-01-27 19:13:12 -07:00
|
|
|
.set_rate = &omap2_clksel_set_rate,
|
|
|
|
.round_rate = &omap2_clksel_round_rate,
|
2008-03-13 13:35:09 -06:00
|
|
|
};
|
|
|
|
|
2008-03-18 03:24:28 -06:00
|
|
|
/* The PWRDN bit is apparently only available on 3430ES2 and above */
|
|
|
|
static struct clk dpll4_m4x2_ck = {
|
|
|
|
.name = "dpll4_m4x2_ck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &dpll4_m4_ck,
|
2008-03-18 03:24:28 -06:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
|
|
|
|
.enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
|
2009-01-31 03:05:51 -07:00
|
|
|
.flags = INVERT_ENABLE,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll4_clkdm",
|
2008-03-13 13:35:09 -06:00
|
|
|
.recalc = &omap3_clkoutx2_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* This virtual clock is the source for dpll4_m5x2_ck */
|
|
|
|
static struct clk dpll4_m5_ck = {
|
|
|
|
.name = "dpll4_m5_ck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &dpll4_ck,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
|
|
|
|
.clksel = div16_dpll4_clksel,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* The PWRDN bit is apparently only available on 3430ES2 and above */
|
|
|
|
static struct clk dpll4_m5x2_ck = {
|
|
|
|
.name = "dpll4_m5x2_ck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &dpll4_m5_ck,
|
2008-03-18 03:24:28 -06:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
|
|
|
|
.enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
|
2009-01-31 03:05:51 -07:00
|
|
|
.flags = INVERT_ENABLE,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll4_clkdm",
|
2008-03-13 13:35:09 -06:00
|
|
|
.recalc = &omap3_clkoutx2_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* This virtual clock is the source for dpll4_m6x2_ck */
|
|
|
|
static struct clk dpll4_m6_ck = {
|
|
|
|
.name = "dpll4_m6_ck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &dpll4_ck,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
|
|
|
|
.clksel_mask = OMAP3430_DIV_DPLL4_MASK,
|
|
|
|
.clksel = div16_dpll4_clksel,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* The PWRDN bit is apparently only available on 3430ES2 and above */
|
|
|
|
static struct clk dpll4_m6x2_ck = {
|
|
|
|
.name = "dpll4_m6x2_ck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &dpll4_m6_ck,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
|
|
|
|
.enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
|
2009-01-31 03:05:51 -07:00
|
|
|
.flags = INVERT_ENABLE,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll4_clkdm",
|
2008-03-13 13:35:09 -06:00
|
|
|
.recalc = &omap3_clkoutx2_recalc,
|
2008-03-18 03:24:28 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk emu_per_alwon_ck = {
|
|
|
|
.name = "emu_per_alwon_ck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &dpll4_m6x2_ck,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* DPLL5 */
|
|
|
|
/* Supplies 120MHz clock, USIM source clock */
|
|
|
|
/* Type: DPLL */
|
|
|
|
/* 3430ES2 only */
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
static struct dpll_data dpll5_dd = {
|
2008-03-18 03:24:28 -06:00
|
|
|
.mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
|
|
|
|
.mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
|
|
|
|
.div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
|
[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 06:29:22 -07:00
|
|
|
.clk_bypass = &sys_ck,
|
|
|
|
.clk_ref = &sys_ck,
|
2009-01-27 19:12:47 -07:00
|
|
|
.freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
|
2008-03-18 03:24:28 -06:00
|
|
|
.control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
|
|
|
|
.enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
|
2008-07-03 03:24:45 -06:00
|
|
|
.modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
|
2008-03-18 03:24:28 -06:00
|
|
|
.auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
|
|
|
|
.recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
|
|
|
|
.recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
|
2008-07-03 03:24:45 -06:00
|
|
|
.autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
|
|
|
|
.autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
|
|
|
|
.idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
|
2009-01-28 12:08:17 -07:00
|
|
|
.idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
.max_multiplier = OMAP3_MAX_DPLL_MULT,
|
2009-01-28 12:08:44 -07:00
|
|
|
.min_divider = 1,
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
.max_divider = OMAP3_MAX_DPLL_DIV,
|
|
|
|
.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
|
2008-03-18 03:24:28 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk dpll5_ck = {
|
|
|
|
.name = "dpll5_ck",
|
2008-11-04 07:02:46 -07:00
|
|
|
.ops = &clkops_noncore_dpll_ops,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &sys_ck,
|
|
|
|
.dpll_data = &dpll5_dd,
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 03:24:46 -06:00
|
|
|
.round_rate = &omap2_dpll_round_rate,
|
2009-01-27 19:12:47 -07:00
|
|
|
.set_rate = &omap3_noncore_dpll_set_rate,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll5_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap3_dpll_recalc,
|
|
|
|
};
|
|
|
|
|
2008-03-13 13:35:09 -06:00
|
|
|
static const struct clksel div16_dpll5_clksel[] = {
|
2008-03-18 03:24:28 -06:00
|
|
|
{ .parent = &dpll5_ck, .rates = div16_dpll_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk dpll5_m2_ck = {
|
|
|
|
.name = "dpll5_m2_ck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &dpll5_ck,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
|
|
|
|
.clksel_mask = OMAP3430ES2_DIV_120M_MASK,
|
2008-03-13 13:35:09 -06:00
|
|
|
.clksel = div16_dpll5_clksel,
|
2009-01-27 19:44:18 -07:00
|
|
|
.clkdm_name = "dpll5_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* CM EXTERNAL CLOCK OUTPUTS */
|
|
|
|
|
|
|
|
static const struct clksel_rate clkout2_src_core_rates[] = {
|
|
|
|
{ .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate clkout2_src_sys_rates[] = {
|
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate clkout2_src_96m_rates[] = {
|
|
|
|
{ .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate clkout2_src_54m_rates[] = {
|
|
|
|
{ .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel clkout2_src_clksel[] = {
|
2009-01-27 19:13:02 -07:00
|
|
|
{ .parent = &core_ck, .rates = clkout2_src_core_rates },
|
|
|
|
{ .parent = &sys_ck, .rates = clkout2_src_sys_rates },
|
|
|
|
{ .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
|
|
|
|
{ .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
|
2008-03-18 03:24:28 -06:00
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk clkout2_src_ck = {
|
|
|
|
.name = "clkout2_src_ck",
|
[ARM] omap: don't use clkops_omap2_dflt_wait for non-ICLK/FCLK clocks
The original code in omap2_clk_wait_ready() used to check the low 8
bits to determine whether they were within the FCLKEN or ICLKEN
registers. Specifically, the test is satisfied when these offsets
are used:
CM_FCLKEN, CM_FCLKEN1, CM_CLKEN, OMAP24XX_CM_FCLKEN2, CM_ICLKEN,
CM_ICLKEN1, CM_ICLKEN2, CM_ICLKEN3, OMAP24XX_CM_ICLKEN4
OMAP3430_CM_CLKEN_PLL, OMAP3430ES2_CM_CLKEN2
If one of these offsets isn't used, omap2_clk_wait_ready() merely
returns without doing anything. So we should use the non-wait clkops
version instead and eliminate that conditional.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 14:24:00 -07:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP3430_CM_CLKOUT_CTRL,
|
|
|
|
.enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
|
|
|
|
.clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
|
|
|
|
.clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
|
|
|
|
.clksel = clkout2_src_clksel,
|
2008-05-07 19:19:07 -06:00
|
|
|
.clkdm_name = "core_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate sys_clkout2_rates[] = {
|
|
|
|
{ .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 2, .val = 1, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 4, .val = 2, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 8, .val = 3, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 16, .val = 4, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel sys_clkout2_clksel[] = {
|
|
|
|
{ .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
|
|
|
|
{ .parent = NULL },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk sys_clkout2 = {
|
|
|
|
.name = "sys_clkout2",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
|
|
|
|
.clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
|
|
|
|
.clksel = sys_clkout2_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* CM OUTPUT CLOCKS */
|
|
|
|
|
|
|
|
static struct clk corex2_fck = {
|
|
|
|
.name = "corex2_fck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &dpll3_m2x2_ck,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* DPLL power domain clock controls */
|
|
|
|
|
2009-01-28 12:08:14 -07:00
|
|
|
static const struct clksel_rate div4_rates[] = {
|
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 2, .val = 2, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 4, .val = 4, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel div4_core_clksel[] = {
|
|
|
|
{ .parent = &core_ck, .rates = div4_rates },
|
2008-03-18 03:24:28 -06:00
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
2008-03-13 13:35:09 -06:00
|
|
|
/*
|
|
|
|
* REVISIT: Are these in DPLL power domain or CM power domain? docs
|
|
|
|
* may be inconsistent here?
|
|
|
|
*/
|
2008-03-18 03:24:28 -06:00
|
|
|
static struct clk dpll1_fck = {
|
|
|
|
.name = "dpll1_fck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_ck,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
|
|
|
|
.clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
|
2009-01-28 12:08:14 -07:00
|
|
|
.clksel = div4_core_clksel,
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
2008-03-13 13:35:09 -06:00
|
|
|
static struct clk mpu_ck = {
|
|
|
|
.name = "mpu_ck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &dpll1_x2m2_ck,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "mpu_clkdm",
|
[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 06:29:22 -07:00
|
|
|
.recalc = &followparent_recalc,
|
2008-03-13 13:35:09 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
|
|
|
|
static const struct clksel_rate arm_fck_rates[] = {
|
|
|
|
{ .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 2, .val = 1, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel arm_fck_clksel[] = {
|
|
|
|
{ .parent = &mpu_ck, .rates = arm_fck_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk arm_fck = {
|
|
|
|
.name = "arm_fck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &mpu_ck,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
|
|
|
|
.clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
|
|
|
|
.clksel = arm_fck_clksel,
|
2009-09-03 11:14:00 -06:00
|
|
|
.clkdm_name = "mpu_clkdm",
|
2008-03-13 13:35:09 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
2008-08-19 02:08:45 -06:00
|
|
|
/* XXX What about neon_clkdm ? */
|
|
|
|
|
2008-03-13 13:35:09 -06:00
|
|
|
/*
|
|
|
|
* REVISIT: This clock is never specifically defined in the 3430 TRM,
|
|
|
|
* although it is referenced - so this is a guess
|
|
|
|
*/
|
|
|
|
static struct clk emu_mpu_alwon_ck = {
|
|
|
|
.name = "emu_mpu_alwon_ck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &mpu_ck,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2008-03-18 03:24:28 -06:00
|
|
|
static struct clk dpll2_fck = {
|
|
|
|
.name = "dpll2_fck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_ck,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
|
|
|
|
.clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
|
2009-01-28 12:08:14 -07:00
|
|
|
.clksel = div4_core_clksel,
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
2008-03-13 13:35:09 -06:00
|
|
|
static struct clk iva2_ck = {
|
|
|
|
.name = "iva2_ck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-13 13:35:09 -06:00
|
|
|
.parent = &dpll2_m2_ck,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
2008-04-01 01:11:22 -06:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "iva2_clkdm",
|
[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 06:29:22 -07:00
|
|
|
.recalc = &followparent_recalc,
|
2008-03-13 13:35:09 -06:00
|
|
|
};
|
|
|
|
|
2008-03-18 03:24:28 -06:00
|
|
|
/* Common interface clocks */
|
|
|
|
|
2009-01-28 12:08:14 -07:00
|
|
|
static const struct clksel div2_core_clksel[] = {
|
|
|
|
{ .parent = &core_ck, .rates = div2_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
2008-03-18 03:24:28 -06:00
|
|
|
static struct clk l3_ick = {
|
|
|
|
.name = "l3_ick",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_ck,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_L3_MASK,
|
|
|
|
.clksel = div2_core_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l3_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel div2_l3_clksel[] = {
|
|
|
|
{ .parent = &l3_ick, .rates = div2_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk l4_ick = {
|
|
|
|
.name = "l4_ick",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &l3_ick,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_L4_MASK,
|
|
|
|
.clksel = div2_l3_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel div2_l4_clksel[] = {
|
|
|
|
{ .parent = &l4_ick, .rates = div2_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk rm_ick = {
|
|
|
|
.name = "rm_ick",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &l4_ick,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_RM_MASK,
|
|
|
|
.clksel = div2_l4_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* GFX power domain */
|
|
|
|
|
2008-03-13 13:35:09 -06:00
|
|
|
/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
|
2008-03-18 03:24:28 -06:00
|
|
|
|
|
|
|
static const struct clksel gfx_l3_clksel[] = {
|
|
|
|
{ .parent = &l3_ick, .rates = gfx_l3_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
2008-08-19 02:08:45 -06:00
|
|
|
/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
|
|
|
|
static struct clk gfx_l3_ck = {
|
|
|
|
.name = "gfx_l3_ck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &l3_ick,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP_EN_GFX_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gfx_l3_fck = {
|
|
|
|
.name = "gfx_l3_fck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-08-19 02:08:45 -06:00
|
|
|
.parent = &gfx_l3_ck,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
2008-03-18 03:24:28 -06:00
|
|
|
.clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP_CLKSEL_GFX_MASK,
|
|
|
|
.clksel = gfx_l3_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "gfx_3430es1_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gfx_l3_ick = {
|
|
|
|
.name = "gfx_l3_ick",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-08-19 02:08:45 -06:00
|
|
|
.parent = &gfx_l3_ck,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "gfx_3430es1_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gfx_cg1_ck = {
|
|
|
|
.name = "gfx_cg1_ck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &gfx_l3_fck, /* REVISIT: correct? */
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430ES1_EN_2D_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "gfx_3430es1_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gfx_cg2_ck = {
|
|
|
|
.name = "gfx_cg2_ck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &gfx_l3_fck, /* REVISIT: correct? */
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430ES1_EN_3D_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "gfx_3430es1_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* SGX power domain - 3430ES2 only */
|
|
|
|
|
|
|
|
static const struct clksel_rate sgx_core_rates[] = {
|
|
|
|
{ .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 4, .val = 1, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 6, .val = 2, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate sgx_96m_rates[] = {
|
|
|
|
{ .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel sgx_clksel[] = {
|
|
|
|
{ .parent = &core_ck, .rates = sgx_core_rates },
|
|
|
|
{ .parent = &cm_96m_fck, .rates = sgx_96m_rates },
|
|
|
|
{ .parent = NULL },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk sgx_fck = {
|
|
|
|
.name = "sgx_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
|
2009-01-27 19:13:05 -07:00
|
|
|
.enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
|
2008-03-18 03:24:28 -06:00
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
|
|
|
|
.clksel = sgx_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "sgx_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk sgx_ick = {
|
|
|
|
.name = "sgx_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &l3_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
|
2009-01-27 19:13:05 -07:00
|
|
|
.enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "sgx_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* CORE power domain */
|
|
|
|
|
|
|
|
static struct clk d2d_26m_fck = {
|
|
|
|
.name = "d2d_26m_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &sys_ck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "d2d_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2009-04-28 16:27:44 -06:00
|
|
|
static struct clk modem_fck = {
|
|
|
|
.name = "modem_fck",
|
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
|
|
|
.parent = &sys_ck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MODEM_SHIFT,
|
|
|
|
.clkdm_name = "d2d_clkdm",
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk sad2d_ick = {
|
|
|
|
.name = "sad2d_ick",
|
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
|
|
|
.parent = &l3_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_SAD2D_SHIFT,
|
|
|
|
.clkdm_name = "d2d_clkdm",
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mad2d_ick = {
|
|
|
|
.name = "mad2d_ick",
|
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
|
|
|
.parent = &l3_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
|
|
|
|
.enable_bit = OMAP3430_EN_MAD2D_SHIFT,
|
|
|
|
.clkdm_name = "d2d_clkdm",
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2008-03-18 03:24:28 -06:00
|
|
|
static const struct clksel omap343x_gpt_clksel[] = {
|
|
|
|
{ .parent = &omap_32k_fck, .rates = gpt_32k_rates },
|
|
|
|
{ .parent = &sys_ck, .rates = gpt_sys_rates },
|
|
|
|
{ .parent = NULL}
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt10_fck = {
|
|
|
|
.name = "gpt10_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &sys_ck,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT10_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
|
|
|
|
.clksel = omap343x_gpt_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt11_fck = {
|
|
|
|
.name = "gpt11_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &sys_ck,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT11_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
|
|
|
|
.clksel = omap343x_gpt_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk cpefuse_fck = {
|
|
|
|
.name = "cpefuse_fck",
|
[ARM] omap: don't use clkops_omap2_dflt_wait for non-ICLK/FCLK clocks
The original code in omap2_clk_wait_ready() used to check the low 8
bits to determine whether they were within the FCLKEN or ICLKEN
registers. Specifically, the test is satisfied when these offsets
are used:
CM_FCLKEN, CM_FCLKEN1, CM_CLKEN, OMAP24XX_CM_FCLKEN2, CM_ICLKEN,
CM_ICLKEN1, CM_ICLKEN2, CM_ICLKEN3, OMAP24XX_CM_ICLKEN4
OMAP3430_CM_CLKEN_PLL, OMAP3430ES2_CM_CLKEN2
If one of these offsets isn't used, omap2_clk_wait_ready() merely
returns without doing anything. So we should use the non-wait clkops
version instead and eliminate that conditional.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 14:24:00 -07:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &sys_ck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
|
|
|
|
.enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk ts_fck = {
|
|
|
|
.name = "ts_fck",
|
[ARM] omap: don't use clkops_omap2_dflt_wait for non-ICLK/FCLK clocks
The original code in omap2_clk_wait_ready() used to check the low 8
bits to determine whether they were within the FCLKEN or ICLKEN
registers. Specifically, the test is satisfied when these offsets
are used:
CM_FCLKEN, CM_FCLKEN1, CM_CLKEN, OMAP24XX_CM_FCLKEN2, CM_ICLKEN,
CM_ICLKEN1, CM_ICLKEN2, CM_ICLKEN3, OMAP24XX_CM_ICLKEN4
OMAP3430_CM_CLKEN_PLL, OMAP3430ES2_CM_CLKEN2
If one of these offsets isn't used, omap2_clk_wait_ready() merely
returns without doing anything. So we should use the non-wait clkops
version instead and eliminate that conditional.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 14:24:00 -07:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &omap_32k_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
|
|
|
|
.enable_bit = OMAP3430ES2_EN_TS_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk usbtll_fck = {
|
|
|
|
.name = "usbtll_fck",
|
[ARM] omap: don't use clkops_omap2_dflt_wait for non-ICLK/FCLK clocks
The original code in omap2_clk_wait_ready() used to check the low 8
bits to determine whether they were within the FCLKEN or ICLKEN
registers. Specifically, the test is satisfied when these offsets
are used:
CM_FCLKEN, CM_FCLKEN1, CM_CLKEN, OMAP24XX_CM_FCLKEN2, CM_ICLKEN,
CM_ICLKEN1, CM_ICLKEN2, CM_ICLKEN3, OMAP24XX_CM_ICLKEN4
OMAP3430_CM_CLKEN_PLL, OMAP3430ES2_CM_CLKEN2
If one of these offsets isn't used, omap2_clk_wait_ready() merely
returns without doing anything. So we should use the non-wait clkops
version instead and eliminate that conditional.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 14:24:00 -07:00
|
|
|
.ops = &clkops_omap2_dflt,
|
[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 06:29:22 -07:00
|
|
|
.parent = &dpll5_m2_ck,
|
2008-03-18 03:24:28 -06:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
|
|
|
|
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* CORE 96M FCLK-derived clocks */
|
|
|
|
|
|
|
|
static struct clk core_96m_fck = {
|
|
|
|
.name = "core_96m_fck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &omap_96m_fck,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mmchs3_fck = {
|
|
|
|
.name = "mmchs_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-12-10 18:37:16 -07:00
|
|
|
.id = 2,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_96m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mmchs2_fck = {
|
|
|
|
.name = "mmchs_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-12-10 18:37:16 -07:00
|
|
|
.id = 1,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_96m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mspro_fck = {
|
|
|
|
.name = "mspro_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_96m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MSPRO_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mmchs1_fck = {
|
|
|
|
.name = "mmchs_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_96m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk i2c3_fck = {
|
|
|
|
.name = "i2c_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.id = 3,
|
|
|
|
.parent = &core_96m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk i2c2_fck = {
|
|
|
|
.name = "i2c_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-08-19 02:08:45 -06:00
|
|
|
.id = 2,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_96m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk i2c1_fck = {
|
|
|
|
.name = "i2c_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.id = 1,
|
|
|
|
.parent = &core_96m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
|
|
|
|
* MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
|
|
|
|
*/
|
|
|
|
static const struct clksel_rate common_mcbsp_96m_rates[] = {
|
|
|
|
{ .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
|
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel mcbsp_15_clksel[] = {
|
|
|
|
{ .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
|
|
|
|
{ .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcbsp5_fck = {
|
2008-07-03 03:24:40 -06:00
|
|
|
.name = "mcbsp_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-07-03 03:24:40 -06:00
|
|
|
.id = 5,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
|
|
|
|
.clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
|
|
|
|
.clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
|
|
|
|
.clksel = mcbsp_15_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcbsp1_fck = {
|
2008-07-03 03:24:40 -06:00
|
|
|
.name = "mcbsp_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-07-03 03:24:40 -06:00
|
|
|
.id = 1,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
|
|
|
|
.clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
|
|
|
|
.clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
|
|
|
|
.clksel = mcbsp_15_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* CORE_48M_FCK-derived clocks */
|
|
|
|
|
|
|
|
static struct clk core_48m_fck = {
|
|
|
|
.name = "core_48m_fck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &omap_48m_fck,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcspi4_fck = {
|
|
|
|
.name = "mcspi_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.id = 4,
|
|
|
|
.parent = &core_48m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcspi3_fck = {
|
|
|
|
.name = "mcspi_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.id = 3,
|
|
|
|
.parent = &core_48m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcspi2_fck = {
|
|
|
|
.name = "mcspi_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.id = 2,
|
|
|
|
.parent = &core_48m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcspi1_fck = {
|
|
|
|
.name = "mcspi_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.id = 1,
|
|
|
|
.parent = &core_48m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk uart2_fck = {
|
|
|
|
.name = "uart2_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_48m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_UART2_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk uart1_fck = {
|
|
|
|
.name = "uart1_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_48m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_UART1_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk fshostusb_fck = {
|
|
|
|
.name = "fshostusb_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_48m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* CORE_12M_FCK based clocks */
|
|
|
|
|
|
|
|
static struct clk core_12m_fck = {
|
|
|
|
.name = "core_12m_fck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &omap_12m_fck,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk hdq_fck = {
|
|
|
|
.name = "hdq_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_12m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_HDQ_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* DPLL3-derived clock */
|
|
|
|
|
|
|
|
static const struct clksel_rate ssi_ssr_corex2_rates[] = {
|
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 2, .val = 2, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 3, .val = 3, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 4, .val = 4, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 6, .val = 6, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 8, .val = 8, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 0 }
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel ssi_ssr_clksel[] = {
|
|
|
|
{ .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
|
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB
Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices. These devices are both interconnect
initiators and targets. Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:
Clock usbhost_48m_fck didn't enable in 100000 tries
Two bugs are fixed by this patch. First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips
should not wait for these clocks to enable. So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.
Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks. It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1]. Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.
This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].
In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.
Problem reported by Jarkko Nikula <jhnikula@gmail.com>:
http://marc.info/?l=linux-omap&m=124306184903679&w=2
...
1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
DSS case).
2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.
3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
2009-07-24 19:44:06 -06:00
|
|
|
static struct clk ssi_ssr_fck_3430es1 = {
|
2008-03-18 03:24:28 -06:00
|
|
|
.name = "ssi_ssr_fck",
|
2008-11-04 11:59:32 -07:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_SSI_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
|
|
|
|
.clksel = ssi_ssr_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB
Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices. These devices are both interconnect
initiators and targets. Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:
Clock usbhost_48m_fck didn't enable in 100000 tries
Two bugs are fixed by this patch. First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips
should not wait for these clocks to enable. So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.
Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks. It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1]. Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.
This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].
In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.
Problem reported by Jarkko Nikula <jhnikula@gmail.com>:
http://marc.info/?l=linux-omap&m=124306184903679&w=2
...
1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
DSS case).
2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.
3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
2009-07-24 19:44:06 -06:00
|
|
|
static struct clk ssi_ssr_fck_3430es2 = {
|
|
|
|
.name = "ssi_ssr_fck",
|
|
|
|
.ops = &clkops_omap3430es2_ssi_wait,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_SSI_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
|
|
|
|
.clksel = ssi_ssr_clksel,
|
|
|
|
.clkdm_name = "core_l4_clkdm",
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk ssi_sst_fck_3430es1 = {
|
2008-03-18 03:24:28 -06:00
|
|
|
.name = "ssi_sst_fck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB
Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices. These devices are both interconnect
initiators and targets. Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:
Clock usbhost_48m_fck didn't enable in 100000 tries
Two bugs are fixed by this patch. First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips
should not wait for these clocks to enable. So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.
Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks. It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1]. Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.
This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].
In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.
Problem reported by Jarkko Nikula <jhnikula@gmail.com>:
http://marc.info/?l=linux-omap&m=124306184903679&w=2
...
1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
DSS case).
2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.
3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
2009-07-24 19:44:06 -06:00
|
|
|
.parent = &ssi_ssr_fck_3430es1,
|
|
|
|
.fixed_div = 2,
|
|
|
|
.recalc = &omap2_fixed_divisor_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk ssi_sst_fck_3430es2 = {
|
|
|
|
.name = "ssi_sst_fck",
|
|
|
|
.ops = &clkops_null,
|
|
|
|
.parent = &ssi_ssr_fck_3430es2,
|
2008-03-18 03:24:28 -06:00
|
|
|
.fixed_div = 2,
|
|
|
|
.recalc = &omap2_fixed_divisor_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* CORE_L3_ICK based clocks */
|
|
|
|
|
2008-08-19 02:08:45 -06:00
|
|
|
/*
|
|
|
|
* XXX must add clk_enable/clk_disable for these if standard code won't
|
|
|
|
* handle it
|
|
|
|
*/
|
2008-03-18 03:24:28 -06:00
|
|
|
static struct clk core_l3_ick = {
|
|
|
|
.name = "core_l3_ick",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &l3_ick,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l3_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB
Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices. These devices are both interconnect
initiators and targets. Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:
Clock usbhost_48m_fck didn't enable in 100000 tries
Two bugs are fixed by this patch. First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips
should not wait for these clocks to enable. So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.
Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks. It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1]. Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.
This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].
In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.
Problem reported by Jarkko Nikula <jhnikula@gmail.com>:
http://marc.info/?l=linux-omap&m=124306184903679&w=2
...
1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
DSS case).
2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.
3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
2009-07-24 19:44:06 -06:00
|
|
|
static struct clk hsotgusb_ick_3430es1 = {
|
2008-03-18 03:24:28 -06:00
|
|
|
.name = "hsotgusb_ick",
|
OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB
Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices. These devices are both interconnect
initiators and targets. Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:
Clock usbhost_48m_fck didn't enable in 100000 tries
Two bugs are fixed by this patch. First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips
should not wait for these clocks to enable. So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.
Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks. It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1]. Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.
This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].
In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.
Problem reported by Jarkko Nikula <jhnikula@gmail.com>:
http://marc.info/?l=linux-omap&m=124306184903679&w=2
...
1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
DSS case).
2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.
3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
2009-07-24 19:44:06 -06:00
|
|
|
.ops = &clkops_omap2_dflt,
|
|
|
|
.parent = &core_l3_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
|
|
|
|
.clkdm_name = "core_l3_clkdm",
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk hsotgusb_ick_3430es2 = {
|
|
|
|
.name = "hsotgusb_ick",
|
|
|
|
.ops = &clkops_omap3430es2_hsotgusb_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l3_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l3_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk sdrc_ick = {
|
|
|
|
.name = "sdrc_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l3_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_SDRC_SHIFT,
|
2009-01-19 08:51:11 -07:00
|
|
|
.flags = ENABLE_ON_INIT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l3_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpmc_fck = {
|
|
|
|
.name = "gpmc_fck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l3_ick,
|
2009-01-19 08:51:11 -07:00
|
|
|
.flags = ENABLE_ON_INIT, /* huh? */
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l3_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* SECURITY_L3_ICK based clocks */
|
|
|
|
|
|
|
|
static struct clk security_l3_ick = {
|
|
|
|
.name = "security_l3_ick",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &l3_ick,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk pka_ick = {
|
|
|
|
.name = "pka_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &security_l3_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
|
|
|
|
.enable_bit = OMAP3430_EN_PKA_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* CORE_L4_ICK based clocks */
|
|
|
|
|
|
|
|
static struct clk core_l4_ick = {
|
|
|
|
.name = "core_l4_ick",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &l4_ick,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk usbtll_ick = {
|
|
|
|
.name = "usbtll_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
|
|
|
|
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mmchs3_ick = {
|
|
|
|
.name = "mmchs_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-12-10 18:37:16 -07:00
|
|
|
.id = 2,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Intersystem Communication Registers - chassis mode only */
|
|
|
|
static struct clk icr_ick = {
|
|
|
|
.name = "icr_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_ICR_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk aes2_ick = {
|
|
|
|
.name = "aes2_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_AES2_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk sha12_ick = {
|
|
|
|
.name = "sha12_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_SHA12_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk des2_ick = {
|
|
|
|
.name = "des2_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_DES2_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mmchs2_ick = {
|
|
|
|
.name = "mmchs_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-12-10 18:37:16 -07:00
|
|
|
.id = 1,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mmchs1_ick = {
|
|
|
|
.name = "mmchs_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mspro_ick = {
|
|
|
|
.name = "mspro_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MSPRO_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk hdq_ick = {
|
|
|
|
.name = "hdq_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_HDQ_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcspi4_ick = {
|
|
|
|
.name = "mcspi_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.id = 4,
|
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcspi3_ick = {
|
|
|
|
.name = "mcspi_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.id = 3,
|
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcspi2_ick = {
|
|
|
|
.name = "mcspi_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.id = 2,
|
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcspi1_ick = {
|
|
|
|
.name = "mcspi_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.id = 1,
|
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk i2c3_ick = {
|
|
|
|
.name = "i2c_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.id = 3,
|
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk i2c2_ick = {
|
|
|
|
.name = "i2c_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.id = 2,
|
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk i2c1_ick = {
|
|
|
|
.name = "i2c_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.id = 1,
|
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk uart2_ick = {
|
|
|
|
.name = "uart2_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_UART2_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk uart1_ick = {
|
|
|
|
.name = "uart1_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_UART1_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt11_ick = {
|
|
|
|
.name = "gpt11_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT11_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt10_ick = {
|
|
|
|
.name = "gpt10_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT10_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcbsp5_ick = {
|
2008-07-03 03:24:40 -06:00
|
|
|
.name = "mcbsp_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-07-03 03:24:40 -06:00
|
|
|
.id = 5,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcbsp1_ick = {
|
2008-07-03 03:24:40 -06:00
|
|
|
.name = "mcbsp_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-07-03 03:24:40 -06:00
|
|
|
.id = 1,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk fac_ick = {
|
|
|
|
.name = "fac_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mailboxes_ick = {
|
|
|
|
.name = "mailboxes_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk omapctrl_ick = {
|
|
|
|
.name = "omapctrl_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &core_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
|
2009-01-19 08:51:11 -07:00
|
|
|
.flags = ENABLE_ON_INIT,
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* SSI_L4_ICK based clocks */
|
|
|
|
|
|
|
|
static struct clk ssi_l4_ick = {
|
|
|
|
.name = "ssi_l4_ick",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &l4_ick,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB
Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices. These devices are both interconnect
initiators and targets. Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:
Clock usbhost_48m_fck didn't enable in 100000 tries
Two bugs are fixed by this patch. First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips
should not wait for these clocks to enable. So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.
Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks. It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1]. Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.
This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].
In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.
Problem reported by Jarkko Nikula <jhnikula@gmail.com>:
http://marc.info/?l=linux-omap&m=124306184903679&w=2
...
1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
DSS case).
2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.
3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
2009-07-24 19:44:06 -06:00
|
|
|
static struct clk ssi_ick_3430es1 = {
|
2008-03-18 03:24:28 -06:00
|
|
|
.name = "ssi_ick",
|
2008-11-04 11:59:32 -07:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &ssi_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_SSI_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB
Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices. These devices are both interconnect
initiators and targets. Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:
Clock usbhost_48m_fck didn't enable in 100000 tries
Two bugs are fixed by this patch. First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips
should not wait for these clocks to enable. So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.
Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks. It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1]. Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.
This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].
In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.
Problem reported by Jarkko Nikula <jhnikula@gmail.com>:
http://marc.info/?l=linux-omap&m=124306184903679&w=2
...
1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
DSS case).
2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.
3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
2009-07-24 19:44:06 -06:00
|
|
|
static struct clk ssi_ick_3430es2 = {
|
|
|
|
.name = "ssi_ick",
|
|
|
|
.ops = &clkops_omap3430es2_ssi_wait,
|
|
|
|
.parent = &ssi_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430_EN_SSI_SHIFT,
|
|
|
|
.clkdm_name = "core_l4_clkdm",
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2008-03-18 03:24:28 -06:00
|
|
|
/* REVISIT: Technically the TRM claims that this is CORE_CLK based,
|
|
|
|
* but l4_ick makes more sense to me */
|
|
|
|
|
|
|
|
static const struct clksel usb_l4_clksel[] = {
|
|
|
|
{ .parent = &l4_ick, .rates = div2_rates },
|
|
|
|
{ .parent = NULL },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk usb_l4_ick = {
|
|
|
|
.name = "usb_l4_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &l4_ick,
|
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
|
|
|
|
.enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
|
|
|
|
.clksel = usb_l4_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* SECURITY_L4_ICK2 based clocks */
|
|
|
|
|
|
|
|
static struct clk security_l4_ick2 = {
|
|
|
|
.name = "security_l4_ick2",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &l4_ick,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk aes1_ick = {
|
|
|
|
.name = "aes1_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &security_l4_ick2,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
|
|
|
|
.enable_bit = OMAP3430_EN_AES1_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk rng_ick = {
|
|
|
|
.name = "rng_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &security_l4_ick2,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
|
|
|
|
.enable_bit = OMAP3430_EN_RNG_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk sha11_ick = {
|
|
|
|
.name = "sha11_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &security_l4_ick2,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
|
|
|
|
.enable_bit = OMAP3430_EN_SHA11_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk des1_ick = {
|
|
|
|
.name = "des1_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &security_l4_ick2,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
|
|
|
|
.enable_bit = OMAP3430_EN_DES1_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* DSS */
|
OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB
Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices. These devices are both interconnect
initiators and targets. Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:
Clock usbhost_48m_fck didn't enable in 100000 tries
Two bugs are fixed by this patch. First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips
should not wait for these clocks to enable. So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.
Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks. It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1]. Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.
This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].
In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.
Problem reported by Jarkko Nikula <jhnikula@gmail.com>:
http://marc.info/?l=linux-omap&m=124306184903679&w=2
...
1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
DSS case).
2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.
3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
2009-07-24 19:44:06 -06:00
|
|
|
static struct clk dss1_alwon_fck_3430es1 = {
|
2008-03-18 03:24:28 -06:00
|
|
|
.name = "dss1_alwon_fck",
|
2008-11-04 11:59:32 -07:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &dpll4_m4x2_ck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_DSS1_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "dss_clkdm",
|
[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 06:29:22 -07:00
|
|
|
.recalc = &followparent_recalc,
|
2008-03-18 03:24:28 -06:00
|
|
|
};
|
|
|
|
|
OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB
Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices. These devices are both interconnect
initiators and targets. Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:
Clock usbhost_48m_fck didn't enable in 100000 tries
Two bugs are fixed by this patch. First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips
should not wait for these clocks to enable. So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.
Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks. It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1]. Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.
This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].
In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.
Problem reported by Jarkko Nikula <jhnikula@gmail.com>:
http://marc.info/?l=linux-omap&m=124306184903679&w=2
...
1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
DSS case).
2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.
3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
2009-07-24 19:44:06 -06:00
|
|
|
static struct clk dss1_alwon_fck_3430es2 = {
|
|
|
|
.name = "dss1_alwon_fck",
|
|
|
|
.ops = &clkops_omap3430es2_dss_usbhost_wait,
|
|
|
|
.parent = &dpll4_m4x2_ck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_DSS1_SHIFT,
|
|
|
|
.clkdm_name = "dss_clkdm",
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2008-03-18 03:24:28 -06:00
|
|
|
static struct clk dss_tv_fck = {
|
|
|
|
.name = "dss_tv_fck",
|
2008-11-04 11:59:32 -07:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &omap_54m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_TV_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "dss_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk dss_96m_fck = {
|
|
|
|
.name = "dss_96m_fck",
|
2008-11-04 11:59:32 -07:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &omap_96m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_TV_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "dss_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk dss2_alwon_fck = {
|
|
|
|
.name = "dss2_alwon_fck",
|
2008-11-04 11:59:32 -07:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &sys_ck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_DSS2_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "dss_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB
Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices. These devices are both interconnect
initiators and targets. Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:
Clock usbhost_48m_fck didn't enable in 100000 tries
Two bugs are fixed by this patch. First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips
should not wait for these clocks to enable. So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.
Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks. It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1]. Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.
This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].
In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.
Problem reported by Jarkko Nikula <jhnikula@gmail.com>:
http://marc.info/?l=linux-omap&m=124306184903679&w=2
...
1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
DSS case).
2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.
3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
2009-07-24 19:44:06 -06:00
|
|
|
static struct clk dss_ick_3430es1 = {
|
2008-03-18 03:24:28 -06:00
|
|
|
/* Handles both L3 and L4 clocks */
|
|
|
|
.name = "dss_ick",
|
2008-11-04 11:59:32 -07:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "dss_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB
Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices. These devices are both interconnect
initiators and targets. Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:
Clock usbhost_48m_fck didn't enable in 100000 tries
Two bugs are fixed by this patch. First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips
should not wait for these clocks to enable. So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.
Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks. It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1]. Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.
This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].
In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.
Problem reported by Jarkko Nikula <jhnikula@gmail.com>:
http://marc.info/?l=linux-omap&m=124306184903679&w=2
...
1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
DSS case).
2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.
3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
2009-07-24 19:44:06 -06:00
|
|
|
static struct clk dss_ick_3430es2 = {
|
|
|
|
/* Handles both L3 and L4 clocks */
|
|
|
|
.name = "dss_ick",
|
|
|
|
.ops = &clkops_omap3430es2_dss_usbhost_wait,
|
|
|
|
.parent = &l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
|
|
|
|
.clkdm_name = "dss_clkdm",
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2008-03-18 03:24:28 -06:00
|
|
|
/* CAM */
|
|
|
|
|
|
|
|
static struct clk cam_mclk = {
|
|
|
|
.name = "cam_mclk",
|
2009-04-23 21:11:07 -06:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &dpll4_m5x2_ck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_CAM_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "cam_clkdm",
|
[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 06:29:22 -07:00
|
|
|
.recalc = &followparent_recalc,
|
2008-03-18 03:24:28 -06:00
|
|
|
};
|
|
|
|
|
2008-08-19 02:08:45 -06:00
|
|
|
static struct clk cam_ick = {
|
|
|
|
/* Handles both L3 and L4 clocks */
|
|
|
|
.name = "cam_ick",
|
2009-04-23 21:11:07 -06:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_CAM_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "cam_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2009-01-27 19:13:09 -07:00
|
|
|
static struct clk csi2_96m_fck = {
|
|
|
|
.name = "csi2_96m_fck",
|
2009-04-23 21:11:07 -06:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2009-01-27 19:13:09 -07:00
|
|
|
.parent = &core_96m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_CSI2_SHIFT,
|
|
|
|
.clkdm_name = "cam_clkdm",
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2008-03-18 03:24:28 -06:00
|
|
|
/* USBHOST - 3430ES2 only */
|
|
|
|
|
|
|
|
static struct clk usbhost_120m_fck = {
|
|
|
|
.name = "usbhost_120m_fck",
|
OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB
Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices. These devices are both interconnect
initiators and targets. Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:
Clock usbhost_48m_fck didn't enable in 100000 tries
Two bugs are fixed by this patch. First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips
should not wait for these clocks to enable. So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.
Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks. It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1]. Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.
This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].
In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.
Problem reported by Jarkko Nikula <jhnikula@gmail.com>:
http://marc.info/?l=linux-omap&m=124306184903679&w=2
...
1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
DSS case).
2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.
3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
2009-07-24 19:44:06 -06:00
|
|
|
.ops = &clkops_omap2_dflt,
|
[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 06:29:22 -07:00
|
|
|
.parent = &dpll5_m2_ck,
|
2008-03-18 03:24:28 -06:00
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "usbhost_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk usbhost_48m_fck = {
|
|
|
|
.name = "usbhost_48m_fck",
|
OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB
Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices. These devices are both interconnect
initiators and targets. Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:
Clock usbhost_48m_fck didn't enable in 100000 tries
Two bugs are fixed by this patch. First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips
should not wait for these clocks to enable. So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.
Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks. It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1]. Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.
This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].
In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.
Problem reported by Jarkko Nikula <jhnikula@gmail.com>:
http://marc.info/?l=linux-omap&m=124306184903679&w=2
...
1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
DSS case).
2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.
3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
2009-07-24 19:44:06 -06:00
|
|
|
.ops = &clkops_omap3430es2_dss_usbhost_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &omap_48m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "usbhost_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2008-08-19 02:08:45 -06:00
|
|
|
static struct clk usbhost_ick = {
|
|
|
|
/* Handles both L3 and L4 clocks */
|
|
|
|
.name = "usbhost_ick",
|
OMAP3 clock: correct module IDLEST bits: SSI; DSS; USBHOST; HSOTGUSB
Fix two bugs in the OMAP3 clock tree pertaining to the SSI, DSS,
USBHOST, and HSOTGUSB devices. These devices are both interconnect
initiators and targets. Without this patch, clk_enable()s on clocks for
these modules can be very high latency (potentially up to ~200
milliseconds) and message such as the following are generated:
Clock usbhost_48m_fck didn't enable in 100000 tries
Two bugs are fixed by this patch. First, OMAP hardware only supports
target CM_IDLEST register bits on ES2+ chips and beyond. ES1 chips
should not wait for these clocks to enable. So, split the appropriate
clocks into ES1 and ES2+ variants, so that kernels running on ES1
devices won't try to wait.
Second, the current heuristic in omap2_clk_dflt_find_idlest() will
fail for these clocks. It assumes that the CM_IDLEST bit to wait upon
is the same as the CM_*CLKEN bit, which is false[1]. Fix by
implementing custom clkops .find_idlest function pointers for the
appropriate clocks that return the correct slave IDLEST bit shift.
This was originally fixed in the linux-omap kernel during 2.6.29 in a
slightly different manner[2][3].
In the medium-term future, all of the module IDLEST code will
eventually be moved to the omap_hwmod code.
Problem reported by Jarkko Nikula <jhnikula@gmail.com>:
http://marc.info/?l=linux-omap&m=124306184903679&w=2
...
1. See for example 34xx TRM Revision P Table 4-213 and 4-217 (for the
DSS case).
2. http://www.spinics.net/lists/linux-omap/msg05512.html et seq.
3. http://lkml.indiana.edu/hypermail/linux/kernel/0901.3/01498.html
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Jarkko Nikula <jhnikula@gmail.com>
2009-07-24 19:44:06 -06:00
|
|
|
.ops = &clkops_omap3430es2_dss_usbhost_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "usbhost_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* WKUP */
|
|
|
|
|
|
|
|
static const struct clksel_rate usim_96m_rates[] = {
|
|
|
|
{ .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 4, .val = 4, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 8, .val = 5, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 10, .val = 6, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate usim_120m_rates[] = {
|
|
|
|
{ .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 8, .val = 8, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 16, .val = 9, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 20, .val = 10, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel usim_clksel[] = {
|
|
|
|
{ .parent = &omap_96m_fck, .rates = usim_96m_rates },
|
[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 06:29:22 -07:00
|
|
|
{ .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
|
2008-03-18 03:24:28 -06:00
|
|
|
{ .parent = &sys_ck, .rates = div2_rates },
|
|
|
|
{ .parent = NULL },
|
|
|
|
};
|
|
|
|
|
|
|
|
/* 3430ES2 only */
|
|
|
|
static struct clk usim_fck = {
|
|
|
|
.name = "usim_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
|
|
|
|
.clksel = usim_clksel,
|
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
2008-08-19 02:08:45 -06:00
|
|
|
/* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
|
2008-03-18 03:24:28 -06:00
|
|
|
static struct clk gpt1_fck = {
|
|
|
|
.name = "gpt1_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT1_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
|
|
|
|
.clksel = omap343x_gpt_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk wkup_32k_fck = {
|
|
|
|
.name = "wkup_32k_fck",
|
2008-11-04 09:35:03 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &omap_32k_fck,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2008-12-10 18:35:24 -07:00
|
|
|
static struct clk gpio1_dbck = {
|
|
|
|
.name = "gpio1_dbck",
|
2009-05-11 10:58:19 -06:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &wkup_32k_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk wdt2_fck = {
|
|
|
|
.name = "wdt2_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &wkup_32k_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk wkup_l4_ick = {
|
|
|
|
.name = "wkup_l4_ick",
|
2008-11-04 09:35:03 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &sys_ck,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* 3430ES2 only */
|
|
|
|
/* Never specifically named in the TRM, so we have to infer a likely name */
|
|
|
|
static struct clk usim_ick = {
|
|
|
|
.name = "usim_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &wkup_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk wdt2_ick = {
|
|
|
|
.name = "wdt2_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &wkup_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk wdt1_ick = {
|
|
|
|
.name = "wdt1_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &wkup_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_WDT1_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpio1_ick = {
|
|
|
|
.name = "gpio1_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &wkup_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk omap_32ksync_ick = {
|
|
|
|
.name = "omap_32ksync_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &wkup_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2008-08-19 02:08:45 -06:00
|
|
|
/* XXX This clock no longer exists in 3430 TRM rev F */
|
2008-03-18 03:24:28 -06:00
|
|
|
static struct clk gpt12_ick = {
|
|
|
|
.name = "gpt12_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &wkup_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT12_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt1_ick = {
|
|
|
|
.name = "gpt1_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &wkup_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT1_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "wkup_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* PER clock domain */
|
|
|
|
|
|
|
|
static struct clk per_96m_fck = {
|
|
|
|
.name = "per_96m_fck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &omap_96m_alwon_fck,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk per_48m_fck = {
|
|
|
|
.name = "per_48m_fck",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &omap_48m_fck,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk uart3_fck = {
|
|
|
|
.name = "uart3_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_48m_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_UART3_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt2_fck = {
|
|
|
|
.name = "gpt2_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT2_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
|
|
|
|
.clksel = omap343x_gpt_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt3_fck = {
|
|
|
|
.name = "gpt3_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT3_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
|
|
|
|
.clksel = omap343x_gpt_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt4_fck = {
|
|
|
|
.name = "gpt4_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT4_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
|
|
|
|
.clksel = omap343x_gpt_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt5_fck = {
|
|
|
|
.name = "gpt5_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT5_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
|
|
|
|
.clksel = omap343x_gpt_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt6_fck = {
|
|
|
|
.name = "gpt6_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT6_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
|
|
|
|
.clksel = omap343x_gpt_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt7_fck = {
|
|
|
|
.name = "gpt7_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT7_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
|
|
|
|
.clksel = omap343x_gpt_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt8_fck = {
|
|
|
|
.name = "gpt8_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT8_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
|
|
|
|
.clksel = omap343x_gpt_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt9_fck = {
|
|
|
|
.name = "gpt9_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT9_SHIFT,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
|
|
|
|
.clksel = omap343x_gpt_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk per_32k_alwon_fck = {
|
|
|
|
.name = "per_32k_alwon_fck",
|
2008-11-04 09:35:03 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &omap_32k_fck,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2008-12-10 18:35:24 -07:00
|
|
|
static struct clk gpio6_dbck = {
|
|
|
|
.name = "gpio6_dbck",
|
2009-05-11 10:58:19 -06:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_32k_alwon_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
|
2008-03-28 06:57:50 -06:00
|
|
|
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2008-12-10 18:35:24 -07:00
|
|
|
static struct clk gpio5_dbck = {
|
|
|
|
.name = "gpio5_dbck",
|
2009-05-11 10:58:19 -06:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_32k_alwon_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
|
2008-03-28 06:57:50 -06:00
|
|
|
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2008-12-10 18:35:24 -07:00
|
|
|
static struct clk gpio4_dbck = {
|
|
|
|
.name = "gpio4_dbck",
|
2009-05-11 10:58:19 -06:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_32k_alwon_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
|
2008-03-28 06:57:50 -06:00
|
|
|
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2008-12-10 18:35:24 -07:00
|
|
|
static struct clk gpio3_dbck = {
|
|
|
|
.name = "gpio3_dbck",
|
2009-05-11 10:58:19 -06:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_32k_alwon_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
|
2008-03-28 06:57:50 -06:00
|
|
|
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
2008-12-10 18:35:24 -07:00
|
|
|
static struct clk gpio2_dbck = {
|
|
|
|
.name = "gpio2_dbck",
|
2009-05-11 10:58:19 -06:00
|
|
|
.ops = &clkops_omap2_dflt,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_32k_alwon_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
|
2008-03-28 06:57:50 -06:00
|
|
|
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk wdt3_fck = {
|
|
|
|
.name = "wdt3_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_32k_alwon_fck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_WDT3_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk per_l4_ick = {
|
|
|
|
.name = "per_l4_ick",
|
2008-11-04 09:48:35 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &l4_ick,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpio6_ick = {
|
|
|
|
.name = "gpio6_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpio5_ick = {
|
|
|
|
.name = "gpio5_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpio4_ick = {
|
|
|
|
.name = "gpio4_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpio3_ick = {
|
|
|
|
.name = "gpio3_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpio2_ick = {
|
|
|
|
.name = "gpio2_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk wdt3_ick = {
|
|
|
|
.name = "wdt3_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_WDT3_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk uart3_ick = {
|
|
|
|
.name = "uart3_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_UART3_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt9_ick = {
|
|
|
|
.name = "gpt9_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT9_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt8_ick = {
|
|
|
|
.name = "gpt8_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT8_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt7_ick = {
|
|
|
|
.name = "gpt7_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT7_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt6_ick = {
|
|
|
|
.name = "gpt6_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT6_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt5_ick = {
|
|
|
|
.name = "gpt5_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT5_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt4_ick = {
|
|
|
|
.name = "gpt4_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT4_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt3_ick = {
|
|
|
|
.name = "gpt3_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT3_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk gpt2_ick = {
|
|
|
|
.name = "gpt2_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_GPT2_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcbsp2_ick = {
|
2008-07-03 03:24:40 -06:00
|
|
|
.name = "mcbsp_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-07-03 03:24:40 -06:00
|
|
|
.id = 2,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcbsp3_ick = {
|
2008-07-03 03:24:40 -06:00
|
|
|
.name = "mcbsp_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-07-03 03:24:40 -06:00
|
|
|
.id = 3,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcbsp4_ick = {
|
2008-07-03 03:24:40 -06:00
|
|
|
.name = "mcbsp_ick",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-07-03 03:24:40 -06:00
|
|
|
.id = 4,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &per_l4_ick,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel mcbsp_234_clksel[] = {
|
2009-01-27 19:13:02 -07:00
|
|
|
{ .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
|
|
|
|
{ .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
|
2008-03-18 03:24:28 -06:00
|
|
|
{ .parent = NULL }
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcbsp2_fck = {
|
2008-07-03 03:24:40 -06:00
|
|
|
.name = "mcbsp_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-07-03 03:24:40 -06:00
|
|
|
.id = 2,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
|
|
|
|
.clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
|
|
|
|
.clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
|
|
|
|
.clksel = mcbsp_234_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcbsp3_fck = {
|
2008-07-03 03:24:40 -06:00
|
|
|
.name = "mcbsp_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-07-03 03:24:40 -06:00
|
|
|
.id = 3,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
|
|
|
|
.clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
|
|
|
|
.clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
|
|
|
|
.clksel = mcbsp_234_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk mcbsp4_fck = {
|
2008-07-03 03:24:40 -06:00
|
|
|
.name = "mcbsp_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-07-03 03:24:40 -06:00
|
|
|
.id = 4,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
|
|
|
|
.clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
|
|
|
|
.clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
|
|
|
|
.clksel = mcbsp_234_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "per_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* EMU clocks */
|
|
|
|
|
|
|
|
/* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
|
|
|
|
|
|
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static const struct clksel_rate emu_src_sys_rates[] = {
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{ .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
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{ .div = 0 },
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};
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static const struct clksel_rate emu_src_core_rates[] = {
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{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
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{ .div = 0 },
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};
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static const struct clksel_rate emu_src_per_rates[] = {
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{ .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
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{ .div = 0 },
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};
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static const struct clksel_rate emu_src_mpu_rates[] = {
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{ .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
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{ .div = 0 },
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};
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static const struct clksel emu_src_clksel[] = {
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{ .parent = &sys_ck, .rates = emu_src_sys_rates },
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{ .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
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{ .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
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{ .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
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{ .parent = NULL },
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};
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/*
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* Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
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* to switch the source of some of the EMU clocks.
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* XXX Are there CLKEN bits for these EMU clks?
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*/
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static struct clk emu_src_ck = {
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.name = "emu_src_ck",
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2008-11-04 09:35:03 -07:00
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.ops = &clkops_null,
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2008-03-18 03:24:28 -06:00
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.init = &omap2_init_clksel_parent,
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.clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
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.clksel_mask = OMAP3430_MUX_CTRL_MASK,
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.clksel = emu_src_clksel,
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2008-08-19 02:08:45 -06:00
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.clkdm_name = "emu_clkdm",
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2008-03-18 03:24:28 -06:00
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.recalc = &omap2_clksel_recalc,
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};
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static const struct clksel_rate pclk_emu_rates[] = {
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{ .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
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{ .div = 3, .val = 3, .flags = RATE_IN_343X },
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{ .div = 4, .val = 4, .flags = RATE_IN_343X },
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{ .div = 6, .val = 6, .flags = RATE_IN_343X },
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{ .div = 0 },
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};
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static const struct clksel pclk_emu_clksel[] = {
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{ .parent = &emu_src_ck, .rates = pclk_emu_rates },
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{ .parent = NULL },
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};
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static struct clk pclk_fck = {
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.name = "pclk_fck",
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2008-11-04 09:35:03 -07:00
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.ops = &clkops_null,
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2008-03-18 03:24:28 -06:00
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.init = &omap2_init_clksel_parent,
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.clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
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.clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
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.clksel = pclk_emu_clksel,
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2008-08-19 02:08:45 -06:00
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.clkdm_name = "emu_clkdm",
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2008-03-18 03:24:28 -06:00
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.recalc = &omap2_clksel_recalc,
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};
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static const struct clksel_rate pclkx2_emu_rates[] = {
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{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
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{ .div = 2, .val = 2, .flags = RATE_IN_343X },
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{ .div = 3, .val = 3, .flags = RATE_IN_343X },
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{ .div = 0 },
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};
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static const struct clksel pclkx2_emu_clksel[] = {
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{ .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
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{ .parent = NULL },
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|
|
};
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static struct clk pclkx2_fck = {
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.name = "pclkx2_fck",
|
2008-11-04 09:35:03 -07:00
|
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.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
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.init = &omap2_init_clksel_parent,
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|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
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|
|
.clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
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|
|
.clksel = pclkx2_emu_clksel,
|
2008-08-19 02:08:45 -06:00
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|
|
.clkdm_name = "emu_clkdm",
|
2008-03-18 03:24:28 -06:00
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|
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.recalc = &omap2_clksel_recalc,
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|
|
};
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static const struct clksel atclk_emu_clksel[] = {
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|
|
{ .parent = &emu_src_ck, .rates = div2_rates },
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|
|
{ .parent = NULL },
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|
|
|
};
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|
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static struct clk atclk_fck = {
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|
|
.name = "atclk_fck",
|
2008-11-04 09:35:03 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
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|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
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|
|
.clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
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|
|
.clksel = atclk_emu_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "emu_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
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|
|
|
|
|
static struct clk traceclk_src_fck = {
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|
|
|
.name = "traceclk_src_fck",
|
2008-11-04 09:35:03 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
|
|
|
|
.clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
|
|
|
|
.clksel = emu_src_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "emu_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel_rate traceclk_rates[] = {
|
|
|
|
{ .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
|
|
|
|
{ .div = 2, .val = 2, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 4, .val = 4, .flags = RATE_IN_343X },
|
|
|
|
{ .div = 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct clksel traceclk_clksel[] = {
|
|
|
|
{ .parent = &traceclk_src_fck, .rates = traceclk_rates },
|
|
|
|
{ .parent = NULL },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk traceclk_fck = {
|
|
|
|
.name = "traceclk_fck",
|
2008-11-04 09:35:03 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.init = &omap2_init_clksel_parent,
|
|
|
|
.clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
|
|
|
|
.clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
|
|
|
|
.clksel = traceclk_clksel,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "emu_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &omap2_clksel_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* SR clocks */
|
|
|
|
|
|
|
|
/* SmartReflex fclk (VDD1) */
|
|
|
|
static struct clk sr1_fck = {
|
|
|
|
.name = "sr1_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &sys_ck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_SR1_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* SmartReflex fclk (VDD2) */
|
|
|
|
static struct clk sr2_fck = {
|
|
|
|
.name = "sr2_fck",
|
2008-11-04 10:59:52 -07:00
|
|
|
.ops = &clkops_omap2_dflt_wait,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &sys_ck,
|
|
|
|
.enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
|
|
|
|
.enable_bit = OMAP3430_EN_SR2_SHIFT,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk sr_l4_ick = {
|
|
|
|
.name = "sr_l4_ick",
|
2008-11-04 09:35:03 -07:00
|
|
|
.ops = &clkops_null, /* RMK: missing? */
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &l4_ick,
|
2008-08-19 02:08:45 -06:00
|
|
|
.clkdm_name = "core_l4_clkdm",
|
2008-03-18 03:24:28 -06:00
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* SECURE_32K_FCK clocks */
|
|
|
|
|
|
|
|
static struct clk gpt12_fck = {
|
|
|
|
.name = "gpt12_fck",
|
2008-11-04 09:35:03 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &secure_32k_fck,
|
|
|
|
.recalc = &followparent_recalc,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct clk wdt1_fck = {
|
|
|
|
.name = "wdt1_fck",
|
2008-11-04 09:35:03 -07:00
|
|
|
.ops = &clkops_null,
|
2008-03-18 03:24:28 -06:00
|
|
|
.parent = &secure_32k_fck,
|
2009-01-19 08:51:11 -07:00
|
|
|
.recalc = &followparent_recalc,
|
2008-03-18 03:24:28 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
#endif
|