2010-05-21 14:26:39 -06:00
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/*
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* Copyright © 2008-2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Zou Nan hai <nanhai.zou@intel.com>
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* Xiang Hai hao<haihao.xiang@intel.com>
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drv.h"
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2010-05-20 19:08:55 -06:00
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#include "i915_drm.h"
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2010-05-21 14:26:39 -06:00
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#include "i915_trace.h"
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2010-09-19 07:40:43 -06:00
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#include "intel_drv.h"
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2010-05-21 14:26:39 -06:00
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2010-08-07 04:01:22 -06:00
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static u32 i915_gem_get_seqno(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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u32 seqno;
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seqno = dev_priv->next_seqno;
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/* reserve 0 for non-seqno */
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if (++dev_priv->next_seqno == 0)
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dev_priv->next_seqno = 1;
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return seqno;
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}
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2010-05-20 19:08:55 -06:00
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static void
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2010-10-27 05:18:21 -06:00
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render_ring_flush(struct intel_ring_buffer *ring,
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2010-09-19 10:53:44 -06:00
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u32 invalidate_domains,
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u32 flush_domains)
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2010-05-21 14:26:39 -06:00
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{
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2010-10-27 05:18:21 -06:00
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struct drm_device *dev = ring->dev;
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2010-08-07 04:01:22 -06:00
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drm_i915_private_t *dev_priv = dev->dev_private;
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u32 cmd;
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2010-05-21 14:26:39 -06:00
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#if WATCH_EXEC
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DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
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invalidate_domains, flush_domains);
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#endif
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2010-08-07 04:01:22 -06:00
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trace_i915_gem_request_flush(dev, dev_priv->next_seqno,
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2010-05-21 14:26:39 -06:00
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invalidate_domains, flush_domains);
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if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
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/*
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* read/write caches:
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*
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* I915_GEM_DOMAIN_RENDER is always invalidated, but is
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* only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
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* also flushed at 2d versus 3d pipeline switches.
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*
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* read-only caches:
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*
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* I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
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* MI_READ_FLUSH is set, and is always flushed on 965.
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*
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* I915_GEM_DOMAIN_COMMAND may not exist?
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*
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* I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
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* invalidated when MI_EXE_FLUSH is set.
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*
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* I915_GEM_DOMAIN_VERTEX, which exists on 965, is
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* invalidated with every MI_FLUSH.
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*
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* TLBs:
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*
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* On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
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* and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
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* I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
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* are flushed at any MI_FLUSH.
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*/
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cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
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if ((invalidate_domains|flush_domains) &
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I915_GEM_DOMAIN_RENDER)
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cmd &= ~MI_NO_WRITE_FLUSH;
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2010-09-16 17:32:17 -06:00
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if (INTEL_INFO(dev)->gen < 4) {
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2010-05-21 14:26:39 -06:00
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/*
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* On the 965, the sampler cache always gets flushed
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* and this bit is reserved.
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*/
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if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
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cmd |= MI_READ_FLUSH;
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}
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if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
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cmd |= MI_EXE_FLUSH;
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#if WATCH_EXEC
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DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
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#endif
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2010-10-27 05:18:21 -06:00
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intel_ring_begin(ring, 2);
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intel_ring_emit(ring, cmd);
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_advance(ring);
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2010-05-21 14:26:39 -06:00
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}
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2010-05-20 19:08:55 -06:00
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}
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2010-10-27 05:18:21 -06:00
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static void ring_write_tail(struct intel_ring_buffer *ring,
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2010-10-22 10:02:41 -06:00
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u32 value)
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2010-09-15 20:43:12 -06:00
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{
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2010-10-27 05:18:21 -06:00
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drm_i915_private_t *dev_priv = ring->dev->dev_private;
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2010-10-22 10:02:41 -06:00
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I915_WRITE_TAIL(ring, value);
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2010-09-15 20:43:12 -06:00
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}
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2010-10-27 05:18:21 -06:00
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u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
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2010-05-20 19:08:55 -06:00
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{
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2010-10-27 05:18:21 -06:00
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drm_i915_private_t *dev_priv = ring->dev->dev_private;
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u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
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2010-09-24 13:14:22 -06:00
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RING_ACTHD(ring->mmio_base) : ACTHD;
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2010-05-20 19:08:55 -06:00
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return I915_READ(acthd_reg);
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}
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2010-10-27 05:18:21 -06:00
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static int init_ring_common(struct intel_ring_buffer *ring)
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2010-05-20 19:08:55 -06:00
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{
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2010-10-27 05:18:21 -06:00
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drm_i915_private_t *dev_priv = ring->dev->dev_private;
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struct drm_i915_gem_object *obj_priv = to_intel_bo(ring->gem_object);
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2010-05-20 19:08:55 -06:00
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u32 head;
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/* Stop the ring if it's running. */
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2010-08-02 09:06:59 -06:00
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I915_WRITE_CTL(ring, 0);
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2010-08-02 09:06:23 -06:00
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I915_WRITE_HEAD(ring, 0);
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2010-10-27 05:18:21 -06:00
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ring->write_tail(ring, 0);
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2010-05-20 19:08:55 -06:00
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/* Initialize the ring. */
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2010-08-02 08:33:33 -06:00
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I915_WRITE_START(ring, obj_priv->gtt_offset);
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2010-08-02 09:06:23 -06:00
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head = I915_READ_HEAD(ring) & HEAD_ADDR;
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2010-05-20 19:08:55 -06:00
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/* G45 ring initialization fails to reset head to zero */
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if (head != 0) {
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DRM_ERROR("%s head not reset to zero "
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"ctl %08x head %08x tail %08x start %08x\n",
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ring->name,
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2010-08-02 09:06:59 -06:00
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I915_READ_CTL(ring),
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2010-08-02 09:06:23 -06:00
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I915_READ_HEAD(ring),
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2010-08-02 08:29:44 -06:00
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I915_READ_TAIL(ring),
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2010-08-02 08:33:33 -06:00
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I915_READ_START(ring));
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2010-05-20 19:08:55 -06:00
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2010-08-02 09:06:23 -06:00
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I915_WRITE_HEAD(ring, 0);
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2010-05-20 19:08:55 -06:00
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DRM_ERROR("%s head forced to zero "
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"ctl %08x head %08x tail %08x start %08x\n",
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ring->name,
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2010-08-02 09:06:59 -06:00
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I915_READ_CTL(ring),
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2010-08-02 09:06:23 -06:00
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I915_READ_HEAD(ring),
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2010-08-02 08:29:44 -06:00
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I915_READ_TAIL(ring),
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2010-08-02 08:33:33 -06:00
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I915_READ_START(ring));
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2010-05-20 19:08:55 -06:00
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}
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2010-08-02 09:06:59 -06:00
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I915_WRITE_CTL(ring,
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2010-05-20 19:08:55 -06:00
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((ring->gem_object->size - PAGE_SIZE) & RING_NR_PAGES)
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| RING_NO_REPORT | RING_VALID);
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2010-08-02 09:06:23 -06:00
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head = I915_READ_HEAD(ring) & HEAD_ADDR;
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2010-05-20 19:08:55 -06:00
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/* If the head is still not zero, the ring is dead */
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if (head != 0) {
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DRM_ERROR("%s initialization failed "
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"ctl %08x head %08x tail %08x start %08x\n",
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ring->name,
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2010-08-02 09:06:59 -06:00
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I915_READ_CTL(ring),
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2010-08-02 09:06:23 -06:00
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I915_READ_HEAD(ring),
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2010-08-02 08:29:44 -06:00
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I915_READ_TAIL(ring),
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2010-08-02 08:33:33 -06:00
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I915_READ_START(ring));
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2010-05-20 19:08:55 -06:00
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return -EIO;
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}
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2010-10-27 05:18:21 -06:00
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if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
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i915_kernel_lost_context(ring->dev);
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2010-05-20 19:08:55 -06:00
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else {
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2010-08-02 09:06:23 -06:00
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ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
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2010-08-02 08:29:44 -06:00
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ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
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2010-05-20 19:08:55 -06:00
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ring->space = ring->head - (ring->tail + 8);
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if (ring->space < 0)
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ring->space += ring->size;
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}
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return 0;
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}
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2010-10-27 05:18:21 -06:00
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static int init_render_ring(struct intel_ring_buffer *ring)
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2010-05-20 19:08:55 -06:00
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{
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2010-10-27 05:18:21 -06:00
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struct drm_device *dev = ring->dev;
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int ret = init_ring_common(ring);
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2010-08-30 02:12:42 -06:00
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2010-09-16 17:32:17 -06:00
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if (INTEL_INFO(dev)->gen > 3) {
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2010-10-27 05:18:21 -06:00
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drm_i915_private_t *dev_priv = dev->dev_private;
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int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
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2010-08-30 02:12:42 -06:00
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if (IS_GEN6(dev))
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mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
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I915_WRITE(MI_MODE, mode);
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2010-05-20 19:08:55 -06:00
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}
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2010-10-27 05:18:21 -06:00
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2010-05-20 19:08:55 -06:00
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return ret;
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}
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2010-10-27 05:18:21 -06:00
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#define PIPE_CONTROL_FLUSH(ring__, addr__) \
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2010-05-20 19:08:55 -06:00
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do { \
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2010-10-27 05:18:21 -06:00
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intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
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2010-05-26 20:26:42 -06:00
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PIPE_CONTROL_DEPTH_STALL | 2); \
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2010-10-27 05:18:21 -06:00
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intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
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intel_ring_emit(ring__, 0); \
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intel_ring_emit(ring__, 0); \
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2010-05-20 19:08:55 -06:00
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} while (0)
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2010-05-21 14:26:39 -06:00
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/**
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* Creates a new sequence number, emitting a write of it to the status page
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* plus an interrupt, which will trigger i915_user_interrupt_handler.
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*
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* Must be called with struct_lock held.
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*
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* Returned sequence numbers are nonzero on success.
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*/
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2010-05-20 19:08:55 -06:00
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static u32
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2010-10-27 05:18:21 -06:00
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render_ring_add_request(struct intel_ring_buffer *ring,
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2010-09-19 10:53:44 -06:00
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u32 flush_domains)
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2010-05-21 14:26:39 -06:00
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{
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2010-10-27 05:18:21 -06:00
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struct drm_device *dev = ring->dev;
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2010-05-21 14:26:39 -06:00
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drm_i915_private_t *dev_priv = dev->dev_private;
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2010-08-07 04:01:22 -06:00
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u32 seqno;
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seqno = i915_gem_get_seqno(dev);
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2010-05-26 20:26:42 -06:00
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if (IS_GEN6(dev)) {
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2010-10-27 05:18:21 -06:00
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intel_ring_begin(ring, 6);
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intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | 3);
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intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE |
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2010-05-26 20:26:42 -06:00
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PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_IS_FLUSH |
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PIPE_CONTROL_NOTIFY);
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2010-10-27 05:18:21 -06:00
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intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
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intel_ring_emit(ring, seqno);
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, 0);
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intel_ring_advance(ring);
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2010-05-26 20:26:42 -06:00
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} else if (HAS_PIPE_CONTROL(dev)) {
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2010-05-21 14:26:39 -06:00
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u32 scratch_addr = dev_priv->seqno_gfx_addr + 128;
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/*
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* Workaround qword write incoherence by flushing the
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* PIPE_NOTIFY buffers out to memory before requesting
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* an interrupt.
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*/
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2010-10-27 05:18:21 -06:00
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intel_ring_begin(ring, 32);
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intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
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2010-05-21 14:26:39 -06:00
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PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
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2010-10-27 05:18:21 -06:00
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intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
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intel_ring_emit(ring, seqno);
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intel_ring_emit(ring, 0);
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PIPE_CONTROL_FLUSH(ring, scratch_addr);
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2010-05-21 14:26:39 -06:00
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scratch_addr += 128; /* write to separate cachelines */
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2010-10-27 05:18:21 -06:00
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PIPE_CONTROL_FLUSH(ring, scratch_addr);
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2010-05-21 14:26:39 -06:00
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scratch_addr += 128;
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2010-10-27 05:18:21 -06:00
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PIPE_CONTROL_FLUSH(ring, scratch_addr);
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2010-05-21 14:26:39 -06:00
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scratch_addr += 128;
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2010-10-27 05:18:21 -06:00
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PIPE_CONTROL_FLUSH(ring, scratch_addr);
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2010-05-21 14:26:39 -06:00
|
|
|
scratch_addr += 128;
|
2010-10-27 05:18:21 -06:00
|
|
|
PIPE_CONTROL_FLUSH(ring, scratch_addr);
|
2010-05-21 14:26:39 -06:00
|
|
|
scratch_addr += 128;
|
2010-10-27 05:18:21 -06:00
|
|
|
PIPE_CONTROL_FLUSH(ring, scratch_addr);
|
|
|
|
intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
|
2010-05-21 14:26:39 -06:00
|
|
|
PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
|
|
|
|
PIPE_CONTROL_NOTIFY);
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
|
|
|
|
intel_ring_emit(ring, seqno);
|
|
|
|
intel_ring_emit(ring, 0);
|
|
|
|
intel_ring_advance(ring);
|
2010-05-21 14:26:39 -06:00
|
|
|
} else {
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_ring_begin(ring, 4);
|
|
|
|
intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
|
|
|
|
intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
|
|
|
|
intel_ring_emit(ring, seqno);
|
2010-05-21 14:26:39 -06:00
|
|
|
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_ring_emit(ring, MI_USER_INTERRUPT);
|
|
|
|
intel_ring_advance(ring);
|
2010-05-21 14:26:39 -06:00
|
|
|
}
|
|
|
|
return seqno;
|
|
|
|
}
|
|
|
|
|
2010-05-20 19:08:55 -06:00
|
|
|
static u32
|
2010-10-27 05:18:21 -06:00
|
|
|
render_ring_get_seqno(struct intel_ring_buffer *ring)
|
2010-05-20 19:08:55 -06:00
|
|
|
{
|
2010-10-27 05:18:21 -06:00
|
|
|
struct drm_device *dev = ring->dev;
|
2010-05-20 19:08:55 -06:00
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
if (HAS_PIPE_CONTROL(dev))
|
|
|
|
return ((volatile u32 *)(dev_priv->seqno_page))[0];
|
|
|
|
else
|
|
|
|
return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2010-10-27 05:18:21 -06:00
|
|
|
render_ring_get_user_irq(struct intel_ring_buffer *ring)
|
2010-05-21 14:26:39 -06:00
|
|
|
{
|
2010-10-27 05:18:21 -06:00
|
|
|
struct drm_device *dev = ring->dev;
|
2010-05-21 14:26:39 -06:00
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
|
2010-05-20 19:08:55 -06:00
|
|
|
if (dev->irq_enabled && (++ring->user_irq_refcount == 1)) {
|
2010-05-21 14:26:39 -06:00
|
|
|
if (HAS_PCH_SPLIT(dev))
|
|
|
|
ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
|
|
|
|
else
|
|
|
|
i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
|
|
|
|
}
|
|
|
|
|
2010-05-20 19:08:55 -06:00
|
|
|
static void
|
2010-10-27 05:18:21 -06:00
|
|
|
render_ring_put_user_irq(struct intel_ring_buffer *ring)
|
2010-05-21 14:26:39 -06:00
|
|
|
{
|
2010-10-27 05:18:21 -06:00
|
|
|
struct drm_device *dev = ring->dev;
|
2010-05-21 14:26:39 -06:00
|
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
|
2010-05-20 19:08:55 -06:00
|
|
|
BUG_ON(dev->irq_enabled && ring->user_irq_refcount <= 0);
|
|
|
|
if (dev->irq_enabled && (--ring->user_irq_refcount == 0)) {
|
2010-05-21 14:26:39 -06:00
|
|
|
if (HAS_PCH_SPLIT(dev))
|
|
|
|
ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
|
|
|
|
else
|
|
|
|
i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
|
|
|
|
}
|
|
|
|
|
2010-10-27 05:18:21 -06:00
|
|
|
void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
|
2010-05-20 19:08:55 -06:00
|
|
|
{
|
2010-10-27 05:18:21 -06:00
|
|
|
drm_i915_private_t *dev_priv = ring->dev->dev_private;
|
|
|
|
u32 mmio = IS_GEN6(ring->dev) ?
|
|
|
|
RING_HWS_PGA_GEN6(ring->mmio_base) :
|
|
|
|
RING_HWS_PGA(ring->mmio_base);
|
|
|
|
I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
|
|
|
|
POSTING_READ(mmio);
|
2010-05-20 19:08:55 -06:00
|
|
|
}
|
|
|
|
|
2010-09-19 10:53:44 -06:00
|
|
|
static void
|
2010-10-27 05:18:21 -06:00
|
|
|
bsd_ring_flush(struct intel_ring_buffer *ring,
|
|
|
|
u32 invalidate_domains,
|
|
|
|
u32 flush_domains)
|
2010-05-20 19:08:57 -06:00
|
|
|
{
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_ring_begin(ring, 2);
|
|
|
|
intel_ring_emit(ring, MI_FLUSH);
|
|
|
|
intel_ring_emit(ring, MI_NOOP);
|
|
|
|
intel_ring_advance(ring);
|
2010-05-20 19:08:57 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static u32
|
2010-10-27 05:18:21 -06:00
|
|
|
ring_add_request(struct intel_ring_buffer *ring,
|
2010-10-19 04:19:32 -06:00
|
|
|
u32 flush_domains)
|
2010-05-20 19:08:57 -06:00
|
|
|
{
|
|
|
|
u32 seqno;
|
2010-08-07 04:01:22 -06:00
|
|
|
|
2010-10-27 05:18:21 -06:00
|
|
|
seqno = i915_gem_get_seqno(ring->dev);
|
2010-08-07 04:01:22 -06:00
|
|
|
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_ring_begin(ring, 4);
|
|
|
|
intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
|
|
|
|
intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
|
|
|
|
intel_ring_emit(ring, seqno);
|
|
|
|
intel_ring_emit(ring, MI_USER_INTERRUPT);
|
|
|
|
intel_ring_advance(ring);
|
2010-05-20 19:08:57 -06:00
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno);
|
|
|
|
|
|
|
|
return seqno;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2010-10-27 05:18:21 -06:00
|
|
|
bsd_ring_get_user_irq(struct intel_ring_buffer *ring)
|
2010-05-20 19:08:57 -06:00
|
|
|
{
|
|
|
|
/* do nothing */
|
|
|
|
}
|
|
|
|
static void
|
2010-10-27 05:18:21 -06:00
|
|
|
bsd_ring_put_user_irq(struct intel_ring_buffer *ring)
|
2010-05-20 19:08:57 -06:00
|
|
|
{
|
|
|
|
/* do nothing */
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32
|
2010-10-27 05:18:21 -06:00
|
|
|
ring_status_page_get_seqno(struct intel_ring_buffer *ring)
|
2010-05-20 19:08:57 -06:00
|
|
|
{
|
|
|
|
return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2010-10-27 05:18:21 -06:00
|
|
|
ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
|
|
|
|
struct drm_i915_gem_execbuffer2 *exec,
|
|
|
|
struct drm_clip_rect *cliprects,
|
|
|
|
uint64_t exec_offset)
|
2010-05-20 19:08:57 -06:00
|
|
|
{
|
|
|
|
uint32_t exec_start;
|
2010-10-27 05:18:21 -06:00
|
|
|
|
2010-05-20 19:08:57 -06:00
|
|
|
exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
|
2010-10-27 05:18:21 -06:00
|
|
|
|
|
|
|
intel_ring_begin(ring, 2);
|
|
|
|
intel_ring_emit(ring,
|
|
|
|
MI_BATCH_BUFFER_START |
|
|
|
|
(2 << 6) |
|
|
|
|
MI_BATCH_NON_SECURE_I965);
|
|
|
|
intel_ring_emit(ring, exec_start);
|
|
|
|
intel_ring_advance(ring);
|
|
|
|
|
2010-05-20 19:08:57 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-05-20 19:08:55 -06:00
|
|
|
static int
|
2010-10-27 05:18:21 -06:00
|
|
|
render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
|
|
|
|
struct drm_i915_gem_execbuffer2 *exec,
|
|
|
|
struct drm_clip_rect *cliprects,
|
|
|
|
uint64_t exec_offset)
|
2010-05-21 14:26:39 -06:00
|
|
|
{
|
2010-10-27 05:18:21 -06:00
|
|
|
struct drm_device *dev = ring->dev;
|
2010-05-21 14:26:39 -06:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
int nbox = exec->num_cliprects;
|
|
|
|
int i = 0, count;
|
|
|
|
uint32_t exec_start, exec_len;
|
2010-10-27 05:18:21 -06:00
|
|
|
|
2010-05-21 14:26:39 -06:00
|
|
|
exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
|
|
|
|
exec_len = (uint32_t) exec->batch_len;
|
|
|
|
|
2010-08-07 04:01:22 -06:00
|
|
|
trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1);
|
2010-05-21 14:26:39 -06:00
|
|
|
|
|
|
|
count = nbox ? nbox : 1;
|
|
|
|
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
if (i < nbox) {
|
|
|
|
int ret = i915_emit_box(dev, cliprects, i,
|
|
|
|
exec->DR1, exec->DR4);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (IS_I830(dev) || IS_845G(dev)) {
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_ring_begin(ring, 4);
|
|
|
|
intel_ring_emit(ring, MI_BATCH_BUFFER);
|
|
|
|
intel_ring_emit(ring, exec_start | MI_BATCH_NON_SECURE);
|
|
|
|
intel_ring_emit(ring, exec_start + exec_len - 4);
|
|
|
|
intel_ring_emit(ring, 0);
|
2010-05-21 14:26:39 -06:00
|
|
|
} else {
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_ring_begin(ring, 2);
|
2010-09-16 17:32:17 -06:00
|
|
|
if (INTEL_INFO(dev)->gen >= 4) {
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_ring_emit(ring,
|
2010-05-20 19:08:55 -06:00
|
|
|
MI_BATCH_BUFFER_START | (2 << 6)
|
|
|
|
| MI_BATCH_NON_SECURE_I965);
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_ring_emit(ring, exec_start);
|
2010-05-21 14:26:39 -06:00
|
|
|
} else {
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_ring_emit(ring, MI_BATCH_BUFFER_START
|
2010-05-20 19:08:55 -06:00
|
|
|
| (2 << 6));
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_ring_emit(ring, exec_start |
|
2010-05-20 19:08:55 -06:00
|
|
|
MI_BATCH_NON_SECURE);
|
2010-05-21 14:26:39 -06:00
|
|
|
}
|
|
|
|
}
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_ring_advance(ring);
|
2010-05-21 14:26:39 -06:00
|
|
|
}
|
|
|
|
|
2010-10-21 07:57:17 -06:00
|
|
|
if (IS_G4X(dev) || IS_GEN5(dev)) {
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_ring_begin(ring, 2);
|
|
|
|
intel_ring_emit(ring, MI_FLUSH |
|
2010-06-24 23:40:24 -06:00
|
|
|
MI_NO_WRITE_FLUSH |
|
|
|
|
MI_INVALIDATE_ISP );
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_ring_emit(ring, MI_NOOP);
|
|
|
|
intel_ring_advance(ring);
|
2010-06-24 23:40:24 -06:00
|
|
|
}
|
2010-05-21 14:26:39 -06:00
|
|
|
/* XXX breadcrumb */
|
2010-06-24 23:40:24 -06:00
|
|
|
|
2010-05-21 14:26:39 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-10-27 05:18:21 -06:00
|
|
|
static void cleanup_status_page(struct intel_ring_buffer *ring)
|
2010-05-21 14:26:39 -06:00
|
|
|
{
|
2010-10-27 05:18:21 -06:00
|
|
|
drm_i915_private_t *dev_priv = ring->dev->dev_private;
|
2010-05-21 14:26:39 -06:00
|
|
|
struct drm_gem_object *obj;
|
|
|
|
struct drm_i915_gem_object *obj_priv;
|
|
|
|
|
2010-05-20 19:08:55 -06:00
|
|
|
obj = ring->status_page.obj;
|
|
|
|
if (obj == NULL)
|
2010-05-21 14:26:39 -06:00
|
|
|
return;
|
|
|
|
obj_priv = to_intel_bo(obj);
|
|
|
|
|
|
|
|
kunmap(obj_priv->pages[0]);
|
|
|
|
i915_gem_object_unpin(obj);
|
|
|
|
drm_gem_object_unreference(obj);
|
2010-05-20 19:08:55 -06:00
|
|
|
ring->status_page.obj = NULL;
|
2010-05-21 14:26:39 -06:00
|
|
|
|
|
|
|
memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
|
|
|
|
}
|
|
|
|
|
2010-10-27 05:18:21 -06:00
|
|
|
static int init_status_page(struct intel_ring_buffer *ring)
|
2010-05-21 14:26:39 -06:00
|
|
|
{
|
2010-10-27 05:18:21 -06:00
|
|
|
struct drm_device *dev = ring->dev;
|
2010-05-21 14:26:39 -06:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
struct drm_gem_object *obj;
|
|
|
|
struct drm_i915_gem_object *obj_priv;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
obj = i915_gem_alloc_object(dev, 4096);
|
|
|
|
if (obj == NULL) {
|
|
|
|
DRM_ERROR("Failed to allocate status page\n");
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
obj_priv = to_intel_bo(obj);
|
|
|
|
obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
|
|
|
|
|
|
|
|
ret = i915_gem_object_pin(obj, 4096);
|
|
|
|
if (ret != 0) {
|
|
|
|
goto err_unref;
|
|
|
|
}
|
|
|
|
|
2010-05-20 19:08:55 -06:00
|
|
|
ring->status_page.gfx_addr = obj_priv->gtt_offset;
|
|
|
|
ring->status_page.page_addr = kmap(obj_priv->pages[0]);
|
|
|
|
if (ring->status_page.page_addr == NULL) {
|
2010-05-21 14:26:39 -06:00
|
|
|
memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
|
|
|
|
goto err_unpin;
|
|
|
|
}
|
2010-05-20 19:08:55 -06:00
|
|
|
ring->status_page.obj = obj;
|
|
|
|
memset(ring->status_page.page_addr, 0, PAGE_SIZE);
|
2010-05-21 14:26:39 -06:00
|
|
|
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_ring_setup_status_page(ring);
|
2010-05-20 19:08:55 -06:00
|
|
|
DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
|
|
|
|
ring->name, ring->status_page.gfx_addr);
|
2010-05-21 14:26:39 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_unpin:
|
|
|
|
i915_gem_object_unpin(obj);
|
|
|
|
err_unref:
|
|
|
|
drm_gem_object_unreference(obj);
|
|
|
|
err:
|
2010-05-20 19:08:55 -06:00
|
|
|
return ret;
|
2010-05-21 14:26:39 -06:00
|
|
|
}
|
|
|
|
|
2010-05-20 19:08:55 -06:00
|
|
|
int intel_init_ring_buffer(struct drm_device *dev,
|
2010-09-19 10:53:44 -06:00
|
|
|
struct intel_ring_buffer *ring)
|
2010-05-21 14:26:39 -06:00
|
|
|
{
|
2010-08-02 08:29:44 -06:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-05-20 19:08:55 -06:00
|
|
|
struct drm_i915_gem_object *obj_priv;
|
|
|
|
struct drm_gem_object *obj;
|
2010-08-07 04:01:34 -06:00
|
|
|
int ret;
|
|
|
|
|
2010-05-20 19:08:55 -06:00
|
|
|
ring->dev = dev;
|
2010-09-29 09:10:57 -06:00
|
|
|
INIT_LIST_HEAD(&ring->active_list);
|
|
|
|
INIT_LIST_HEAD(&ring->request_list);
|
2010-10-24 05:38:05 -06:00
|
|
|
INIT_LIST_HEAD(&ring->gpu_write_list);
|
2010-05-21 14:26:39 -06:00
|
|
|
|
2010-05-20 19:08:55 -06:00
|
|
|
if (I915_NEED_GFX_HWS(dev)) {
|
2010-10-27 05:18:21 -06:00
|
|
|
ret = init_status_page(ring);
|
2010-05-20 19:08:55 -06:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
2010-05-21 14:26:39 -06:00
|
|
|
|
2010-05-20 19:08:55 -06:00
|
|
|
obj = i915_gem_alloc_object(dev, ring->size);
|
2010-05-21 14:26:39 -06:00
|
|
|
if (obj == NULL) {
|
|
|
|
DRM_ERROR("Failed to allocate ringbuffer\n");
|
2010-05-20 19:08:55 -06:00
|
|
|
ret = -ENOMEM;
|
2010-08-07 04:01:34 -06:00
|
|
|
goto err_hws;
|
2010-05-21 14:26:39 -06:00
|
|
|
}
|
|
|
|
|
2010-05-20 19:08:55 -06:00
|
|
|
ring->gem_object = obj;
|
|
|
|
|
2010-08-02 09:22:48 -06:00
|
|
|
ret = i915_gem_object_pin(obj, PAGE_SIZE);
|
2010-08-07 04:01:34 -06:00
|
|
|
if (ret)
|
|
|
|
goto err_unref;
|
2010-05-21 14:26:39 -06:00
|
|
|
|
2010-05-20 19:08:55 -06:00
|
|
|
obj_priv = to_intel_bo(obj);
|
|
|
|
ring->map.size = ring->size;
|
2010-05-21 14:26:39 -06:00
|
|
|
ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
|
|
|
|
ring->map.type = 0;
|
|
|
|
ring->map.flags = 0;
|
|
|
|
ring->map.mtrr = 0;
|
|
|
|
|
|
|
|
drm_core_ioremap_wc(&ring->map, dev);
|
|
|
|
if (ring->map.handle == NULL) {
|
|
|
|
DRM_ERROR("Failed to map ringbuffer.\n");
|
2010-05-20 19:08:55 -06:00
|
|
|
ret = -EINVAL;
|
2010-08-07 04:01:34 -06:00
|
|
|
goto err_unpin;
|
2010-05-21 14:26:39 -06:00
|
|
|
}
|
|
|
|
|
2010-05-20 19:08:55 -06:00
|
|
|
ring->virtual_start = ring->map.handle;
|
2010-10-27 05:18:21 -06:00
|
|
|
ret = ring->init(ring);
|
2010-08-07 04:01:34 -06:00
|
|
|
if (ret)
|
|
|
|
goto err_unmap;
|
2010-05-21 14:26:39 -06:00
|
|
|
|
|
|
|
if (!drm_core_check_feature(dev, DRIVER_MODESET))
|
|
|
|
i915_kernel_lost_context(dev);
|
|
|
|
else {
|
2010-08-02 09:06:23 -06:00
|
|
|
ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
|
2010-08-02 08:29:44 -06:00
|
|
|
ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
|
2010-05-21 14:26:39 -06:00
|
|
|
ring->space = ring->head - (ring->tail + 8);
|
|
|
|
if (ring->space < 0)
|
2010-05-20 19:08:55 -06:00
|
|
|
ring->space += ring->size;
|
2010-05-21 14:26:39 -06:00
|
|
|
}
|
2010-05-20 19:08:55 -06:00
|
|
|
return ret;
|
2010-08-07 04:01:34 -06:00
|
|
|
|
|
|
|
err_unmap:
|
|
|
|
drm_core_ioremapfree(&ring->map, dev);
|
|
|
|
err_unpin:
|
|
|
|
i915_gem_object_unpin(obj);
|
|
|
|
err_unref:
|
|
|
|
drm_gem_object_unreference(obj);
|
|
|
|
ring->gem_object = NULL;
|
|
|
|
err_hws:
|
2010-10-27 05:18:21 -06:00
|
|
|
cleanup_status_page(ring);
|
2010-05-20 19:08:55 -06:00
|
|
|
return ret;
|
2010-05-21 14:26:39 -06:00
|
|
|
}
|
|
|
|
|
2010-10-27 05:18:21 -06:00
|
|
|
void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
|
2010-05-21 14:26:39 -06:00
|
|
|
{
|
2010-05-20 19:08:55 -06:00
|
|
|
if (ring->gem_object == NULL)
|
2010-05-21 14:26:39 -06:00
|
|
|
return;
|
|
|
|
|
2010-10-27 05:18:21 -06:00
|
|
|
drm_core_ioremapfree(&ring->map, ring->dev);
|
2010-05-21 14:26:39 -06:00
|
|
|
|
2010-05-20 19:08:55 -06:00
|
|
|
i915_gem_object_unpin(ring->gem_object);
|
|
|
|
drm_gem_object_unreference(ring->gem_object);
|
|
|
|
ring->gem_object = NULL;
|
2010-10-27 05:18:21 -06:00
|
|
|
|
|
|
|
cleanup_status_page(ring);
|
2010-05-21 14:26:39 -06:00
|
|
|
}
|
|
|
|
|
2010-10-27 05:18:21 -06:00
|
|
|
static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
|
2010-05-21 14:26:39 -06:00
|
|
|
{
|
2010-05-20 19:08:55 -06:00
|
|
|
unsigned int *virt;
|
2010-05-21 14:26:39 -06:00
|
|
|
int rem;
|
2010-05-20 19:08:55 -06:00
|
|
|
rem = ring->size - ring->tail;
|
2010-05-21 14:26:39 -06:00
|
|
|
|
2010-05-20 19:08:55 -06:00
|
|
|
if (ring->space < rem) {
|
2010-10-27 05:18:21 -06:00
|
|
|
int ret = intel_wait_ring_buffer(ring, rem);
|
2010-05-21 14:26:39 -06:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-05-20 19:08:55 -06:00
|
|
|
virt = (unsigned int *)(ring->virtual_start + ring->tail);
|
2010-08-04 08:18:12 -06:00
|
|
|
rem /= 8;
|
|
|
|
while (rem--) {
|
2010-05-21 14:26:39 -06:00
|
|
|
*virt++ = MI_NOOP;
|
2010-08-04 08:18:12 -06:00
|
|
|
*virt++ = MI_NOOP;
|
|
|
|
}
|
2010-05-21 14:26:39 -06:00
|
|
|
|
2010-05-20 19:08:55 -06:00
|
|
|
ring->tail = 0;
|
2010-07-01 10:53:00 -06:00
|
|
|
ring->space = ring->head - 8;
|
2010-05-21 14:26:39 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-10-27 05:18:21 -06:00
|
|
|
int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
|
2010-05-21 14:26:39 -06:00
|
|
|
{
|
2010-10-27 05:18:21 -06:00
|
|
|
struct drm_device *dev = ring->dev;
|
2010-08-02 09:06:23 -06:00
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
2010-10-27 05:18:21 -06:00
|
|
|
unsigned long end;
|
2010-05-21 14:26:39 -06:00
|
|
|
|
|
|
|
trace_i915_ring_wait_begin (dev);
|
2010-05-20 19:08:55 -06:00
|
|
|
end = jiffies + 3 * HZ;
|
|
|
|
do {
|
2010-08-02 09:06:23 -06:00
|
|
|
ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
|
2010-05-21 14:26:39 -06:00
|
|
|
ring->space = ring->head - (ring->tail + 8);
|
|
|
|
if (ring->space < 0)
|
2010-05-20 19:08:55 -06:00
|
|
|
ring->space += ring->size;
|
2010-05-21 14:26:39 -06:00
|
|
|
if (ring->space >= n) {
|
2010-10-27 05:18:21 -06:00
|
|
|
trace_i915_ring_wait_end(dev);
|
2010-05-21 14:26:39 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev->primary->master) {
|
|
|
|
struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
|
|
|
|
if (master_priv->sarea_priv)
|
|
|
|
master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
|
|
|
|
}
|
2010-05-20 19:08:57 -06:00
|
|
|
|
2010-10-13 03:09:14 -06:00
|
|
|
msleep(1);
|
2010-05-20 19:08:55 -06:00
|
|
|
} while (!time_after(jiffies, end));
|
|
|
|
trace_i915_ring_wait_end (dev);
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
2010-05-21 14:26:39 -06:00
|
|
|
|
2010-10-27 05:18:21 -06:00
|
|
|
void intel_ring_begin(struct intel_ring_buffer *ring,
|
2010-09-19 10:53:44 -06:00
|
|
|
int num_dwords)
|
2010-05-20 19:08:55 -06:00
|
|
|
{
|
2010-06-12 03:40:24 -06:00
|
|
|
int n = 4*num_dwords;
|
2010-10-27 05:18:21 -06:00
|
|
|
|
2010-05-20 19:08:55 -06:00
|
|
|
if (unlikely(ring->tail + n > ring->size))
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_wrap_ring_buffer(ring);
|
|
|
|
|
2010-05-20 19:08:55 -06:00
|
|
|
if (unlikely(ring->space < n))
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_wait_ring_buffer(ring, n);
|
2010-08-04 08:18:13 -06:00
|
|
|
|
|
|
|
ring->space -= n;
|
2010-05-20 19:08:55 -06:00
|
|
|
}
|
2010-05-21 14:26:39 -06:00
|
|
|
|
2010-10-27 05:18:21 -06:00
|
|
|
void intel_ring_advance(struct intel_ring_buffer *ring)
|
2010-05-20 19:08:55 -06:00
|
|
|
{
|
2010-08-04 08:18:13 -06:00
|
|
|
ring->tail &= ring->size - 1;
|
2010-10-27 05:18:21 -06:00
|
|
|
ring->write_tail(ring, ring->tail);
|
2010-05-20 19:08:55 -06:00
|
|
|
}
|
2010-05-21 14:26:39 -06:00
|
|
|
|
2010-09-19 07:46:27 -06:00
|
|
|
static const struct intel_ring_buffer render_ring = {
|
2010-05-20 19:08:55 -06:00
|
|
|
.name = "render ring",
|
2010-09-18 04:02:01 -06:00
|
|
|
.id = RING_RENDER,
|
2010-08-02 08:24:01 -06:00
|
|
|
.mmio_base = RENDER_RING_BASE,
|
2010-05-20 19:08:55 -06:00
|
|
|
.size = 32 * PAGE_SIZE,
|
|
|
|
.init = init_render_ring,
|
2010-10-22 10:02:41 -06:00
|
|
|
.write_tail = ring_write_tail,
|
2010-05-20 19:08:55 -06:00
|
|
|
.flush = render_ring_flush,
|
|
|
|
.add_request = render_ring_add_request,
|
2010-09-24 09:02:42 -06:00
|
|
|
.get_seqno = render_ring_get_seqno,
|
2010-05-20 19:08:55 -06:00
|
|
|
.user_irq_get = render_ring_get_user_irq,
|
|
|
|
.user_irq_put = render_ring_put_user_irq,
|
2010-10-27 05:18:21 -06:00
|
|
|
.dispatch_execbuffer = render_ring_dispatch_execbuffer,
|
2010-05-20 19:08:55 -06:00
|
|
|
};
|
2010-05-20 19:08:57 -06:00
|
|
|
|
|
|
|
/* ring buffer for bit-stream decoder */
|
|
|
|
|
2010-09-19 07:46:27 -06:00
|
|
|
static const struct intel_ring_buffer bsd_ring = {
|
2010-05-20 19:08:57 -06:00
|
|
|
.name = "bsd ring",
|
2010-09-18 04:02:01 -06:00
|
|
|
.id = RING_BSD,
|
2010-08-02 08:24:01 -06:00
|
|
|
.mmio_base = BSD_RING_BASE,
|
2010-05-20 19:08:57 -06:00
|
|
|
.size = 32 * PAGE_SIZE,
|
2010-10-27 05:18:21 -06:00
|
|
|
.init = init_ring_common,
|
2010-10-22 10:02:41 -06:00
|
|
|
.write_tail = ring_write_tail,
|
2010-05-20 19:08:57 -06:00
|
|
|
.flush = bsd_ring_flush,
|
2010-10-19 04:19:32 -06:00
|
|
|
.add_request = ring_add_request,
|
|
|
|
.get_seqno = ring_status_page_get_seqno,
|
2010-05-20 19:08:57 -06:00
|
|
|
.user_irq_get = bsd_ring_get_user_irq,
|
|
|
|
.user_irq_put = bsd_ring_put_user_irq,
|
2010-10-27 05:18:21 -06:00
|
|
|
.dispatch_execbuffer = ring_dispatch_execbuffer,
|
2010-05-20 19:08:57 -06:00
|
|
|
};
|
2010-09-15 20:43:11 -06:00
|
|
|
|
2010-09-19 07:40:43 -06:00
|
|
|
|
2010-10-27 05:18:21 -06:00
|
|
|
static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
|
2010-10-22 10:02:41 -06:00
|
|
|
u32 value)
|
2010-09-19 07:40:43 -06:00
|
|
|
{
|
2010-10-27 05:18:21 -06:00
|
|
|
drm_i915_private_t *dev_priv = ring->dev->dev_private;
|
2010-09-19 07:40:43 -06:00
|
|
|
|
|
|
|
/* Every tail move must follow the sequence below */
|
|
|
|
I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
|
|
|
|
GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
|
|
|
|
GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
|
|
|
|
I915_WRITE(GEN6_BSD_RNCID, 0x0);
|
|
|
|
|
|
|
|
if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
|
|
|
|
GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
|
|
|
|
50))
|
|
|
|
DRM_ERROR("timed out waiting for IDLE Indicator\n");
|
|
|
|
|
2010-08-02 08:29:44 -06:00
|
|
|
I915_WRITE_TAIL(ring, value);
|
2010-09-19 07:40:43 -06:00
|
|
|
I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
|
|
|
|
GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
|
|
|
|
GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
|
|
|
|
}
|
|
|
|
|
2010-10-27 05:18:21 -06:00
|
|
|
static void gen6_ring_flush(struct intel_ring_buffer *ring,
|
2010-10-19 04:19:32 -06:00
|
|
|
u32 invalidate_domains,
|
|
|
|
u32 flush_domains)
|
2010-09-19 07:40:43 -06:00
|
|
|
{
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_ring_begin(ring, 4);
|
|
|
|
intel_ring_emit(ring, MI_FLUSH_DW);
|
|
|
|
intel_ring_emit(ring, 0);
|
|
|
|
intel_ring_emit(ring, 0);
|
|
|
|
intel_ring_emit(ring, 0);
|
|
|
|
intel_ring_advance(ring);
|
2010-09-19 07:40:43 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2010-10-27 05:18:21 -06:00
|
|
|
gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
|
|
|
|
struct drm_i915_gem_execbuffer2 *exec,
|
|
|
|
struct drm_clip_rect *cliprects,
|
|
|
|
uint64_t exec_offset)
|
2010-09-19 07:40:43 -06:00
|
|
|
{
|
|
|
|
uint32_t exec_start;
|
2010-09-19 10:53:44 -06:00
|
|
|
|
2010-09-19 07:40:43 -06:00
|
|
|
exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
|
2010-09-19 10:53:44 -06:00
|
|
|
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_ring_begin(ring, 2);
|
|
|
|
intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
|
2010-09-19 10:53:44 -06:00
|
|
|
/* bit0-7 is the length on GEN6+ */
|
2010-10-27 05:18:21 -06:00
|
|
|
intel_ring_emit(ring, exec_start);
|
|
|
|
intel_ring_advance(ring);
|
2010-09-19 10:53:44 -06:00
|
|
|
|
2010-09-19 07:40:43 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* ring buffer for Video Codec for Gen6+ */
|
2010-09-19 07:46:27 -06:00
|
|
|
static const struct intel_ring_buffer gen6_bsd_ring = {
|
2010-09-19 07:40:43 -06:00
|
|
|
.name = "gen6 bsd ring",
|
|
|
|
.id = RING_BSD,
|
2010-08-02 08:24:01 -06:00
|
|
|
.mmio_base = GEN6_BSD_RING_BASE,
|
2010-09-19 07:40:43 -06:00
|
|
|
.size = 32 * PAGE_SIZE,
|
2010-10-27 05:18:21 -06:00
|
|
|
.init = init_ring_common,
|
2010-10-22 10:02:41 -06:00
|
|
|
.write_tail = gen6_bsd_ring_write_tail,
|
2010-10-19 04:19:32 -06:00
|
|
|
.flush = gen6_ring_flush,
|
|
|
|
.add_request = ring_add_request,
|
|
|
|
.get_seqno = ring_status_page_get_seqno,
|
2010-09-19 07:40:43 -06:00
|
|
|
.user_irq_get = bsd_ring_get_user_irq,
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|
|
|
.user_irq_put = bsd_ring_put_user_irq,
|
2010-10-27 05:18:21 -06:00
|
|
|
.dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
|
2010-10-19 04:19:32 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
/* Blitter support (SandyBridge+) */
|
|
|
|
|
|
|
|
static void
|
2010-10-27 05:18:21 -06:00
|
|
|
blt_ring_get_user_irq(struct intel_ring_buffer *ring)
|
2010-10-19 04:19:32 -06:00
|
|
|
{
|
|
|
|
/* do nothing */
|
|
|
|
}
|
|
|
|
static void
|
2010-10-27 05:18:21 -06:00
|
|
|
blt_ring_put_user_irq(struct intel_ring_buffer *ring)
|
2010-10-19 04:19:32 -06:00
|
|
|
{
|
|
|
|
/* do nothing */
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct intel_ring_buffer gen6_blt_ring = {
|
|
|
|
.name = "blt ring",
|
|
|
|
.id = RING_BLT,
|
|
|
|
.mmio_base = BLT_RING_BASE,
|
|
|
|
.size = 32 * PAGE_SIZE,
|
|
|
|
.init = init_ring_common,
|
2010-10-22 10:02:41 -06:00
|
|
|
.write_tail = ring_write_tail,
|
2010-10-19 04:19:32 -06:00
|
|
|
.flush = gen6_ring_flush,
|
|
|
|
.add_request = ring_add_request,
|
|
|
|
.get_seqno = ring_status_page_get_seqno,
|
|
|
|
.user_irq_get = blt_ring_get_user_irq,
|
|
|
|
.user_irq_put = blt_ring_put_user_irq,
|
2010-10-27 05:18:21 -06:00
|
|
|
.dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
|
2010-09-19 07:40:43 -06:00
|
|
|
};
|
|
|
|
|
2010-09-15 20:43:11 -06:00
|
|
|
int intel_init_render_ring_buffer(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
dev_priv->render_ring = render_ring;
|
|
|
|
|
|
|
|
if (!I915_NEED_GFX_HWS(dev)) {
|
|
|
|
dev_priv->render_ring.status_page.page_addr
|
|
|
|
= dev_priv->status_page_dmah->vaddr;
|
|
|
|
memset(dev_priv->render_ring.status_page.page_addr,
|
|
|
|
0, PAGE_SIZE);
|
|
|
|
}
|
|
|
|
|
|
|
|
return intel_init_ring_buffer(dev, &dev_priv->render_ring);
|
|
|
|
}
|
|
|
|
|
|
|
|
int intel_init_bsd_ring_buffer(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
|
2010-09-19 07:40:43 -06:00
|
|
|
if (IS_GEN6(dev))
|
|
|
|
dev_priv->bsd_ring = gen6_bsd_ring;
|
|
|
|
else
|
|
|
|
dev_priv->bsd_ring = bsd_ring;
|
2010-09-15 20:43:11 -06:00
|
|
|
|
|
|
|
return intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
|
|
|
|
}
|
2010-10-19 04:19:32 -06:00
|
|
|
|
|
|
|
int intel_init_blt_ring_buffer(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
dev_priv->blt_ring = gen6_blt_ring;
|
|
|
|
|
|
|
|
return intel_init_ring_buffer(dev, &dev_priv->blt_ring);
|
|
|
|
}
|