2010-05-19 02:44:14 -06:00
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#ifndef _LINUX_XGIFB
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#define _LINUX_XGIFB
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2011-10-11 12:47:15 -06:00
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#include "vgatypes.h"
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#include "vb_struct.h"
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enum xgifb_display_type {
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XGIFB_DISP_NONE = 0,
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XGIFB_DISP_CRT,
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XGIFB_DISP_LCD,
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XGIFB_DISP_TV,
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};
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#define HASVB_NONE 0x00
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#define HASVB_301 0x01
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#define HASVB_LVDS 0x02
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#define HASVB_TRUMPION 0x04
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#define HASVB_LVDS_CHRONTEL 0x10
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#define HASVB_302 0x20
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#define HASVB_CHRONTEL 0x80
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enum XGI_CHIP_TYPE {
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XG40 = 32,
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XG42,
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XG20 = 48,
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XG21,
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XG27,
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};
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enum xgi_tvtype {
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TVMODE_NTSC = 0,
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TVMODE_PAL,
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TVMODE_HIVISION,
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TVTYPE_PALM,
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TVTYPE_PALN,
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TVTYPE_NTSCJ,
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TVMODE_TOTAL
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};
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enum xgi_tv_plug {
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TVPLUG_UNKNOWN = 0,
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TVPLUG_COMPOSITE = 1,
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TVPLUG_SVIDEO = 2,
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TVPLUG_COMPOSITE_AND_SVIDEO = 3,
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TVPLUG_SCART = 4,
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TVPLUG_YPBPR_525i = 5,
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TVPLUG_YPBPR_525P = 6,
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TVPLUG_YPBPR_750P = 7,
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TVPLUG_YPBPR_1080i = 8,
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TVPLUG_TOTAL
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};
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struct xgifb_video_info {
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struct fb_info *fb_info;
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struct xgi_hw_device_info hw_info;
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struct vb_device_info dev_info;
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int mode_idx;
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int rate_idx;
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2011-10-11 12:47:24 -06:00
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u32 pseudo_palette[17];
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int chip_id;
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unsigned int video_size;
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phys_addr_t video_base;
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void __iomem *video_vbase;
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phys_addr_t mmio_base;
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unsigned long mmio_size;
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void __iomem *mmio_vbase;
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unsigned long vga_base;
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unsigned long mtrr;
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int video_bpp;
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int video_cmap_len;
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int video_width;
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int video_height;
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int video_vwidth;
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int video_vheight;
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int org_x;
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int org_y;
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int video_linelength;
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unsigned int refresh_rate;
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enum xgifb_display_type display2; /* the second display output type */
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bool display2_force;
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unsigned char hasVB;
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unsigned char TV_type;
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unsigned char TV_plug;
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2011-12-05 15:10:45 -07:00
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struct XGI21_LVDSCapStruct lvds_data;
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enum XGI_CHIP_TYPE chip;
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unsigned char revision_id;
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unsigned short DstColor;
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unsigned long XGI310_AccelDepth;
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unsigned long CommandReg;
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unsigned int pcibus;
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unsigned int pcislot;
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unsigned int pcifunc;
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unsigned short subsysvendor;
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unsigned short subsysdevice;
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char reserved[236];
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};
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#endif
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