2008-01-30 05:31:51 -07:00
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/*
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* Copyright (C) 1994 Linus Torvalds
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*
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* Pentium III FXSR, SSE support
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* General FPU state handling cleanups
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* Gareth Hughes <gareth@valinux.com>, May 2000
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* x86-64 work by Andi Kleen 2002
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*/
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#ifndef _ASM_X86_I387_H
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#define _ASM_X86_I387_H
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#include <linux/sched.h>
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#include <linux/kernel_stat.h>
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#include <linux/regset.h>
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crypto: padlock - fix VIA PadLock instruction usage with irq_ts_save/restore()
Wolfgang Walter reported this oops on his via C3 using padlock for
AES-encryption:
##################################################################
BUG: unable to handle kernel NULL pointer dereference at 000001f0
IP: [<c01028c5>] __switch_to+0x30/0x117
*pde = 00000000
Oops: 0002 [#1] PREEMPT
Modules linked in:
Pid: 2071, comm: sleep Not tainted (2.6.26 #11)
EIP: 0060:[<c01028c5>] EFLAGS: 00010002 CPU: 0
EIP is at __switch_to+0x30/0x117
EAX: 00000000 EBX: c0493300 ECX: dc48dd00 EDX: c0493300
ESI: dc48dd00 EDI: c0493530 EBP: c04cff8c ESP: c04cff7c
DS: 007b ES: 007b FS: 0000 GS: 0033 SS: 0068
Process sleep (pid: 2071, ti=c04ce000 task=dc48dd00 task.ti=d2fe6000)
Stack: dc48df30 c0493300 00000000 00000000 d2fe7f44 c03b5b43 c04cffc8 00000046
c0131856 0000005a dc472d3c c0493300 c0493470 d983ae00 00002696 00000000
c0239f54 00000000 c04c4000 c04cffd8 c01025fe c04f3740 00049800 c04cffe0
Call Trace:
[<c03b5b43>] ? schedule+0x285/0x2ff
[<c0131856>] ? pm_qos_requirement+0x3c/0x53
[<c0239f54>] ? acpi_processor_idle+0x0/0x434
[<c01025fe>] ? cpu_idle+0x73/0x7f
[<c03a4dcd>] ? rest_init+0x61/0x63
=======================
Wolfgang also found out that adding kernel_fpu_begin() and kernel_fpu_end()
around the padlock instructions fix the oops.
Suresh wrote:
These padlock instructions though don't use/touch SSE registers, but it behaves
similar to other SSE instructions. For example, it might cause DNA faults
when cr0.ts is set. While this is a spurious DNA trap, it might cause
oops with the recent fpu code changes.
This is the code sequence that is probably causing this problem:
a) new app is getting exec'd and it is somewhere in between
start_thread() and flush_old_exec() in the load_xyz_binary()
b) At pont "a", task's fpu state (like TS_USEDFPU, used_math() etc) is
cleared.
c) Now we get an interrupt/softirq which starts using these encrypt/decrypt
routines in the network stack. This generates a math fault (as
cr0.ts is '1') which sets TS_USEDFPU and restores the math that is
in the task's xstate.
d) Return to exec code path, which does start_thread() which does
free_thread_xstate() and sets xstate pointer to NULL while
the TS_USEDFPU is still set.
e) At the next context switch from the new exec'd task to another task,
we have a scenarios where TS_USEDFPU is set but xstate pointer is null.
This can cause an oops during unlazy_fpu() in __switch_to()
Now:
1) This should happen with or with out pre-emption. Viro also encountered
similar problem with out CONFIG_PREEMPT.
2) kernel_fpu_begin() and kernel_fpu_end() will fix this problem, because
kernel_fpu_begin() will manually do a clts() and won't run in to the
situation of setting TS_USEDFPU in step "c" above.
3) This was working before the fpu changes, because its a spurious
math fault which doesn't corrupt any fpu/sse registers and the task's
math state was always in an allocated state.
With out the recent lazy fpu allocation changes, while we don't see oops,
there is a possible race still present in older kernels(for example,
while kernel is using kernel_fpu_begin() in some optimized clear/copy
page and an interrupt/softirq happens which uses these padlock
instructions generating DNA fault).
This is the failing scenario that existed even before the lazy fpu allocation
changes:
0. CPU's TS flag is set
1. kernel using FPU in some optimized copy routine and while doing
kernel_fpu_begin() takes an interrupt just before doing clts()
2. Takes an interrupt and ipsec uses padlock instruction. And we
take a DNA fault as TS flag is still set.
3. We handle the DNA fault and set TS_USEDFPU and clear cr0.ts
4. We complete the padlock routine
5. Go back to step-1, which resumes clts() in kernel_fpu_begin(), finishes
the optimized copy routine and does kernel_fpu_end(). At this point,
we have cr0.ts again set to '1' but the task's TS_USEFPU is stilll
set and not cleared.
6. Now kernel resumes its user operation. And at the next context
switch, kernel sees it has do a FP save as TS_USEDFPU is still set
and then will do a unlazy_fpu() in __switch_to(). unlazy_fpu()
will take a DNA fault, as cr0.ts is '1' and now, because we are
in __switch_to(), math_state_restore() will get confused and will
restore the next task's FP state and will save it in prev tasks's FP state.
Remember, in __switch_to() we are already on the stack of the next task
but take a DNA fault for the prev task.
This causes the fpu leakage.
Fix the padlock instruction usage by calling them inside the
context of new routines irq_ts_save/restore(), which clear/restore cr0.ts
manually in the interrupt context. This will not generate spurious DNA
in the context of the interrupt which will fix the oops encountered and
the possible FPU leakage issue.
Reported-and-bisected-by: Wolfgang Walter <wolfgang.walter@stwm.de>
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2008-08-13 06:02:26 -06:00
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#include <linux/hardirq.h>
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2008-02-04 08:47:58 -07:00
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#include <asm/asm.h>
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2008-01-30 05:31:51 -07:00
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#include <asm/processor.h>
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#include <asm/sigcontext.h>
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#include <asm/user.h>
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#include <asm/uaccess.h>
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extern void fpu_init(void);
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extern void mxcsr_feature_mask_init(void);
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2008-03-10 16:28:05 -06:00
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extern int init_fpu(struct task_struct *child);
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2008-01-30 05:31:51 -07:00
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extern asmlinkage void math_state_restore(void);
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2008-03-10 16:28:04 -06:00
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extern void init_thread_xstate(void);
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2008-01-30 05:31:51 -07:00
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extern user_regset_active_fn fpregs_active, xfpregs_active;
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extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
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extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;
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#ifdef CONFIG_IA32_EMULATION
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struct _fpstate_ia32;
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extern int save_i387_ia32(struct _fpstate_ia32 __user *buf);
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extern int restore_i387_ia32(struct _fpstate_ia32 __user *buf);
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#endif
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#ifdef CONFIG_X86_64
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/* Ignore delayed exceptions from user space */
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static inline void tolerant_fwait(void)
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{
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asm volatile("1: fwait\n"
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"2:\n"
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2008-03-23 02:02:18 -06:00
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_ASM_EXTABLE(1b, 2b));
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2008-01-30 05:31:51 -07:00
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}
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static inline int restore_fpu_checking(struct i387_fxsave_struct *fx)
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{
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int err;
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asm volatile("1: rex64/fxrstor (%[fx])\n\t"
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"2:\n"
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".section .fixup,\"ax\"\n"
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"3: movl $-1,%[err]\n"
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" jmp 2b\n"
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".previous\n"
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2008-03-23 02:02:18 -06:00
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_ASM_EXTABLE(1b, 3b)
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2008-01-30 05:31:51 -07:00
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: [err] "=r" (err)
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#if 0 /* See comment in __save_init_fpu() below. */
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: [fx] "r" (fx), "m" (*fx), "0" (0));
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#else
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: [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
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#endif
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return err;
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}
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#define X87_FSW_ES (1 << 7) /* Exception Summary */
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/* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
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is pending. Clear the x87 state here by setting it to fixed
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values. The kernel data segment can be sometimes 0 and sometimes
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new user value. Both should be ok.
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Use the PDA as safe address because it should be already in L1. */
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static inline void clear_fpu_state(struct i387_fxsave_struct *fx)
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{
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if (unlikely(fx->swd & X87_FSW_ES))
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2008-03-23 02:02:18 -06:00
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asm volatile("fnclex");
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2008-01-30 05:31:51 -07:00
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alternative_input(ASM_NOP8 ASM_NOP2,
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2008-03-23 02:02:18 -06:00
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" emms\n" /* clear stack tags */
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" fildl %%gs:0", /* load to clear state */
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X86_FEATURE_FXSAVE_LEAK);
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2008-01-30 05:31:51 -07:00
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}
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static inline int save_i387_checking(struct i387_fxsave_struct __user *fx)
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{
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int err;
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asm volatile("1: rex64/fxsave (%[fx])\n\t"
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"2:\n"
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".section .fixup,\"ax\"\n"
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"3: movl $-1,%[err]\n"
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" jmp 2b\n"
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".previous\n"
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2008-03-23 02:02:18 -06:00
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_ASM_EXTABLE(1b, 3b)
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2008-01-30 05:31:51 -07:00
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: [err] "=r" (err), "=m" (*fx)
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#if 0 /* See comment in __fxsave_clear() below. */
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: [fx] "r" (fx), "0" (0));
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#else
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: [fx] "cdaSDb" (fx), "0" (0));
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#endif
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2008-03-23 02:02:18 -06:00
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if (unlikely(err) &&
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__clear_user(fx, sizeof(struct i387_fxsave_struct)))
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2008-01-30 05:31:51 -07:00
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err = -EFAULT;
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/* No need to clear here because the caller clears USED_MATH */
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return err;
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}
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static inline void __save_init_fpu(struct task_struct *tsk)
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{
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/* Using "rex64; fxsave %0" is broken because, if the memory operand
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uses any extended registers for addressing, a second REX prefix
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will be generated (to the assembler, rex64 followed by semicolon
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is a separate instruction), and hence the 64-bitness is lost. */
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#if 0
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/* Using "fxsaveq %0" would be the ideal choice, but is only supported
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starting with gas 2.16. */
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__asm__ __volatile__("fxsaveq %0"
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2008-03-10 16:28:04 -06:00
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: "=m" (tsk->thread.xstate->fxsave));
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2008-01-30 05:31:51 -07:00
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#elif 0
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/* Using, as a workaround, the properly prefixed form below isn't
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accepted by any binutils version so far released, complaining that
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the same type of prefix is used twice if an extended register is
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needed for addressing (fix submitted to mainline 2005-11-21). */
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__asm__ __volatile__("rex64/fxsave %0"
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2008-03-10 16:28:04 -06:00
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: "=m" (tsk->thread.xstate->fxsave));
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2008-01-30 05:31:51 -07:00
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#else
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/* This, however, we can work around by forcing the compiler to select
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an addressing mode that doesn't require extended registers. */
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2008-03-10 16:28:04 -06:00
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__asm__ __volatile__("rex64/fxsave (%1)"
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: "=m" (tsk->thread.xstate->fxsave)
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: "cdaSDb" (&tsk->thread.xstate->fxsave));
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2008-01-30 05:31:51 -07:00
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#endif
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2008-03-10 16:28:04 -06:00
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clear_fpu_state(&tsk->thread.xstate->fxsave);
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2008-01-30 05:31:51 -07:00
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task_thread_info(tsk)->status &= ~TS_USEDFPU;
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}
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#else /* CONFIG_X86_32 */
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2008-05-23 17:26:37 -06:00
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extern void finit(void);
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2008-01-30 05:31:51 -07:00
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static inline void tolerant_fwait(void)
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{
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asm volatile("fnclex ; fwait");
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}
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static inline void restore_fpu(struct task_struct *tsk)
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{
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/*
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* The "nop" is needed to make the instructions the same
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* length.
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*/
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alternative_input(
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"nop ; frstor %1",
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"fxrstor %1",
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X86_FEATURE_FXSR,
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2008-03-10 16:28:04 -06:00
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"m" (tsk->thread.xstate->fxsave));
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2008-01-30 05:31:51 -07:00
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}
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/* We need a safe address that is cheap to find and that is already
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in L1 during context switch. The best choices are unfortunately
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different for UP and SMP */
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#ifdef CONFIG_SMP
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#define safe_address (__per_cpu_offset[0])
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#else
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#define safe_address (kstat_cpu(0).cpustat.user)
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#endif
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/*
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* These must be called with preempt disabled
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*/
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static inline void __save_init_fpu(struct task_struct *tsk)
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{
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/* Use more nops than strictly needed in case the compiler
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varies code */
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alternative_input(
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"fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
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"fxsave %[fx]\n"
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"bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
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X86_FEATURE_FXSR,
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2008-03-10 16:28:04 -06:00
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[fx] "m" (tsk->thread.xstate->fxsave),
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[fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
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2008-01-30 05:31:51 -07:00
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/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
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is pending. Clear the x87 state here by setting it to fixed
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values. safe_address is a random variable that should be in L1 */
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alternative_input(
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GENERIC_NOP8 GENERIC_NOP2,
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"emms\n\t" /* clear stack tags */
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"fildl %[addr]", /* set F?P to defined value */
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X86_FEATURE_FXSAVE_LEAK,
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[addr] "m" (safe_address));
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task_thread_info(tsk)->status &= ~TS_USEDFPU;
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}
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/*
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* Signal frame handlers...
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*/
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extern int save_i387(struct _fpstate __user *buf);
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extern int restore_i387(struct _fpstate __user *buf);
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#endif /* CONFIG_X86_64 */
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static inline void __unlazy_fpu(struct task_struct *tsk)
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{
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if (task_thread_info(tsk)->status & TS_USEDFPU) {
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__save_init_fpu(tsk);
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stts();
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} else
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tsk->fpu_counter = 0;
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}
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static inline void __clear_fpu(struct task_struct *tsk)
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{
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if (task_thread_info(tsk)->status & TS_USEDFPU) {
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tolerant_fwait();
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task_thread_info(tsk)->status &= ~TS_USEDFPU;
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stts();
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}
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}
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static inline void kernel_fpu_begin(void)
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{
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struct thread_info *me = current_thread_info();
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preempt_disable();
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if (me->status & TS_USEDFPU)
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__save_init_fpu(me->task);
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else
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clts();
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}
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static inline void kernel_fpu_end(void)
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{
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stts();
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preempt_enable();
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}
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|
|
crypto: padlock - fix VIA PadLock instruction usage with irq_ts_save/restore()
Wolfgang Walter reported this oops on his via C3 using padlock for
AES-encryption:
##################################################################
BUG: unable to handle kernel NULL pointer dereference at 000001f0
IP: [<c01028c5>] __switch_to+0x30/0x117
*pde = 00000000
Oops: 0002 [#1] PREEMPT
Modules linked in:
Pid: 2071, comm: sleep Not tainted (2.6.26 #11)
EIP: 0060:[<c01028c5>] EFLAGS: 00010002 CPU: 0
EIP is at __switch_to+0x30/0x117
EAX: 00000000 EBX: c0493300 ECX: dc48dd00 EDX: c0493300
ESI: dc48dd00 EDI: c0493530 EBP: c04cff8c ESP: c04cff7c
DS: 007b ES: 007b FS: 0000 GS: 0033 SS: 0068
Process sleep (pid: 2071, ti=c04ce000 task=dc48dd00 task.ti=d2fe6000)
Stack: dc48df30 c0493300 00000000 00000000 d2fe7f44 c03b5b43 c04cffc8 00000046
c0131856 0000005a dc472d3c c0493300 c0493470 d983ae00 00002696 00000000
c0239f54 00000000 c04c4000 c04cffd8 c01025fe c04f3740 00049800 c04cffe0
Call Trace:
[<c03b5b43>] ? schedule+0x285/0x2ff
[<c0131856>] ? pm_qos_requirement+0x3c/0x53
[<c0239f54>] ? acpi_processor_idle+0x0/0x434
[<c01025fe>] ? cpu_idle+0x73/0x7f
[<c03a4dcd>] ? rest_init+0x61/0x63
=======================
Wolfgang also found out that adding kernel_fpu_begin() and kernel_fpu_end()
around the padlock instructions fix the oops.
Suresh wrote:
These padlock instructions though don't use/touch SSE registers, but it behaves
similar to other SSE instructions. For example, it might cause DNA faults
when cr0.ts is set. While this is a spurious DNA trap, it might cause
oops with the recent fpu code changes.
This is the code sequence that is probably causing this problem:
a) new app is getting exec'd and it is somewhere in between
start_thread() and flush_old_exec() in the load_xyz_binary()
b) At pont "a", task's fpu state (like TS_USEDFPU, used_math() etc) is
cleared.
c) Now we get an interrupt/softirq which starts using these encrypt/decrypt
routines in the network stack. This generates a math fault (as
cr0.ts is '1') which sets TS_USEDFPU and restores the math that is
in the task's xstate.
d) Return to exec code path, which does start_thread() which does
free_thread_xstate() and sets xstate pointer to NULL while
the TS_USEDFPU is still set.
e) At the next context switch from the new exec'd task to another task,
we have a scenarios where TS_USEDFPU is set but xstate pointer is null.
This can cause an oops during unlazy_fpu() in __switch_to()
Now:
1) This should happen with or with out pre-emption. Viro also encountered
similar problem with out CONFIG_PREEMPT.
2) kernel_fpu_begin() and kernel_fpu_end() will fix this problem, because
kernel_fpu_begin() will manually do a clts() and won't run in to the
situation of setting TS_USEDFPU in step "c" above.
3) This was working before the fpu changes, because its a spurious
math fault which doesn't corrupt any fpu/sse registers and the task's
math state was always in an allocated state.
With out the recent lazy fpu allocation changes, while we don't see oops,
there is a possible race still present in older kernels(for example,
while kernel is using kernel_fpu_begin() in some optimized clear/copy
page and an interrupt/softirq happens which uses these padlock
instructions generating DNA fault).
This is the failing scenario that existed even before the lazy fpu allocation
changes:
0. CPU's TS flag is set
1. kernel using FPU in some optimized copy routine and while doing
kernel_fpu_begin() takes an interrupt just before doing clts()
2. Takes an interrupt and ipsec uses padlock instruction. And we
take a DNA fault as TS flag is still set.
3. We handle the DNA fault and set TS_USEDFPU and clear cr0.ts
4. We complete the padlock routine
5. Go back to step-1, which resumes clts() in kernel_fpu_begin(), finishes
the optimized copy routine and does kernel_fpu_end(). At this point,
we have cr0.ts again set to '1' but the task's TS_USEFPU is stilll
set and not cleared.
6. Now kernel resumes its user operation. And at the next context
switch, kernel sees it has do a FP save as TS_USEDFPU is still set
and then will do a unlazy_fpu() in __switch_to(). unlazy_fpu()
will take a DNA fault, as cr0.ts is '1' and now, because we are
in __switch_to(), math_state_restore() will get confused and will
restore the next task's FP state and will save it in prev tasks's FP state.
Remember, in __switch_to() we are already on the stack of the next task
but take a DNA fault for the prev task.
This causes the fpu leakage.
Fix the padlock instruction usage by calling them inside the
context of new routines irq_ts_save/restore(), which clear/restore cr0.ts
manually in the interrupt context. This will not generate spurious DNA
in the context of the interrupt which will fix the oops encountered and
the possible FPU leakage issue.
Reported-and-bisected-by: Wolfgang Walter <wolfgang.walter@stwm.de>
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2008-08-13 06:02:26 -06:00
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/*
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* Some instructions like VIA's padlock instructions generate a spurious
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* DNA fault but don't modify SSE registers. And these instructions
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* get used from interrupt context aswell. To prevent these kernel instructions
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* in interrupt context interact wrongly with other user/kernel fpu usage, we
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* should use them only in the context of irq_ts_save/restore()
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*/
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static inline int irq_ts_save(void)
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{
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/*
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* If we are in process context, we are ok to take a spurious DNA fault.
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* Otherwise, doing clts() in process context require pre-emption to
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* be disabled or some heavy lifting like kernel_fpu_begin()
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*/
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if (!in_interrupt())
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return 0;
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if (read_cr0() & X86_CR0_TS) {
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clts();
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return 1;
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}
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return 0;
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}
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static inline void irq_ts_restore(int TS_state)
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{
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if (TS_state)
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stts();
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}
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2008-01-30 05:31:51 -07:00
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#ifdef CONFIG_X86_64
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static inline void save_init_fpu(struct task_struct *tsk)
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{
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__save_init_fpu(tsk);
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stts();
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}
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#define unlazy_fpu __unlazy_fpu
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#define clear_fpu __clear_fpu
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#else /* CONFIG_X86_32 */
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/*
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* These disable preemption on their own and are safe
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*/
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static inline void save_init_fpu(struct task_struct *tsk)
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{
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preempt_disable();
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__save_init_fpu(tsk);
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stts();
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preempt_enable();
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}
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static inline void unlazy_fpu(struct task_struct *tsk)
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{
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preempt_disable();
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__unlazy_fpu(tsk);
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preempt_enable();
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}
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static inline void clear_fpu(struct task_struct *tsk)
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{
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preempt_disable();
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__clear_fpu(tsk);
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preempt_enable();
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}
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#endif /* CONFIG_X86_64 */
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/*
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* i387 state interaction
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*/
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static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
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{
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if (cpu_has_fxsr) {
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2008-03-10 16:28:04 -06:00
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return tsk->thread.xstate->fxsave.cwd;
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2008-01-30 05:31:51 -07:00
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} else {
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2008-04-16 02:27:53 -06:00
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return (unsigned short)tsk->thread.xstate->fsave.cwd;
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2008-01-30 05:31:51 -07:00
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}
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}
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static inline unsigned short get_fpu_swd(struct task_struct *tsk)
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{
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if (cpu_has_fxsr) {
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2008-03-10 16:28:04 -06:00
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return tsk->thread.xstate->fxsave.swd;
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2008-01-30 05:31:51 -07:00
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} else {
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2008-04-16 02:27:53 -06:00
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return (unsigned short)tsk->thread.xstate->fsave.swd;
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2008-01-30 05:31:51 -07:00
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}
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}
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static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
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{
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if (cpu_has_xmm) {
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2008-03-10 16:28:04 -06:00
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return tsk->thread.xstate->fxsave.mxcsr;
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2008-01-30 05:31:51 -07:00
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} else {
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return MXCSR_DEFAULT;
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}
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}
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#endif /* _ASM_X86_I387_H */
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