2005-04-16 16:20:36 -06:00
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/*
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* linux/arch/alpha/kernel/sys_marvel.c
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*
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* Marvel / IO7 support
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/core_marvel.h>
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#include <asm/hwrpb.h>
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#include <asm/tlbflush.h>
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#include "proto.h"
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#include "err_impl.h"
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#include "irq_impl.h"
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#include "pci_impl.h"
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#include "machvec_impl.h"
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#if NR_IRQS < MARVEL_NR_IRQS
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# error NR_IRQS < MARVEL_NR_IRQS !!!
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#endif
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/*
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* Interrupt handling.
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*/
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static void
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2006-10-08 07:36:08 -06:00
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io7_device_interrupt(unsigned long vector)
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2005-04-16 16:20:36 -06:00
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{
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unsigned int pid;
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unsigned int irq;
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/*
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* Vector is 0x800 + (interrupt)
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*
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* where (interrupt) is:
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*
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* ...16|15 14|13 4|3 0
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* -----+-----+--------+---
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* PE | 0 | irq | 0
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*
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* where (irq) is
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*
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* 0x0800 - 0x0ff0 - 0x0800 + (LSI id << 4)
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* 0x1000 - 0x2ff0 - 0x1000 + (MSI_DAT<8:0> << 4)
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*/
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pid = vector >> 16;
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irq = ((vector & 0xffff) - 0x800) >> 4;
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irq += 16; /* offset for legacy */
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irq &= MARVEL_IRQ_VEC_IRQ_MASK; /* not too many bits */
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irq |= pid << MARVEL_IRQ_VEC_PE_SHIFT; /* merge the pid */
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2006-10-08 07:36:08 -06:00
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handle_irq(irq, get_irq_regs());
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2005-04-16 16:20:36 -06:00
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}
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static volatile unsigned long *
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io7_get_irq_ctl(unsigned int irq, struct io7 **pio7)
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{
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volatile unsigned long *ctl;
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unsigned int pid;
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struct io7 *io7;
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pid = irq >> MARVEL_IRQ_VEC_PE_SHIFT;
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if (!(io7 = marvel_find_io7(pid))) {
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printk(KERN_ERR
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"%s for nonexistent io7 -- vec %x, pid %d\n",
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__FUNCTION__, irq, pid);
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return NULL;
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}
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irq &= MARVEL_IRQ_VEC_IRQ_MASK; /* isolate the vector */
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irq -= 16; /* subtract legacy bias */
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if (irq >= 0x180) {
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printk(KERN_ERR
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"%s for invalid irq -- pid %d adjusted irq %x\n",
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__FUNCTION__, pid, irq);
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return NULL;
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}
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ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */
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if (irq >= 0x80) /* MSI */
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ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr;
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if (pio7) *pio7 = io7;
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return ctl;
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}
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static void
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io7_enable_irq(unsigned int irq)
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{
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volatile unsigned long *ctl;
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struct io7 *io7;
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ctl = io7_get_irq_ctl(irq, &io7);
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if (!ctl || !io7) {
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printk(KERN_ERR "%s: get_ctl failed for irq %x\n",
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__FUNCTION__, irq);
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return;
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}
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spin_lock(&io7->irq_lock);
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*ctl |= 1UL << 24;
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mb();
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*ctl;
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spin_unlock(&io7->irq_lock);
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}
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static void
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io7_disable_irq(unsigned int irq)
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{
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volatile unsigned long *ctl;
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struct io7 *io7;
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ctl = io7_get_irq_ctl(irq, &io7);
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if (!ctl || !io7) {
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printk(KERN_ERR "%s: get_ctl failed for irq %x\n",
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__FUNCTION__, irq);
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return;
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}
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spin_lock(&io7->irq_lock);
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*ctl &= ~(1UL << 24);
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mb();
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*ctl;
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spin_unlock(&io7->irq_lock);
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}
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static unsigned int
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io7_startup_irq(unsigned int irq)
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{
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io7_enable_irq(irq);
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return 0; /* never anything pending */
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}
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static void
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io7_end_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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io7_enable_irq(irq);
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}
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static void
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marvel_irq_noop(unsigned int irq)
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{
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return;
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}
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static unsigned int
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marvel_irq_noop_return(unsigned int irq)
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{
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return 0;
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}
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static struct hw_interrupt_type marvel_legacy_irq_type = {
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.typename = "LEGACY",
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.startup = marvel_irq_noop_return,
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.shutdown = marvel_irq_noop,
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.enable = marvel_irq_noop,
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.disable = marvel_irq_noop,
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.ack = marvel_irq_noop,
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.end = marvel_irq_noop,
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};
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static struct hw_interrupt_type io7_lsi_irq_type = {
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.typename = "LSI",
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.startup = io7_startup_irq,
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.shutdown = io7_disable_irq,
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.enable = io7_enable_irq,
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.disable = io7_disable_irq,
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.ack = io7_disable_irq,
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.end = io7_end_irq,
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};
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static struct hw_interrupt_type io7_msi_irq_type = {
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.typename = "MSI",
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.startup = io7_startup_irq,
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.shutdown = io7_disable_irq,
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.enable = io7_enable_irq,
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.disable = io7_disable_irq,
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.ack = marvel_irq_noop,
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.end = io7_end_irq,
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};
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static void
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io7_redirect_irq(struct io7 *io7,
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volatile unsigned long *csr,
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unsigned int where)
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{
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unsigned long val;
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val = *csr;
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val &= ~(0x1ffUL << 24); /* clear the target pid */
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val |= ((unsigned long)where << 24); /* set the new target pid */
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*csr = val;
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mb();
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*csr;
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}
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static void
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io7_redirect_one_lsi(struct io7 *io7, unsigned int which, unsigned int where)
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{
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unsigned long val;
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/*
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* LSI_CTL has target PID @ 14
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*/
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val = io7->csrs->PO7_LSI_CTL[which].csr;
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val &= ~(0x1ffUL << 14); /* clear the target pid */
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val |= ((unsigned long)where << 14); /* set the new target pid */
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io7->csrs->PO7_LSI_CTL[which].csr = val;
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mb();
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io7->csrs->PO7_LSI_CTL[which].csr;
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}
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static void
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io7_redirect_one_msi(struct io7 *io7, unsigned int which, unsigned int where)
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{
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unsigned long val;
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/*
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* MSI_CTL has target PID @ 14
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*/
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val = io7->csrs->PO7_MSI_CTL[which].csr;
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val &= ~(0x1ffUL << 14); /* clear the target pid */
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val |= ((unsigned long)where << 14); /* set the new target pid */
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io7->csrs->PO7_MSI_CTL[which].csr = val;
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mb();
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io7->csrs->PO7_MSI_CTL[which].csr;
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}
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static void __init
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init_one_io7_lsi(struct io7 *io7, unsigned int which, unsigned int where)
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{
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/*
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* LSI_CTL has target PID @ 14
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*/
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io7->csrs->PO7_LSI_CTL[which].csr = ((unsigned long)where << 14);
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mb();
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io7->csrs->PO7_LSI_CTL[which].csr;
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}
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static void __init
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init_one_io7_msi(struct io7 *io7, unsigned int which, unsigned int where)
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{
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/*
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* MSI_CTL has target PID @ 14
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*/
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io7->csrs->PO7_MSI_CTL[which].csr = ((unsigned long)where << 14);
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mb();
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io7->csrs->PO7_MSI_CTL[which].csr;
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}
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static void __init
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init_io7_irqs(struct io7 *io7,
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struct hw_interrupt_type *lsi_ops,
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struct hw_interrupt_type *msi_ops)
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{
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long base = (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT) + 16;
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long i;
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printk("Initializing interrupts for IO7 at PE %u - base %lx\n",
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io7->pe, base);
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/*
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* Where should interrupts from this IO7 go?
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*
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* They really should be sent to the local CPU to avoid having to
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* traverse the mesh, but if it's not an SMP kernel, they have to
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* go to the boot CPU. Send them all to the boot CPU for now,
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* as each secondary starts, it can redirect it's local device
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* interrupts.
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*/
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printk(" Interrupts reported to CPU at PE %u\n", boot_cpuid);
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spin_lock(&io7->irq_lock);
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/* set up the error irqs */
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io7_redirect_irq(io7, &io7->csrs->HLT_CTL.csr, boot_cpuid);
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io7_redirect_irq(io7, &io7->csrs->HPI_CTL.csr, boot_cpuid);
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io7_redirect_irq(io7, &io7->csrs->CRD_CTL.csr, boot_cpuid);
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io7_redirect_irq(io7, &io7->csrs->STV_CTL.csr, boot_cpuid);
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io7_redirect_irq(io7, &io7->csrs->HEI_CTL.csr, boot_cpuid);
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/* Set up the lsi irqs. */
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for (i = 0; i < 128; ++i) {
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irq_desc[base + i].status = IRQ_DISABLED | IRQ_LEVEL;
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[PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding
various abstractions and features to it, without impacting existing
functionality.
While the queue can be best described as "fix and improve everything in the
generic IRQ layer that we could think of", and thus it consists of many
smaller features and lots of cleanups, the one feature that stands out most is
the new 'irq chip' abstraction.
The irq-chip abstraction is about describing and coding and IRQ controller
driver by mapping its raw hardware capabilities [and quirks, if needed] in a
straightforward way, without having to think about "IRQ flow"
(level/edge/etc.) type of details.
This stands in contrast with the current 'irq-type' model of genirq
architectures, which 'mixes' raw hardware capabilities with 'flow' details.
The patchset supports both types of irq controller designs at once, and
converts i386 and x86_64 to the new irq-chip design.
As a bonus side-effect of the irq-chip approach, chained interrupt controllers
(master/slave PIC constructs, etc.) are now supported by design as well.
The end result of this patchset intends to be simpler architecture-level code
and more consolidation between architectures.
We reused many bits of code and many concepts from Russell King's ARM IRQ
layer, the merging of which was one of the motivations for this patchset.
This patch:
rename desc->handler to desc->chip.
Originally i did not want to do this, because it's a big patch. But having
both "desc->handler", "desc->handle_irq" and "action->handler" caused a
large degree of confusion and made the code appear alot less clean than it
truly is.
I have also attempted a dual approach as well by introducing a
desc->chip alias - but that just wasnt robust enough and broke
frequently.
So lets get over with this quickly. The conversion was done automatically
via scripts and converts all the code in the kernel.
This renaming patch is the first one amongst the patches, so that the
remaining patches can stay flexible and can be merged and split up
without having some big monolithic patch act as a merge barrier.
[akpm@osdl.org: build fix]
[akpm@osdl.org: another build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-29 03:24:36 -06:00
|
|
|
|
irq_desc[base + i].chip = lsi_ops;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Disable the implemented irqs in hardware. */
|
|
|
|
|
for (i = 0; i < 0x60; ++i)
|
|
|
|
|
init_one_io7_lsi(io7, i, boot_cpuid);
|
|
|
|
|
|
|
|
|
|
init_one_io7_lsi(io7, 0x74, boot_cpuid);
|
|
|
|
|
init_one_io7_lsi(io7, 0x75, boot_cpuid);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* Set up the msi irqs. */
|
|
|
|
|
for (i = 128; i < (128 + 512); ++i) {
|
|
|
|
|
irq_desc[base + i].status = IRQ_DISABLED | IRQ_LEVEL;
|
[PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding
various abstractions and features to it, without impacting existing
functionality.
While the queue can be best described as "fix and improve everything in the
generic IRQ layer that we could think of", and thus it consists of many
smaller features and lots of cleanups, the one feature that stands out most is
the new 'irq chip' abstraction.
The irq-chip abstraction is about describing and coding and IRQ controller
driver by mapping its raw hardware capabilities [and quirks, if needed] in a
straightforward way, without having to think about "IRQ flow"
(level/edge/etc.) type of details.
This stands in contrast with the current 'irq-type' model of genirq
architectures, which 'mixes' raw hardware capabilities with 'flow' details.
The patchset supports both types of irq controller designs at once, and
converts i386 and x86_64 to the new irq-chip design.
As a bonus side-effect of the irq-chip approach, chained interrupt controllers
(master/slave PIC constructs, etc.) are now supported by design as well.
The end result of this patchset intends to be simpler architecture-level code
and more consolidation between architectures.
We reused many bits of code and many concepts from Russell King's ARM IRQ
layer, the merging of which was one of the motivations for this patchset.
This patch:
rename desc->handler to desc->chip.
Originally i did not want to do this, because it's a big patch. But having
both "desc->handler", "desc->handle_irq" and "action->handler" caused a
large degree of confusion and made the code appear alot less clean than it
truly is.
I have also attempted a dual approach as well by introducing a
desc->chip alias - but that just wasnt robust enough and broke
frequently.
So lets get over with this quickly. The conversion was done automatically
via scripts and converts all the code in the kernel.
This renaming patch is the first one amongst the patches, so that the
remaining patches can stay flexible and can be merged and split up
without having some big monolithic patch act as a merge barrier.
[akpm@osdl.org: build fix]
[akpm@osdl.org: another build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-29 03:24:36 -06:00
|
|
|
|
irq_desc[base + i].chip = msi_ops;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < 16; ++i)
|
|
|
|
|
init_one_io7_msi(io7, i, boot_cpuid);
|
|
|
|
|
|
|
|
|
|
spin_unlock(&io7->irq_lock);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __init
|
|
|
|
|
marvel_init_irq(void)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
struct io7 *io7 = NULL;
|
|
|
|
|
|
|
|
|
|
/* Reserve the legacy irqs. */
|
|
|
|
|
for (i = 0; i < 16; ++i) {
|
|
|
|
|
irq_desc[i].status = IRQ_DISABLED;
|
[PATCH] genirq: rename desc->handler to desc->chip
This patch-queue improves the generic IRQ layer to be truly generic, by adding
various abstractions and features to it, without impacting existing
functionality.
While the queue can be best described as "fix and improve everything in the
generic IRQ layer that we could think of", and thus it consists of many
smaller features and lots of cleanups, the one feature that stands out most is
the new 'irq chip' abstraction.
The irq-chip abstraction is about describing and coding and IRQ controller
driver by mapping its raw hardware capabilities [and quirks, if needed] in a
straightforward way, without having to think about "IRQ flow"
(level/edge/etc.) type of details.
This stands in contrast with the current 'irq-type' model of genirq
architectures, which 'mixes' raw hardware capabilities with 'flow' details.
The patchset supports both types of irq controller designs at once, and
converts i386 and x86_64 to the new irq-chip design.
As a bonus side-effect of the irq-chip approach, chained interrupt controllers
(master/slave PIC constructs, etc.) are now supported by design as well.
The end result of this patchset intends to be simpler architecture-level code
and more consolidation between architectures.
We reused many bits of code and many concepts from Russell King's ARM IRQ
layer, the merging of which was one of the motivations for this patchset.
This patch:
rename desc->handler to desc->chip.
Originally i did not want to do this, because it's a big patch. But having
both "desc->handler", "desc->handle_irq" and "action->handler" caused a
large degree of confusion and made the code appear alot less clean than it
truly is.
I have also attempted a dual approach as well by introducing a
desc->chip alias - but that just wasnt robust enough and broke
frequently.
So lets get over with this quickly. The conversion was done automatically
via scripts and converts all the code in the kernel.
This renaming patch is the first one amongst the patches, so that the
remaining patches can stay flexible and can be merged and split up
without having some big monolithic patch act as a merge barrier.
[akpm@osdl.org: build fix]
[akpm@osdl.org: another build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-29 03:24:36 -06:00
|
|
|
|
irq_desc[i].chip = &marvel_legacy_irq_type;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Init the io7 irqs. */
|
|
|
|
|
for (io7 = NULL; (io7 = marvel_next_io7(io7)) != NULL; )
|
|
|
|
|
init_io7_irqs(io7, &io7_lsi_irq_type, &io7_msi_irq_type);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
marvel_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
|
|
|
|
|
{
|
|
|
|
|
struct pci_controller *hose = dev->sysdata;
|
|
|
|
|
struct io7_port *io7_port = hose->sysdata;
|
|
|
|
|
struct io7 *io7 = io7_port->io7;
|
|
|
|
|
int msi_loc, msi_data_off;
|
|
|
|
|
u16 msg_ctl;
|
|
|
|
|
u16 msg_dat;
|
|
|
|
|
u8 intline;
|
|
|
|
|
int irq;
|
|
|
|
|
|
|
|
|
|
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline);
|
|
|
|
|
irq = intline;
|
|
|
|
|
|
|
|
|
|
msi_loc = pci_find_capability(dev, PCI_CAP_ID_MSI);
|
|
|
|
|
msg_ctl = 0;
|
|
|
|
|
if (msi_loc)
|
|
|
|
|
pci_read_config_word(dev, msi_loc + PCI_MSI_FLAGS, &msg_ctl);
|
|
|
|
|
|
|
|
|
|
if (msg_ctl & PCI_MSI_FLAGS_ENABLE) {
|
|
|
|
|
msi_data_off = PCI_MSI_DATA_32;
|
|
|
|
|
if (msg_ctl & PCI_MSI_FLAGS_64BIT)
|
|
|
|
|
msi_data_off = PCI_MSI_DATA_64;
|
|
|
|
|
pci_read_config_word(dev, msi_loc + msi_data_off, &msg_dat);
|
|
|
|
|
|
|
|
|
|
irq = msg_dat & 0x1ff; /* we use msg_data<8:0> */
|
|
|
|
|
irq += 0x80; /* offset for lsi */
|
|
|
|
|
|
|
|
|
|
#if 1
|
2005-07-16 20:22:20 -06:00
|
|
|
|
printk("PCI:%d:%d:%d (hose %d) is using MSI\n",
|
2005-04-16 16:20:36 -06:00
|
|
|
|
dev->bus->number,
|
|
|
|
|
PCI_SLOT(dev->devfn),
|
|
|
|
|
PCI_FUNC(dev->devfn),
|
2005-07-16 20:22:20 -06:00
|
|
|
|
hose->index);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
printk(" %d message(s) from 0x%04x\n",
|
|
|
|
|
1 << ((msg_ctl & PCI_MSI_FLAGS_QSIZE) >> 4),
|
|
|
|
|
msg_dat);
|
|
|
|
|
printk(" reporting on %d IRQ(s) from %d (0x%x)\n",
|
|
|
|
|
1 << ((msg_ctl & PCI_MSI_FLAGS_QSIZE) >> 4),
|
|
|
|
|
(irq + 16) | (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT),
|
|
|
|
|
(irq + 16) | (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT));
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
|
pci_write_config_word(dev, msi_loc + PCI_MSI_FLAGS,
|
|
|
|
|
msg_ctl & ~PCI_MSI_FLAGS_ENABLE);
|
|
|
|
|
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &intline);
|
|
|
|
|
irq = intline;
|
|
|
|
|
|
|
|
|
|
printk(" forcing LSI interrupt on irq %d [0x%x]\n", irq, irq);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
irq += 16; /* offset for legacy */
|
|
|
|
|
irq |= io7->pe << MARVEL_IRQ_VEC_PE_SHIFT; /* merge the pid */
|
|
|
|
|
|
|
|
|
|
return irq;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __init
|
|
|
|
|
marvel_init_pci(void)
|
|
|
|
|
{
|
|
|
|
|
struct io7 *io7;
|
|
|
|
|
|
|
|
|
|
marvel_register_error_handlers();
|
|
|
|
|
|
|
|
|
|
pci_probe_only = 1;
|
|
|
|
|
common_init_pci();
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_VGA_HOSE
|
|
|
|
|
locate_and_init_vga(NULL);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* Clear any io7 errors. */
|
|
|
|
|
for (io7 = NULL; (io7 = marvel_next_io7(io7)) != NULL; )
|
|
|
|
|
io7_clear_errors(io7);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
marvel_init_rtc(void)
|
|
|
|
|
{
|
|
|
|
|
init_rtc_irq();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
marvel_smp_callin(void)
|
|
|
|
|
{
|
|
|
|
|
int cpuid = hard_smp_processor_id();
|
|
|
|
|
struct io7 *io7 = marvel_find_io7(cpuid);
|
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
|
|
if (!io7)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* There is a local IO7 - redirect all of its interrupts here.
|
|
|
|
|
*/
|
|
|
|
|
printk("Redirecting IO7 interrupts to local CPU at PE %u\n", cpuid);
|
|
|
|
|
|
|
|
|
|
/* Redirect the error IRQS here. */
|
|
|
|
|
io7_redirect_irq(io7, &io7->csrs->HLT_CTL.csr, cpuid);
|
|
|
|
|
io7_redirect_irq(io7, &io7->csrs->HPI_CTL.csr, cpuid);
|
|
|
|
|
io7_redirect_irq(io7, &io7->csrs->CRD_CTL.csr, cpuid);
|
|
|
|
|
io7_redirect_irq(io7, &io7->csrs->STV_CTL.csr, cpuid);
|
|
|
|
|
io7_redirect_irq(io7, &io7->csrs->HEI_CTL.csr, cpuid);
|
|
|
|
|
|
|
|
|
|
/* Redirect the implemented LSIs here. */
|
|
|
|
|
for (i = 0; i < 0x60; ++i)
|
|
|
|
|
io7_redirect_one_lsi(io7, i, cpuid);
|
|
|
|
|
|
|
|
|
|
io7_redirect_one_lsi(io7, 0x74, cpuid);
|
|
|
|
|
io7_redirect_one_lsi(io7, 0x75, cpuid);
|
|
|
|
|
|
|
|
|
|
/* Redirect the MSIs here. */
|
|
|
|
|
for (i = 0; i < 16; ++i)
|
|
|
|
|
io7_redirect_one_msi(io7, i, cpuid);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* System Vectors
|
|
|
|
|
*/
|
|
|
|
|
struct alpha_machine_vector marvel_ev7_mv __initmv = {
|
|
|
|
|
.vector_name = "MARVEL/EV7",
|
|
|
|
|
DO_EV7_MMU,
|
|
|
|
|
DO_DEFAULT_RTC,
|
|
|
|
|
DO_MARVEL_IO,
|
|
|
|
|
.machine_check = marvel_machine_check,
|
|
|
|
|
.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
|
|
|
|
|
.min_io_address = DEFAULT_IO_BASE,
|
|
|
|
|
.min_mem_address = DEFAULT_MEM_BASE,
|
|
|
|
|
.pci_dac_offset = IO7_DAC_OFFSET,
|
|
|
|
|
|
|
|
|
|
.nr_irqs = MARVEL_NR_IRQS,
|
|
|
|
|
.device_interrupt = io7_device_interrupt,
|
|
|
|
|
|
|
|
|
|
.agp_info = marvel_agp_info,
|
|
|
|
|
|
|
|
|
|
.smp_callin = marvel_smp_callin,
|
|
|
|
|
.init_arch = marvel_init_arch,
|
|
|
|
|
.init_irq = marvel_init_irq,
|
|
|
|
|
.init_rtc = marvel_init_rtc,
|
|
|
|
|
.init_pci = marvel_init_pci,
|
|
|
|
|
.kill_arch = marvel_kill_arch,
|
|
|
|
|
.pci_map_irq = marvel_map_irq,
|
|
|
|
|
.pci_swizzle = common_swizzle,
|
|
|
|
|
|
|
|
|
|
.pa_to_nid = marvel_pa_to_nid,
|
|
|
|
|
.cpuid_to_nid = marvel_cpuid_to_nid,
|
|
|
|
|
.node_mem_start = marvel_node_mem_start,
|
|
|
|
|
.node_mem_size = marvel_node_mem_size,
|
|
|
|
|
};
|
|
|
|
|
ALIAS_MV(marvel_ev7)
|