2007-07-24 16:17:33 -06:00
|
|
|
/* head.S: Initial boot code for the Sparc64 port of Linux.
|
2005-04-16 16:20:36 -06:00
|
|
|
*
|
2007-07-24 16:17:33 -06:00
|
|
|
* Copyright (C) 1996, 1997, 2007 David S. Miller (davem@davemloft.net)
|
2005-04-16 16:20:36 -06:00
|
|
|
* Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
|
2007-07-24 16:17:33 -06:00
|
|
|
* Copyright (C) 1997, 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
|
2005-04-16 16:20:36 -06:00
|
|
|
* Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/version.h>
|
|
|
|
#include <linux/errno.h>
|
2006-05-31 02:24:02 -06:00
|
|
|
#include <linux/threads.h>
|
2007-07-24 16:17:33 -06:00
|
|
|
#include <linux/init.h>
|
2008-09-01 04:13:17 -06:00
|
|
|
#include <linux/linkage.h>
|
2005-04-16 16:20:36 -06:00
|
|
|
#include <asm/thread_info.h>
|
|
|
|
#include <asm/asi.h>
|
|
|
|
#include <asm/pstate.h>
|
|
|
|
#include <asm/ptrace.h>
|
|
|
|
#include <asm/spitfire.h>
|
|
|
|
#include <asm/page.h>
|
|
|
|
#include <asm/pgtable.h>
|
|
|
|
#include <asm/errno.h>
|
|
|
|
#include <asm/signal.h>
|
|
|
|
#include <asm/processor.h>
|
|
|
|
#include <asm/lsu.h>
|
|
|
|
#include <asm/dcr.h>
|
|
|
|
#include <asm/dcu.h>
|
|
|
|
#include <asm/head.h>
|
|
|
|
#include <asm/ttable.h>
|
|
|
|
#include <asm/mmu.h>
|
2006-02-27 00:24:22 -07:00
|
|
|
#include <asm/cpudata.h>
|
2008-04-28 01:47:20 -06:00
|
|
|
#include <asm/pil.h>
|
|
|
|
#include <asm/estate.h>
|
|
|
|
#include <asm/sfafsr.h>
|
|
|
|
#include <asm/unistd.h>
|
2016-01-16 19:39:30 -07:00
|
|
|
#include <asm/export.h>
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/* This section from from _start to sparc64_boot_end should fit into
|
2005-10-12 13:22:46 -06:00
|
|
|
* 0x0000000000404000 to 0x0000000000408000.
|
2005-04-16 16:20:36 -06:00
|
|
|
*/
|
|
|
|
.text
|
|
|
|
.globl start, _start, stext, _stext
|
|
|
|
_start:
|
|
|
|
start:
|
|
|
|
_stext:
|
|
|
|
stext:
|
|
|
|
! 0x0000000000404000
|
|
|
|
b sparc64_boot
|
|
|
|
flushw /* Flush register file. */
|
|
|
|
|
|
|
|
/* This stuff has to be in sync with SILO and other potential boot loaders
|
|
|
|
* Fields should be kept upward compatible and whenever any change is made,
|
|
|
|
* HdrS version should be incremented.
|
|
|
|
*/
|
|
|
|
.global root_flags, ram_flags, root_dev
|
|
|
|
.global sparc_ramdisk_image, sparc_ramdisk_size
|
|
|
|
.global sparc_ramdisk_image64
|
|
|
|
|
|
|
|
.ascii "HdrS"
|
|
|
|
.word LINUX_VERSION_CODE
|
|
|
|
|
|
|
|
/* History:
|
|
|
|
*
|
|
|
|
* 0x0300 : Supports being located at other than 0x4000
|
|
|
|
* 0x0202 : Supports kernel params string
|
|
|
|
* 0x0201 : Supports reboot_command
|
|
|
|
*/
|
|
|
|
.half 0x0301 /* HdrS version */
|
|
|
|
|
|
|
|
root_flags:
|
|
|
|
.half 1
|
|
|
|
root_dev:
|
|
|
|
.half 0
|
|
|
|
ram_flags:
|
|
|
|
.half 0
|
|
|
|
sparc_ramdisk_image:
|
|
|
|
.word 0
|
|
|
|
sparc_ramdisk_size:
|
|
|
|
.word 0
|
|
|
|
.xword reboot_command
|
|
|
|
.xword bootstr_info
|
|
|
|
sparc_ramdisk_image64:
|
|
|
|
.xword 0
|
|
|
|
.word _end
|
|
|
|
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 21:11:33 -06:00
|
|
|
/* PROM cif handler code address is in %o4. */
|
|
|
|
sparc64_boot:
|
2006-12-11 22:06:55 -07:00
|
|
|
mov %o4, %l7
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 21:11:33 -06:00
|
|
|
|
2011-03-30 19:57:33 -06:00
|
|
|
/* We need to remap the kernel. Use position independent
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 21:11:33 -06:00
|
|
|
* code to remap us to KERNBASE.
|
2005-04-16 16:20:36 -06:00
|
|
|
*
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 21:11:33 -06:00
|
|
|
* SILO can invoke us with 32-bit address masking enabled,
|
|
|
|
* so make sure that's clear.
|
2005-04-16 16:20:36 -06:00
|
|
|
*/
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 21:11:33 -06:00
|
|
|
rdpr %pstate, %g1
|
|
|
|
andn %g1, PSTATE_AM, %g1
|
|
|
|
wrpr %g1, 0x0, %pstate
|
|
|
|
ba,a,pt %xcc, 1f
|
arch/sparc: Avoid DCTI Couples
Avoid un-intended DCTI Couples. Use of DCTI couples is deprecated.
Also address the "Programming Note" for optimal performance.
Here is the complete text from Oracle SPARC Architecture Specs.
6.3.4.7 DCTI Couples
"A delayed control transfer instruction (DCTI) in the delay slot of
another DCTI is referred to as a “DCTI couple”. The use of DCTI couples
is deprecated in the Oracle SPARC Architecture; no new software should
place a DCTI in the delay slot of another DCTI, because on future Oracle
SPARC Architecture implementations DCTI couples may execute either
slowly or differently than the programmer assumes it will.
SPARC V8 and SPARC V9 Compatibility Note
The SPARC V8 architecture left behavior undefined for a DCTI couple. The
SPARC V9 architecture defined behavior in that case, but as of
UltraSPARC Architecture 2005, use of DCTI couples was deprecated.
Software should not expect high performance from DCTI couples, and
performance of DCTI couples should be expected to decline further in
future processors.
Programming Note
As noted in TABLE 6-5 on page 115, an annulled branch-always
(branch-always with a = 1) instruction is not architecturally a DCTI.
However, since not all implementations make that distinction, for
optimal performance, a DCTI should not be placed in the instruction word
immediately following an annulled branch-always instruction (BA,A or
BPA,A)."
Signed-off-by: Babu Moger <babu.moger@oracle.com>
Reviewed-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-17 14:52:21 -06:00
|
|
|
nop
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 21:11:33 -06:00
|
|
|
|
2006-02-09 03:52:44 -07:00
|
|
|
.globl prom_finddev_name, prom_chosen_path, prom_root_node
|
|
|
|
.globl prom_getprop_name, prom_mmu_name, prom_peer_name
|
|
|
|
.globl prom_callmethod_name, prom_translate_name, prom_root_compatible
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 21:11:33 -06:00
|
|
|
.globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
|
|
|
|
.globl prom_boot_mapped_pc, prom_boot_mapping_mode
|
|
|
|
.globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
|
2007-08-08 18:11:39 -06:00
|
|
|
.globl prom_compatible_name, prom_cpu_path, prom_cpu_compatible
|
2007-09-16 12:51:15 -06:00
|
|
|
.globl is_sun4v, sun4v_chip_type, prom_set_trap_table_name
|
2006-02-09 03:52:44 -07:00
|
|
|
prom_peer_name:
|
|
|
|
.asciz "peer"
|
|
|
|
prom_compatible_name:
|
|
|
|
.asciz "compatible"
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 21:11:33 -06:00
|
|
|
prom_finddev_name:
|
|
|
|
.asciz "finddevice"
|
|
|
|
prom_chosen_path:
|
|
|
|
.asciz "/chosen"
|
2007-08-08 18:11:39 -06:00
|
|
|
prom_cpu_path:
|
|
|
|
.asciz "/cpu"
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 21:11:33 -06:00
|
|
|
prom_getprop_name:
|
|
|
|
.asciz "getprop"
|
|
|
|
prom_mmu_name:
|
|
|
|
.asciz "mmu"
|
|
|
|
prom_callmethod_name:
|
|
|
|
.asciz "call-method"
|
|
|
|
prom_translate_name:
|
|
|
|
.asciz "translate"
|
|
|
|
prom_map_name:
|
|
|
|
.asciz "map"
|
|
|
|
prom_unmap_name:
|
|
|
|
.asciz "unmap"
|
2007-09-16 12:51:15 -06:00
|
|
|
prom_set_trap_table_name:
|
|
|
|
.asciz "SUNW,set-trap-table"
|
2006-02-09 03:52:44 -07:00
|
|
|
prom_sun4v_name:
|
2006-02-11 11:56:43 -07:00
|
|
|
.asciz "sun4v"
|
2007-08-08 18:11:39 -06:00
|
|
|
prom_niagara_prefix:
|
|
|
|
.asciz "SUNW,UltraSPARC-T"
|
sparc: Detect and handle UltraSPARC-T3 cpu types.
The cpu compatible string we look for is "SPARC-T3".
As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+. Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.
We use the Niagara-T2 perf support, since T3 is a close relative in
this regard. Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.
For now I haven't added any new ELF hwcap flags. We probably need
to add a couple, for example:
T2 and T3 both support the population count instruction in hardware.
T3 supports VIS3 instructions, including support (finally) for
partitioned shift. One can also now move directly between float
and integer registers.
T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply. Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.
T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.
So we'll need about 3 new elf capability flags in the end to represent
all of these things.
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-07-27 22:06:16 -06:00
|
|
|
prom_sparc_prefix:
|
2011-09-11 11:42:20 -06:00
|
|
|
.asciz "SPARC-"
|
2013-03-05 16:47:59 -07:00
|
|
|
prom_sparc64x_prefix:
|
|
|
|
.asciz "SPARC64-X"
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 21:11:33 -06:00
|
|
|
.align 4
|
2006-02-09 03:52:44 -07:00
|
|
|
prom_root_compatible:
|
|
|
|
.skip 64
|
2007-08-08 18:11:39 -06:00
|
|
|
prom_cpu_compatible:
|
|
|
|
.skip 64
|
2006-02-09 03:52:44 -07:00
|
|
|
prom_root_node:
|
|
|
|
.word 0
|
2016-01-16 19:39:30 -07:00
|
|
|
EXPORT_SYMBOL(prom_root_node)
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 21:11:33 -06:00
|
|
|
prom_mmu_ihandle_cache:
|
|
|
|
.word 0
|
|
|
|
prom_boot_mapped_pc:
|
|
|
|
.word 0
|
|
|
|
prom_boot_mapping_mode:
|
|
|
|
.word 0
|
|
|
|
.align 8
|
|
|
|
prom_boot_mapping_phys_high:
|
|
|
|
.xword 0
|
|
|
|
prom_boot_mapping_phys_low:
|
|
|
|
.xword 0
|
2006-02-09 03:52:44 -07:00
|
|
|
is_sun4v:
|
|
|
|
.word 0
|
2007-08-08 18:11:39 -06:00
|
|
|
sun4v_chip_type:
|
|
|
|
.word SUN4V_CHIP_INVALID
|
2016-01-16 19:39:30 -07:00
|
|
|
EXPORT_SYMBOL(sun4v_chip_type)
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 21:11:33 -06:00
|
|
|
1:
|
|
|
|
rd %pc, %l0
|
2006-02-09 03:52:44 -07:00
|
|
|
|
|
|
|
mov (1b - prom_peer_name), %l1
|
|
|
|
sub %l0, %l1, %l1
|
|
|
|
mov 0, %l2
|
|
|
|
|
|
|
|
/* prom_root_node = prom_peer(0) */
|
|
|
|
stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "peer"
|
|
|
|
mov 1, %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
|
|
|
|
stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, 0
|
|
|
|
stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
|
|
|
|
call %l7
|
|
|
|
add %sp, (2047 + 128), %o0 ! argument array
|
|
|
|
|
|
|
|
ldx [%sp + 2047 + 128 + 0x20], %l4 ! prom root node
|
|
|
|
mov (1b - prom_root_node), %l1
|
|
|
|
sub %l0, %l1, %l1
|
|
|
|
stw %l4, [%l1]
|
|
|
|
|
|
|
|
mov (1b - prom_getprop_name), %l1
|
|
|
|
mov (1b - prom_compatible_name), %l2
|
|
|
|
mov (1b - prom_root_compatible), %l5
|
|
|
|
sub %l0, %l1, %l1
|
|
|
|
sub %l0, %l2, %l2
|
|
|
|
sub %l0, %l5, %l5
|
|
|
|
|
|
|
|
/* prom_getproperty(prom_root_node, "compatible",
|
|
|
|
* &prom_root_compatible, 64)
|
|
|
|
*/
|
|
|
|
stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
|
|
|
|
mov 4, %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
|
|
|
|
mov 1, %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
|
|
|
|
stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, prom_root_node
|
|
|
|
stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
|
|
|
|
stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_root_compatible
|
|
|
|
mov 64, %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
|
|
|
|
stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
|
|
|
|
call %l7
|
|
|
|
add %sp, (2047 + 128), %o0 ! argument array
|
|
|
|
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 21:11:33 -06:00
|
|
|
mov (1b - prom_finddev_name), %l1
|
|
|
|
mov (1b - prom_chosen_path), %l2
|
|
|
|
mov (1b - prom_boot_mapped_pc), %l3
|
|
|
|
sub %l0, %l1, %l1
|
|
|
|
sub %l0, %l2, %l2
|
|
|
|
sub %l0, %l3, %l3
|
|
|
|
stw %l0, [%l3]
|
|
|
|
sub %sp, (192 + 128), %sp
|
|
|
|
|
|
|
|
/* chosen_node = prom_finddevice("/chosen") */
|
|
|
|
stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
|
|
|
|
mov 1, %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
|
|
|
|
stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
|
|
|
|
stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
|
|
|
|
call %l7
|
|
|
|
add %sp, (2047 + 128), %o0 ! argument array
|
|
|
|
|
|
|
|
ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node
|
|
|
|
|
|
|
|
mov (1b - prom_getprop_name), %l1
|
|
|
|
mov (1b - prom_mmu_name), %l2
|
|
|
|
mov (1b - prom_mmu_ihandle_cache), %l5
|
|
|
|
sub %l0, %l1, %l1
|
|
|
|
sub %l0, %l2, %l2
|
|
|
|
sub %l0, %l5, %l5
|
|
|
|
|
|
|
|
/* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
|
|
|
|
stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
|
|
|
|
mov 4, %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
|
|
|
|
mov 1, %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
|
|
|
|
stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node
|
|
|
|
stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu"
|
|
|
|
stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache
|
|
|
|
mov 4, %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3)
|
|
|
|
stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
|
|
|
|
call %l7
|
|
|
|
add %sp, (2047 + 128), %o0 ! argument array
|
|
|
|
|
|
|
|
mov (1b - prom_callmethod_name), %l1
|
|
|
|
mov (1b - prom_translate_name), %l2
|
|
|
|
sub %l0, %l1, %l1
|
|
|
|
sub %l0, %l2, %l2
|
|
|
|
lduw [%l5], %l5 ! prom_mmu_ihandle_cache
|
|
|
|
|
|
|
|
stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method"
|
|
|
|
mov 3, %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3
|
|
|
|
mov 5, %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5
|
|
|
|
stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate"
|
|
|
|
stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache
|
2005-10-11 16:45:16 -06:00
|
|
|
/* PAGE align */
|
|
|
|
srlx %l0, 13, %l3
|
|
|
|
sllx %l3, 13, %l3
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 21:11:33 -06:00
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC
|
|
|
|
stx %g0, [%sp + 2047 + 128 + 0x30] ! res1
|
|
|
|
stx %g0, [%sp + 2047 + 128 + 0x38] ! res2
|
|
|
|
stx %g0, [%sp + 2047 + 128 + 0x40] ! res3
|
|
|
|
stx %g0, [%sp + 2047 + 128 + 0x48] ! res4
|
|
|
|
stx %g0, [%sp + 2047 + 128 + 0x50] ! res5
|
|
|
|
call %l7
|
|
|
|
add %sp, (2047 + 128), %o0 ! argument array
|
|
|
|
|
|
|
|
ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode
|
|
|
|
mov (1b - prom_boot_mapping_mode), %l4
|
|
|
|
sub %l0, %l4, %l4
|
|
|
|
stw %l1, [%l4]
|
|
|
|
mov (1b - prom_boot_mapping_phys_high), %l4
|
|
|
|
sub %l0, %l4, %l4
|
|
|
|
ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high
|
|
|
|
stx %l2, [%l4 + 0x0]
|
|
|
|
ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low
|
2005-10-11 16:45:16 -06:00
|
|
|
/* 4MB align */
|
2014-05-03 23:52:50 -06:00
|
|
|
srlx %l3, ILOG2_4MB, %l3
|
|
|
|
sllx %l3, ILOG2_4MB, %l3
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 21:11:33 -06:00
|
|
|
stx %l3, [%l4 + 0x8]
|
|
|
|
|
|
|
|
/* Leave service as-is, "call-method" */
|
|
|
|
mov 7, %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7
|
|
|
|
mov 1, %l3
|
2005-09-22 21:31:29 -06:00
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 21:11:33 -06:00
|
|
|
mov (1b - prom_map_name), %l3
|
|
|
|
sub %l0, %l3, %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map"
|
|
|
|
/* Leave arg2 as-is, prom_mmu_ihandle_cache */
|
|
|
|
mov -1, %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default)
|
2008-03-21 18:01:38 -06:00
|
|
|
/* 4MB align the kernel image size. */
|
|
|
|
set (_end - KERNBASE), %l3
|
|
|
|
set ((4 * 1024 * 1024) - 1), %l4
|
|
|
|
add %l3, %l4, %l3
|
|
|
|
andn %l3, %l4, %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: roundup(ksize, 4MB)
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 21:11:33 -06:00
|
|
|
sethi %hi(KERNBASE), %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE)
|
|
|
|
stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty
|
|
|
|
mov (1b - prom_boot_mapping_phys_low), %l3
|
|
|
|
sub %l0, %l3, %l3
|
|
|
|
ldx [%l3], %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr
|
|
|
|
call %l7
|
|
|
|
add %sp, (2047 + 128), %o0 ! argument array
|
|
|
|
|
|
|
|
add %sp, (192 + 128), %sp
|
|
|
|
|
2006-02-09 03:52:44 -07:00
|
|
|
sethi %hi(prom_root_compatible), %g1
|
|
|
|
or %g1, %lo(prom_root_compatible), %g1
|
|
|
|
sethi %hi(prom_sun4v_name), %g7
|
|
|
|
or %g7, %lo(prom_sun4v_name), %g7
|
2006-02-11 11:56:43 -07:00
|
|
|
mov 5, %g3
|
2007-08-08 18:11:39 -06:00
|
|
|
90: ldub [%g7], %g2
|
2006-02-09 03:52:44 -07:00
|
|
|
ldub [%g1], %g4
|
|
|
|
cmp %g2, %g4
|
2007-08-08 18:11:39 -06:00
|
|
|
bne,pn %icc, 80f
|
2006-02-09 03:52:44 -07:00
|
|
|
add %g7, 1, %g7
|
|
|
|
subcc %g3, 1, %g3
|
2007-08-08 18:11:39 -06:00
|
|
|
bne,pt %xcc, 90b
|
2006-02-09 03:52:44 -07:00
|
|
|
add %g1, 1, %g1
|
|
|
|
|
|
|
|
sethi %hi(is_sun4v), %g1
|
|
|
|
or %g1, %lo(is_sun4v), %g1
|
|
|
|
mov 1, %g7
|
|
|
|
stw %g7, [%g1]
|
|
|
|
|
2007-08-08 18:11:39 -06:00
|
|
|
/* cpu_node = prom_finddevice("/cpu") */
|
|
|
|
mov (1b - prom_finddev_name), %l1
|
|
|
|
mov (1b - prom_cpu_path), %l2
|
|
|
|
sub %l0, %l1, %l1
|
|
|
|
sub %l0, %l2, %l2
|
|
|
|
sub %sp, (192 + 128), %sp
|
|
|
|
|
|
|
|
stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
|
|
|
|
mov 1, %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
|
|
|
|
stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/cpu"
|
|
|
|
stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
|
|
|
|
call %l7
|
|
|
|
add %sp, (2047 + 128), %o0 ! argument array
|
|
|
|
|
|
|
|
ldx [%sp + 2047 + 128 + 0x20], %l4 ! cpu device node
|
|
|
|
|
|
|
|
mov (1b - prom_getprop_name), %l1
|
|
|
|
mov (1b - prom_compatible_name), %l2
|
|
|
|
mov (1b - prom_cpu_compatible), %l5
|
|
|
|
sub %l0, %l1, %l1
|
|
|
|
sub %l0, %l2, %l2
|
|
|
|
sub %l0, %l5, %l5
|
|
|
|
|
|
|
|
/* prom_getproperty(cpu_node, "compatible",
|
|
|
|
* &prom_cpu_compatible, 64)
|
|
|
|
*/
|
|
|
|
stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
|
|
|
|
mov 4, %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
|
|
|
|
mov 1, %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
|
|
|
|
stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, cpu_node
|
|
|
|
stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
|
|
|
|
stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_cpu_compatible
|
|
|
|
mov 64, %l3
|
|
|
|
stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
|
|
|
|
stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
|
|
|
|
call %l7
|
|
|
|
add %sp, (2047 + 128), %o0 ! argument array
|
|
|
|
|
|
|
|
add %sp, (192 + 128), %sp
|
|
|
|
|
|
|
|
sethi %hi(prom_cpu_compatible), %g1
|
|
|
|
or %g1, %lo(prom_cpu_compatible), %g1
|
|
|
|
sethi %hi(prom_niagara_prefix), %g7
|
|
|
|
or %g7, %lo(prom_niagara_prefix), %g7
|
|
|
|
mov 17, %g3
|
sparc: Detect and handle UltraSPARC-T3 cpu types.
The cpu compatible string we look for is "SPARC-T3".
As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+. Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.
We use the Niagara-T2 perf support, since T3 is a close relative in
this regard. Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.
For now I haven't added any new ELF hwcap flags. We probably need
to add a couple, for example:
T2 and T3 both support the population count instruction in hardware.
T3 supports VIS3 instructions, including support (finally) for
partitioned shift. One can also now move directly between float
and integer registers.
T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply. Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.
T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.
So we'll need about 3 new elf capability flags in the end to represent
all of these things.
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-07-27 22:06:16 -06:00
|
|
|
90: ldub [%g7], %g2
|
|
|
|
ldub [%g1], %g4
|
|
|
|
cmp %g2, %g4
|
|
|
|
bne,pn %icc, 89f
|
|
|
|
add %g7, 1, %g7
|
|
|
|
subcc %g3, 1, %g3
|
|
|
|
bne,pt %xcc, 90b
|
|
|
|
add %g1, 1, %g1
|
|
|
|
ba,pt %xcc, 91f
|
|
|
|
nop
|
|
|
|
|
|
|
|
89: sethi %hi(prom_cpu_compatible), %g1
|
|
|
|
or %g1, %lo(prom_cpu_compatible), %g1
|
|
|
|
sethi %hi(prom_sparc_prefix), %g7
|
|
|
|
or %g7, %lo(prom_sparc_prefix), %g7
|
2011-09-11 11:42:20 -06:00
|
|
|
mov 6, %g3
|
2007-08-08 18:11:39 -06:00
|
|
|
90: ldub [%g7], %g2
|
|
|
|
ldub [%g1], %g4
|
|
|
|
cmp %g2, %g4
|
|
|
|
bne,pn %icc, 4f
|
|
|
|
add %g7, 1, %g7
|
|
|
|
subcc %g3, 1, %g3
|
|
|
|
bne,pt %xcc, 90b
|
|
|
|
add %g1, 1, %g1
|
|
|
|
|
|
|
|
sethi %hi(prom_cpu_compatible), %g1
|
sparc: Detect and handle UltraSPARC-T3 cpu types.
The cpu compatible string we look for is "SPARC-T3".
As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+. Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.
We use the Niagara-T2 perf support, since T3 is a close relative in
this regard. Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.
For now I haven't added any new ELF hwcap flags. We probably need
to add a couple, for example:
T2 and T3 both support the population count instruction in hardware.
T3 supports VIS3 instructions, including support (finally) for
partitioned shift. One can also now move directly between float
and integer registers.
T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply. Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.
T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.
So we'll need about 3 new elf capability flags in the end to represent
all of these things.
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-07-27 22:06:16 -06:00
|
|
|
or %g1, %lo(prom_cpu_compatible), %g1
|
2011-09-11 11:42:20 -06:00
|
|
|
ldub [%g1 + 6], %g2
|
|
|
|
cmp %g2, 'T'
|
|
|
|
be,pt %xcc, 70f
|
|
|
|
cmp %g2, 'M'
|
2016-04-19 11:12:54 -06:00
|
|
|
be,pt %xcc, 70f
|
|
|
|
cmp %g2, 'S'
|
2013-03-05 16:47:59 -07:00
|
|
|
bne,pn %xcc, 49f
|
2011-09-11 11:42:20 -06:00
|
|
|
nop
|
|
|
|
|
|
|
|
70: ldub [%g1 + 7], %g2
|
sparc: Detect and handle UltraSPARC-T3 cpu types.
The cpu compatible string we look for is "SPARC-T3".
As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+. Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.
We use the Niagara-T2 perf support, since T3 is a close relative in
this regard. Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.
For now I haven't added any new ELF hwcap flags. We probably need
to add a couple, for example:
T2 and T3 both support the population count instruction in hardware.
T3 supports VIS3 instructions, including support (finally) for
partitioned shift. One can also now move directly between float
and integer registers.
T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply. Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.
T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.
So we'll need about 3 new elf capability flags in the end to represent
all of these things.
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-07-27 22:06:16 -06:00
|
|
|
cmp %g2, '3'
|
|
|
|
be,pt %xcc, 5f
|
|
|
|
mov SUN4V_CHIP_NIAGARA3, %g4
|
2011-09-11 11:42:20 -06:00
|
|
|
cmp %g2, '4'
|
|
|
|
be,pt %xcc, 5f
|
|
|
|
mov SUN4V_CHIP_NIAGARA4, %g4
|
|
|
|
cmp %g2, '5'
|
|
|
|
be,pt %xcc, 5f
|
|
|
|
mov SUN4V_CHIP_NIAGARA5, %g4
|
2014-09-08 00:18:53 -06:00
|
|
|
cmp %g2, '6'
|
|
|
|
be,pt %xcc, 5f
|
|
|
|
mov SUN4V_CHIP_SPARC_M6, %g4
|
|
|
|
cmp %g2, '7'
|
|
|
|
be,pt %xcc, 5f
|
|
|
|
mov SUN4V_CHIP_SPARC_M7, %g4
|
2016-04-19 11:12:54 -06:00
|
|
|
cmp %g2, 'N'
|
|
|
|
be,pt %xcc, 5f
|
|
|
|
mov SUN4V_CHIP_SPARC_SN, %g4
|
2013-03-05 16:47:59 -07:00
|
|
|
ba,pt %xcc, 49f
|
sparc: Detect and handle UltraSPARC-T3 cpu types.
The cpu compatible string we look for is "SPARC-T3".
As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+. Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.
We use the Niagara-T2 perf support, since T3 is a close relative in
this regard. Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.
For now I haven't added any new ELF hwcap flags. We probably need
to add a couple, for example:
T2 and T3 both support the population count instruction in hardware.
T3 supports VIS3 instructions, including support (finally) for
partitioned shift. One can also now move directly between float
and integer registers.
T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply. Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.
T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.
So we'll need about 3 new elf capability flags in the end to represent
all of these things.
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-07-27 22:06:16 -06:00
|
|
|
nop
|
|
|
|
|
|
|
|
91: sethi %hi(prom_cpu_compatible), %g1
|
2007-08-08 18:11:39 -06:00
|
|
|
or %g1, %lo(prom_cpu_compatible), %g1
|
|
|
|
ldub [%g1 + 17], %g2
|
|
|
|
cmp %g2, '1'
|
|
|
|
be,pt %xcc, 5f
|
|
|
|
mov SUN4V_CHIP_NIAGARA1, %g4
|
|
|
|
cmp %g2, '2'
|
|
|
|
be,pt %xcc, 5f
|
|
|
|
mov SUN4V_CHIP_NIAGARA2, %g4
|
sparc: Detect and handle UltraSPARC-T3 cpu types.
The cpu compatible string we look for is "SPARC-T3".
As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+. Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.
We use the Niagara-T2 perf support, since T3 is a close relative in
this regard. Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.
For now I haven't added any new ELF hwcap flags. We probably need
to add a couple, for example:
T2 and T3 both support the population count instruction in hardware.
T3 supports VIS3 instructions, including support (finally) for
partitioned shift. One can also now move directly between float
and integer registers.
T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply. Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.
T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.
So we'll need about 3 new elf capability flags in the end to represent
all of these things.
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-07-27 22:06:16 -06:00
|
|
|
|
2007-08-08 18:11:39 -06:00
|
|
|
4:
|
2013-03-05 16:47:59 -07:00
|
|
|
/* Athena */
|
|
|
|
sethi %hi(prom_cpu_compatible), %g1
|
|
|
|
or %g1, %lo(prom_cpu_compatible), %g1
|
|
|
|
sethi %hi(prom_sparc64x_prefix), %g7
|
|
|
|
or %g7, %lo(prom_sparc64x_prefix), %g7
|
|
|
|
mov 9, %g3
|
|
|
|
41: ldub [%g7], %g2
|
|
|
|
ldub [%g1], %g4
|
|
|
|
cmp %g2, %g4
|
|
|
|
bne,pn %icc, 49f
|
|
|
|
add %g7, 1, %g7
|
|
|
|
subcc %g3, 1, %g3
|
|
|
|
bne,pt %xcc, 41b
|
|
|
|
add %g1, 1, %g1
|
|
|
|
ba,pt %xcc, 5f
|
2016-04-27 15:27:37 -06:00
|
|
|
mov SUN4V_CHIP_SPARC64X, %g4
|
2013-03-05 16:47:59 -07:00
|
|
|
|
|
|
|
49:
|
2007-08-08 18:11:39 -06:00
|
|
|
mov SUN4V_CHIP_UNKNOWN, %g4
|
|
|
|
5: sethi %hi(sun4v_chip_type), %g2
|
|
|
|
or %g2, %lo(sun4v_chip_type), %g2
|
|
|
|
stw %g4, [%g2]
|
|
|
|
|
|
|
|
80:
|
2006-02-09 03:52:44 -07:00
|
|
|
BRANCH_IF_SUN4V(g1, jump_to_sun4u_init)
|
2005-04-16 16:20:36 -06:00
|
|
|
BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
|
|
|
|
BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
|
|
|
|
ba,pt %xcc, spitfire_boot
|
|
|
|
nop
|
|
|
|
|
|
|
|
cheetah_plus_boot:
|
|
|
|
/* Preserve OBP chosen DCU and DCR register settings. */
|
|
|
|
ba,pt %xcc, cheetah_generic_boot
|
|
|
|
nop
|
|
|
|
|
|
|
|
cheetah_boot:
|
|
|
|
mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
|
|
|
|
wr %g1, %asr18
|
|
|
|
|
|
|
|
sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
|
|
|
|
or %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
|
|
|
|
sllx %g7, 32, %g7
|
|
|
|
or %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
|
|
|
|
stxa %g7, [%g0] ASI_DCU_CONTROL_REG
|
|
|
|
membar #Sync
|
|
|
|
|
|
|
|
cheetah_generic_boot:
|
|
|
|
mov TSB_EXTENSION_P, %g3
|
|
|
|
stxa %g0, [%g3] ASI_DMMU
|
|
|
|
stxa %g0, [%g3] ASI_IMMU
|
|
|
|
membar #Sync
|
|
|
|
|
|
|
|
mov TSB_EXTENSION_S, %g3
|
|
|
|
stxa %g0, [%g3] ASI_DMMU
|
|
|
|
membar #Sync
|
|
|
|
|
|
|
|
mov TSB_EXTENSION_N, %g3
|
|
|
|
stxa %g0, [%g3] ASI_DMMU
|
|
|
|
stxa %g0, [%g3] ASI_IMMU
|
|
|
|
membar #Sync
|
|
|
|
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 21:11:33 -06:00
|
|
|
ba,a,pt %xcc, jump_to_sun4u_init
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
spitfire_boot:
|
|
|
|
/* Typically PROM has already enabled both MMU's and both on-chip
|
|
|
|
* caches, but we do it here anyway just to be paranoid.
|
|
|
|
*/
|
|
|
|
mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
|
|
|
|
stxa %g1, [%g0] ASI_LSU_CONTROL
|
|
|
|
membar #Sync
|
|
|
|
|
[SPARC64]: Rewrite bootup sequence.
Instead of all of this cpu-specific code to remap the kernel
to the correct location, use portable firmware calls to do
this instead.
What we do now is the following in position independant
assembler:
chosen_node = prom_finddevice("/chosen");
prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu");
vaddr = 4MB_ALIGN(current_text_addr());
prom_translate(vaddr, &paddr_high, &paddr_low, &mode);
prom_boot_mapping_mode = mode;
prom_boot_mapping_phys_high = paddr_high;
prom_boot_mapping_phys_low = paddr_low;
prom_map(-1, 8 * 1024 * 1024, KERNBASE, paddr_low);
and that replaces the massive amount of by-hand TLB probing and
programming we used to do here.
The new code should also handle properly the case where the kernel
is mapped at the correct address already (think: future kexec
support).
Consequently, the bulk of remap_kernel() dies as does the entirety
of arch/sparc64/prom/map.S
We try to share some strings in the PROM library with the ones used
at bootup, and while we're here mark input strings to oplib.h routines
with "const" when appropriate.
There are many more simplifications now possible. For one thing, we
can consolidate the two copies we now have of a lot of cpu setup code
sitting in head.S and trampoline.S.
This is a significant step towards CONFIG_DEBUG_PAGEALLOC support.
Signed-off-by: David S. Miller <davem@davemloft.net>
2005-09-22 21:11:33 -06:00
|
|
|
jump_to_sun4u_init:
|
2005-04-16 16:20:36 -06:00
|
|
|
/*
|
|
|
|
* Make sure we are in privileged mode, have address masking,
|
|
|
|
* using the ordinary globals and have enabled floating
|
|
|
|
* point.
|
|
|
|
*
|
|
|
|
* Again, typically PROM has left %pil at 13 or similar, and
|
|
|
|
* (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
|
|
|
|
*/
|
|
|
|
wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
|
|
|
|
wr %g0, 0, %fprs
|
|
|
|
|
|
|
|
set sun4u_init, %g2
|
|
|
|
jmpl %g2 + %g0, %g0
|
|
|
|
nop
|
|
|
|
|
2009-04-27 12:02:26 -06:00
|
|
|
__REF
|
2005-04-16 16:20:36 -06:00
|
|
|
sun4u_init:
|
2006-02-11 11:56:43 -07:00
|
|
|
BRANCH_IF_SUN4V(g1, sun4v_init)
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/* Set ctx 0 */
|
2006-02-07 23:13:05 -07:00
|
|
|
mov PRIMARY_CONTEXT, %g7
|
2006-02-11 11:56:43 -07:00
|
|
|
stxa %g0, [%g7] ASI_DMMU
|
2006-02-07 23:13:05 -07:00
|
|
|
membar #Sync
|
|
|
|
|
|
|
|
mov SECONDARY_CONTEXT, %g7
|
2006-02-11 11:56:43 -07:00
|
|
|
stxa %g0, [%g7] ASI_DMMU
|
|
|
|
membar #Sync
|
|
|
|
|
2016-04-27 15:27:37 -06:00
|
|
|
ba,a,pt %xcc, sun4u_continue
|
2006-02-07 23:13:05 -07:00
|
|
|
|
2006-02-11 11:56:43 -07:00
|
|
|
sun4v_init:
|
|
|
|
/* Set ctx 0 */
|
|
|
|
mov PRIMARY_CONTEXT, %g7
|
2006-02-07 23:13:05 -07:00
|
|
|
stxa %g0, [%g7] ASI_MMU
|
2006-02-11 11:56:43 -07:00
|
|
|
membar #Sync
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2006-02-11 11:56:43 -07:00
|
|
|
mov SECONDARY_CONTEXT, %g7
|
|
|
|
stxa %g0, [%g7] ASI_MMU
|
|
|
|
membar #Sync
|
2016-04-27 15:27:37 -06:00
|
|
|
ba,a,pt %xcc, niagara_tlb_fixup
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2006-02-11 11:56:43 -07:00
|
|
|
sun4u_continue:
|
2006-02-09 03:52:44 -07:00
|
|
|
BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2016-04-27 15:27:37 -06:00
|
|
|
ba,a,pt %xcc, spitfire_tlb_fixup
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2006-02-07 17:09:12 -07:00
|
|
|
niagara_tlb_fixup:
|
|
|
|
mov 3, %g2 /* Set TLB type to hypervisor. */
|
|
|
|
sethi %hi(tlb_type), %g1
|
|
|
|
stw %g2, [%g1 + %lo(tlb_type)]
|
|
|
|
|
|
|
|
/* Patch copy/clear ops. */
|
2007-08-08 18:11:39 -06:00
|
|
|
sethi %hi(sun4v_chip_type), %g1
|
|
|
|
lduw [%g1 + %lo(sun4v_chip_type)], %g1
|
|
|
|
cmp %g1, SUN4V_CHIP_NIAGARA1
|
|
|
|
be,pt %xcc, niagara_patch
|
|
|
|
cmp %g1, SUN4V_CHIP_NIAGARA2
|
2007-08-16 02:47:25 -06:00
|
|
|
be,pt %xcc, niagara2_patch
|
2007-08-08 18:11:39 -06:00
|
|
|
nop
|
sparc: Detect and handle UltraSPARC-T3 cpu types.
The cpu compatible string we look for is "SPARC-T3".
As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+. Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.
We use the Niagara-T2 perf support, since T3 is a close relative in
this regard. Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.
For now I haven't added any new ELF hwcap flags. We probably need
to add a couple, for example:
T2 and T3 both support the population count instruction in hardware.
T3 supports VIS3 instructions, including support (finally) for
partitioned shift. One can also now move directly between float
and integer registers.
T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply. Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.
T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.
So we'll need about 3 new elf capability flags in the end to represent
all of these things.
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-07-27 22:06:16 -06:00
|
|
|
cmp %g1, SUN4V_CHIP_NIAGARA3
|
2011-09-11 11:42:20 -06:00
|
|
|
be,pt %xcc, niagara2_patch
|
|
|
|
nop
|
|
|
|
cmp %g1, SUN4V_CHIP_NIAGARA4
|
2012-09-26 22:11:01 -06:00
|
|
|
be,pt %xcc, niagara4_patch
|
2011-09-11 11:42:20 -06:00
|
|
|
nop
|
|
|
|
cmp %g1, SUN4V_CHIP_NIAGARA5
|
2014-09-08 00:18:53 -06:00
|
|
|
be,pt %xcc, niagara4_patch
|
|
|
|
nop
|
|
|
|
cmp %g1, SUN4V_CHIP_SPARC_M6
|
|
|
|
be,pt %xcc, niagara4_patch
|
|
|
|
nop
|
|
|
|
cmp %g1, SUN4V_CHIP_SPARC_M7
|
2016-04-19 11:12:54 -06:00
|
|
|
be,pt %xcc, niagara4_patch
|
|
|
|
nop
|
|
|
|
cmp %g1, SUN4V_CHIP_SPARC_SN
|
2012-09-26 22:11:01 -06:00
|
|
|
be,pt %xcc, niagara4_patch
|
sparc: Detect and handle UltraSPARC-T3 cpu types.
The cpu compatible string we look for is "SPARC-T3".
As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+. Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.
We use the Niagara-T2 perf support, since T3 is a close relative in
this regard. Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.
For now I haven't added any new ELF hwcap flags. We probably need
to add a couple, for example:
T2 and T3 both support the population count instruction in hardware.
T3 supports VIS3 instructions, including support (finally) for
partitioned shift. One can also now move directly between float
and integer registers.
T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply. Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.
T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.
So we'll need about 3 new elf capability flags in the end to represent
all of these things.
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-07-27 22:06:16 -06:00
|
|
|
nop
|
2007-08-08 18:11:39 -06:00
|
|
|
|
|
|
|
call generic_patch_copyops
|
|
|
|
nop
|
|
|
|
call generic_patch_bzero
|
|
|
|
nop
|
|
|
|
call generic_patch_pageops
|
|
|
|
nop
|
|
|
|
|
|
|
|
ba,a,pt %xcc, 80f
|
arch/sparc: Avoid DCTI Couples
Avoid un-intended DCTI Couples. Use of DCTI couples is deprecated.
Also address the "Programming Note" for optimal performance.
Here is the complete text from Oracle SPARC Architecture Specs.
6.3.4.7 DCTI Couples
"A delayed control transfer instruction (DCTI) in the delay slot of
another DCTI is referred to as a “DCTI couple”. The use of DCTI couples
is deprecated in the Oracle SPARC Architecture; no new software should
place a DCTI in the delay slot of another DCTI, because on future Oracle
SPARC Architecture implementations DCTI couples may execute either
slowly or differently than the programmer assumes it will.
SPARC V8 and SPARC V9 Compatibility Note
The SPARC V8 architecture left behavior undefined for a DCTI couple. The
SPARC V9 architecture defined behavior in that case, but as of
UltraSPARC Architecture 2005, use of DCTI couples was deprecated.
Software should not expect high performance from DCTI couples, and
performance of DCTI couples should be expected to decline further in
future processors.
Programming Note
As noted in TABLE 6-5 on page 115, an annulled branch-always
(branch-always with a = 1) instruction is not architecturally a DCTI.
However, since not all implementations make that distinction, for
optimal performance, a DCTI should not be placed in the instruction word
immediately following an annulled branch-always instruction (BA,A or
BPA,A)."
Signed-off-by: Babu Moger <babu.moger@oracle.com>
Reviewed-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-17 14:52:21 -06:00
|
|
|
nop
|
2012-09-26 22:11:01 -06:00
|
|
|
niagara4_patch:
|
|
|
|
call niagara4_patch_copyops
|
|
|
|
nop
|
2012-10-05 14:45:26 -06:00
|
|
|
call niagara4_patch_bzero
|
2012-09-26 22:11:01 -06:00
|
|
|
nop
|
|
|
|
call niagara4_patch_pageops
|
|
|
|
nop
|
|
|
|
|
|
|
|
ba,a,pt %xcc, 80f
|
arch/sparc: Avoid DCTI Couples
Avoid un-intended DCTI Couples. Use of DCTI couples is deprecated.
Also address the "Programming Note" for optimal performance.
Here is the complete text from Oracle SPARC Architecture Specs.
6.3.4.7 DCTI Couples
"A delayed control transfer instruction (DCTI) in the delay slot of
another DCTI is referred to as a “DCTI couple”. The use of DCTI couples
is deprecated in the Oracle SPARC Architecture; no new software should
place a DCTI in the delay slot of another DCTI, because on future Oracle
SPARC Architecture implementations DCTI couples may execute either
slowly or differently than the programmer assumes it will.
SPARC V8 and SPARC V9 Compatibility Note
The SPARC V8 architecture left behavior undefined for a DCTI couple. The
SPARC V9 architecture defined behavior in that case, but as of
UltraSPARC Architecture 2005, use of DCTI couples was deprecated.
Software should not expect high performance from DCTI couples, and
performance of DCTI couples should be expected to decline further in
future processors.
Programming Note
As noted in TABLE 6-5 on page 115, an annulled branch-always
(branch-always with a = 1) instruction is not architecturally a DCTI.
However, since not all implementations make that distinction, for
optimal performance, a DCTI should not be placed in the instruction word
immediately following an annulled branch-always instruction (BA,A or
BPA,A)."
Signed-off-by: Babu Moger <babu.moger@oracle.com>
Reviewed-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-17 14:52:21 -06:00
|
|
|
nop
|
2012-09-26 22:11:01 -06:00
|
|
|
|
2007-08-16 02:47:25 -06:00
|
|
|
niagara2_patch:
|
|
|
|
call niagara2_patch_copyops
|
|
|
|
nop
|
|
|
|
call niagara_patch_bzero
|
|
|
|
nop
|
2011-08-01 19:18:57 -06:00
|
|
|
call niagara_patch_pageops
|
2007-08-16 02:47:25 -06:00
|
|
|
nop
|
|
|
|
|
|
|
|
ba,a,pt %xcc, 80f
|
arch/sparc: Avoid DCTI Couples
Avoid un-intended DCTI Couples. Use of DCTI couples is deprecated.
Also address the "Programming Note" for optimal performance.
Here is the complete text from Oracle SPARC Architecture Specs.
6.3.4.7 DCTI Couples
"A delayed control transfer instruction (DCTI) in the delay slot of
another DCTI is referred to as a “DCTI couple”. The use of DCTI couples
is deprecated in the Oracle SPARC Architecture; no new software should
place a DCTI in the delay slot of another DCTI, because on future Oracle
SPARC Architecture implementations DCTI couples may execute either
slowly or differently than the programmer assumes it will.
SPARC V8 and SPARC V9 Compatibility Note
The SPARC V8 architecture left behavior undefined for a DCTI couple. The
SPARC V9 architecture defined behavior in that case, but as of
UltraSPARC Architecture 2005, use of DCTI couples was deprecated.
Software should not expect high performance from DCTI couples, and
performance of DCTI couples should be expected to decline further in
future processors.
Programming Note
As noted in TABLE 6-5 on page 115, an annulled branch-always
(branch-always with a = 1) instruction is not architecturally a DCTI.
However, since not all implementations make that distinction, for
optimal performance, a DCTI should not be placed in the instruction word
immediately following an annulled branch-always instruction (BA,A or
BPA,A)."
Signed-off-by: Babu Moger <babu.moger@oracle.com>
Reviewed-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-17 14:52:21 -06:00
|
|
|
nop
|
2007-08-08 18:11:39 -06:00
|
|
|
|
|
|
|
niagara_patch:
|
2006-02-07 17:09:12 -07:00
|
|
|
call niagara_patch_copyops
|
|
|
|
nop
|
2006-02-21 15:29:42 -07:00
|
|
|
call niagara_patch_bzero
|
|
|
|
nop
|
2006-02-07 17:09:12 -07:00
|
|
|
call niagara_patch_pageops
|
|
|
|
nop
|
|
|
|
|
2007-08-08 18:11:39 -06:00
|
|
|
80:
|
2006-02-07 17:09:12 -07:00
|
|
|
/* Patch TLB/cache ops. */
|
|
|
|
call hypervisor_patch_cachetlbops
|
|
|
|
nop
|
|
|
|
|
2016-04-27 15:27:37 -06:00
|
|
|
ba,a,pt %xcc, tlb_fixup_done
|
2006-02-09 03:52:44 -07:00
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
cheetah_tlb_fixup:
|
|
|
|
mov 2, %g2 /* Set TLB type to cheetah+. */
|
|
|
|
BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
|
|
|
|
|
|
|
|
mov 1, %g2 /* Set TLB type to cheetah. */
|
|
|
|
|
|
|
|
1: sethi %hi(tlb_type), %g1
|
|
|
|
stw %g2, [%g1 + %lo(tlb_type)]
|
|
|
|
|
2005-10-04 16:23:20 -06:00
|
|
|
/* Patch copy/page operations to cheetah optimized versions. */
|
2005-04-16 16:20:36 -06:00
|
|
|
call cheetah_patch_copyops
|
|
|
|
nop
|
2005-08-30 12:26:15 -06:00
|
|
|
call cheetah_patch_copy_page
|
|
|
|
nop
|
2005-04-16 16:20:36 -06:00
|
|
|
call cheetah_patch_cachetlbops
|
|
|
|
nop
|
|
|
|
|
2016-04-27 15:27:37 -06:00
|
|
|
ba,a,pt %xcc, tlb_fixup_done
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
spitfire_tlb_fixup:
|
|
|
|
/* Set TLB type to spitfire. */
|
|
|
|
mov 0, %g2
|
|
|
|
sethi %hi(tlb_type), %g1
|
|
|
|
stw %g2, [%g1 + %lo(tlb_type)]
|
|
|
|
|
|
|
|
tlb_fixup_done:
|
|
|
|
sethi %hi(init_thread_union), %g6
|
|
|
|
or %g6, %lo(init_thread_union), %g6
|
|
|
|
ldx [%g6 + TI_TASK], %g4
|
|
|
|
|
|
|
|
wr %g0, ASI_P, %asi
|
|
|
|
mov 1, %g1
|
|
|
|
sllx %g1, THREAD_SHIFT, %g1
|
|
|
|
sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
|
|
|
|
add %g6, %g1, %sp
|
|
|
|
|
|
|
|
/* Set per-cpu pointer initially to zero, this makes
|
|
|
|
* the boot-cpu use the in-kernel-image per-cpu areas
|
|
|
|
* before setup_per_cpu_area() is invoked.
|
|
|
|
*/
|
|
|
|
clr %g5
|
|
|
|
|
|
|
|
wrpr %g0, 0, %wstate
|
|
|
|
wrpr %g0, 0x0, %tl
|
|
|
|
|
|
|
|
/* Clear the bss */
|
|
|
|
sethi %hi(__bss_start), %o0
|
|
|
|
or %o0, %lo(__bss_start), %o0
|
|
|
|
sethi %hi(_end), %o1
|
|
|
|
or %o1, %lo(_end), %o1
|
|
|
|
call __bzero
|
|
|
|
sub %o1, %o0, %o1
|
|
|
|
|
|
|
|
call prom_init
|
|
|
|
mov %l7, %o0 ! OpenPROM cif handler
|
|
|
|
|
2014-10-23 13:58:13 -06:00
|
|
|
/* To create a one-register-window buffer between the kernel's
|
|
|
|
* initial stack and the last stack frame we use from the firmware,
|
|
|
|
* do the rest of the boot from a C helper function.
|
2006-05-31 02:24:02 -06:00
|
|
|
*/
|
2014-10-23 13:58:13 -06:00
|
|
|
call start_early_boot
|
2005-04-16 16:20:36 -06:00
|
|
|
nop
|
|
|
|
/* Not reached... */
|
|
|
|
|
2007-07-24 16:17:33 -06:00
|
|
|
.previous
|
|
|
|
|
2005-10-10 17:12:13 -06:00
|
|
|
/* This is meant to allow the sharing of this code between
|
|
|
|
* boot processor invocation (via setup_tba() below) and
|
|
|
|
* secondary processor startup (via trampoline.S). The
|
|
|
|
* former does use this code, the latter does not yet due
|
|
|
|
* to some complexities. That should be fixed up at some
|
|
|
|
* point.
|
2005-10-12 13:22:46 -06:00
|
|
|
*
|
|
|
|
* There used to be enormous complexity wrt. transferring
|
2009-01-26 03:06:57 -07:00
|
|
|
* over from the firmware's trap table to the Linux kernel's.
|
2005-10-12 13:22:46 -06:00
|
|
|
* For example, there was a chicken & egg problem wrt. building
|
|
|
|
* the OBP page tables, yet needing to be on the Linux kernel
|
|
|
|
* trap table (to translate PAGE_OFFSET addresses) in order to
|
|
|
|
* do that.
|
|
|
|
*
|
|
|
|
* We now handle OBP tlb misses differently, via linear lookups
|
|
|
|
* into the prom_trans[] array. So that specific problem no
|
|
|
|
* longer exists. Yet, unfortunately there are still some issues
|
|
|
|
* preventing trampoline.S from using this code... ho hum.
|
2005-10-10 17:12:13 -06:00
|
|
|
*/
|
|
|
|
.globl setup_trap_table
|
|
|
|
setup_trap_table:
|
|
|
|
save %sp, -192, %sp
|
|
|
|
|
2005-10-12 13:22:46 -06:00
|
|
|
/* Force interrupts to be disabled. */
|
2006-07-13 17:05:26 -06:00
|
|
|
rdpr %pstate, %l0
|
|
|
|
andn %l0, PSTATE_IE, %o1
|
2005-10-10 17:12:13 -06:00
|
|
|
wrpr %o1, 0x0, %pstate
|
2006-07-13 17:05:26 -06:00
|
|
|
rdpr %pil, %l1
|
2008-11-23 22:55:29 -07:00
|
|
|
wrpr %g0, PIL_NORMAL_MAX, %pil
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2005-10-12 13:22:46 -06:00
|
|
|
/* Make the firmware call to jump over to the Linux trap table. */
|
2006-02-10 16:39:51 -07:00
|
|
|
sethi %hi(is_sun4v), %o0
|
|
|
|
lduw [%o0 + %lo(is_sun4v)], %o0
|
|
|
|
brz,pt %o0, 1f
|
|
|
|
nop
|
|
|
|
|
|
|
|
TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
|
|
|
|
add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
|
|
|
|
stxa %g2, [%g0] ASI_SCRATCHPAD
|
|
|
|
|
|
|
|
/* Compute physical address:
|
|
|
|
*
|
|
|
|
* paddr = kern_base + (mmfsa_vaddr - KERNBASE)
|
|
|
|
*/
|
|
|
|
sethi %hi(KERNBASE), %g3
|
|
|
|
sub %g2, %g3, %g2
|
|
|
|
sethi %hi(kern_base), %g3
|
|
|
|
ldx [%g3 + %lo(kern_base)], %g3
|
|
|
|
add %g2, %g3, %o1
|
2007-09-16 12:51:15 -06:00
|
|
|
sethi %hi(sparc64_ttable_tl0), %o0
|
2006-02-10 16:39:51 -07:00
|
|
|
|
2007-09-16 12:51:15 -06:00
|
|
|
set prom_set_trap_table_name, %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x00]
|
|
|
|
mov 2, %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x08]
|
|
|
|
mov 0, %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x10]
|
|
|
|
stx %o0, [%sp + 2047 + 128 + 0x18]
|
|
|
|
stx %o1, [%sp + 2047 + 128 + 0x20]
|
|
|
|
sethi %hi(p1275buf), %g2
|
|
|
|
or %g2, %lo(p1275buf), %g2
|
|
|
|
ldx [%g2 + 0x08], %o1
|
|
|
|
call %o1
|
|
|
|
add %sp, (2047 + 128), %o0
|
2006-02-10 16:39:51 -07:00
|
|
|
|
2016-04-27 15:27:37 -06:00
|
|
|
ba,a,pt %xcc, 2f
|
2006-02-10 16:39:51 -07:00
|
|
|
|
2007-09-16 12:51:15 -06:00
|
|
|
1: sethi %hi(sparc64_ttable_tl0), %o0
|
|
|
|
set prom_set_trap_table_name, %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x00]
|
|
|
|
mov 1, %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x08]
|
|
|
|
mov 0, %g2
|
|
|
|
stx %g2, [%sp + 2047 + 128 + 0x10]
|
|
|
|
stx %o0, [%sp + 2047 + 128 + 0x18]
|
|
|
|
sethi %hi(p1275buf), %g2
|
|
|
|
or %g2, %lo(p1275buf), %g2
|
|
|
|
ldx [%g2 + 0x08], %o1
|
|
|
|
call %o1
|
|
|
|
add %sp, (2047 + 128), %o0
|
2005-10-10 17:12:13 -06:00
|
|
|
|
|
|
|
/* Start using proper page size encodings in ctx register. */
|
2006-02-10 16:39:51 -07:00
|
|
|
2: sethi %hi(sparc64_kern_pri_context), %g3
|
2005-10-10 17:12:13 -06:00
|
|
|
ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
|
2006-02-07 23:13:05 -07:00
|
|
|
|
|
|
|
mov PRIMARY_CONTEXT, %g1
|
|
|
|
|
|
|
|
661: stxa %g2, [%g1] ASI_DMMU
|
|
|
|
.section .sun4v_1insn_patch, "ax"
|
|
|
|
.word 661b
|
|
|
|
stxa %g2, [%g1] ASI_MMU
|
|
|
|
.previous
|
|
|
|
|
2005-10-10 17:12:13 -06:00
|
|
|
membar #Sync
|
|
|
|
|
2007-08-16 02:52:44 -06:00
|
|
|
BRANCH_IF_SUN4V(o2, 1f)
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/* Kill PROM timer */
|
|
|
|
sethi %hi(0x80000000), %o2
|
|
|
|
sllx %o2, 32, %o2
|
|
|
|
wr %o2, 0, %tick_cmpr
|
|
|
|
|
2006-02-09 03:52:44 -07:00
|
|
|
BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2016-04-27 15:27:37 -06:00
|
|
|
ba,a,pt %xcc, 2f
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/* Disable STICK_INT interrupts. */
|
|
|
|
1:
|
|
|
|
sethi %hi(0x80000000), %o2
|
|
|
|
sllx %o2, 32, %o2
|
|
|
|
wr %o2, %asr25
|
|
|
|
|
|
|
|
2:
|
|
|
|
wrpr %g0, %g0, %wstate
|
|
|
|
|
|
|
|
call init_irqwork_curcpu
|
|
|
|
nop
|
|
|
|
|
2006-07-13 17:05:26 -06:00
|
|
|
/* Now we can restore interrupt state. */
|
|
|
|
wrpr %l0, 0, %pstate
|
|
|
|
wrpr %l1, 0x0, %pil
|
2005-10-10 17:12:13 -06:00
|
|
|
|
|
|
|
ret
|
|
|
|
restore
|
|
|
|
|
|
|
|
.globl setup_tba
|
2006-01-31 19:33:37 -07:00
|
|
|
setup_tba:
|
2005-10-10 17:12:13 -06:00
|
|
|
save %sp, -192, %sp
|
|
|
|
|
|
|
|
/* The boot processor is the only cpu which invokes this
|
|
|
|
* routine, the other cpus set things up via trampoline.S.
|
|
|
|
* So save the OBP trap table address here.
|
|
|
|
*/
|
|
|
|
rdpr %tba, %g7
|
|
|
|
sethi %hi(prom_tba), %o1
|
|
|
|
or %o1, %lo(prom_tba), %o1
|
|
|
|
stx %g7, [%o1]
|
|
|
|
|
|
|
|
call setup_trap_table
|
|
|
|
nop
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
ret
|
|
|
|
restore
|
2005-10-12 13:22:46 -06:00
|
|
|
sparc64_boot_end:
|
|
|
|
|
2008-12-03 04:11:52 -07:00
|
|
|
#include "etrap_64.S"
|
|
|
|
#include "rtrap_64.S"
|
2005-10-12 13:22:46 -06:00
|
|
|
#include "winfixup.S"
|
2008-04-28 01:47:20 -06:00
|
|
|
#include "fpu_traps.S"
|
|
|
|
#include "ivec.S"
|
|
|
|
#include "getsetcc.S"
|
|
|
|
#include "utrap.S"
|
|
|
|
#include "spiterrs.S"
|
|
|
|
#include "cherrs.S"
|
|
|
|
#include "misctrap.S"
|
|
|
|
#include "syscalls.S"
|
|
|
|
#include "helpers.S"
|
|
|
|
#include "hvcalls.S"
|
2006-02-08 03:53:50 -07:00
|
|
|
#include "sun4v_tlb_miss.S"
|
|
|
|
#include "sun4v_ivec.S"
|
2007-05-29 02:58:31 -06:00
|
|
|
#include "ktlb.S"
|
|
|
|
#include "tsb.S"
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/*
|
2005-10-12 13:22:46 -06:00
|
|
|
* The following skip makes sure the trap table in ttable.S is aligned
|
2005-04-16 16:20:36 -06:00
|
|
|
* on a 32K boundary as required by the v9 specs for TBA register.
|
2006-01-31 19:33:49 -07:00
|
|
|
*
|
|
|
|
* We align to a 32K boundary, then we have the 32K kernel TSB,
|
2007-05-29 02:58:31 -06:00
|
|
|
* the 64K kernel 4MB TSB, and then the 32K aligned trap table.
|
2005-04-16 16:20:36 -06:00
|
|
|
*/
|
2005-10-12 13:22:46 -06:00
|
|
|
1:
|
|
|
|
.skip 0x4000 + _start - 1b
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2007-05-29 02:58:31 -06:00
|
|
|
! 0x0000000000408000
|
|
|
|
|
2006-01-31 19:33:49 -07:00
|
|
|
.globl swapper_tsb
|
|
|
|
swapper_tsb:
|
|
|
|
.skip (32 * 1024)
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2007-05-29 02:58:31 -06:00
|
|
|
.globl swapper_4m_tsb
|
|
|
|
swapper_4m_tsb:
|
|
|
|
.skip (64 * 1024)
|
|
|
|
|
|
|
|
! 0x0000000000420000
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2007-05-29 02:58:31 -06:00
|
|
|
/* Some care needs to be exercised if you try to move the
|
|
|
|
* location of the trap table relative to other things. For
|
|
|
|
* one thing there are br* instructions in some of the
|
|
|
|
* trap table entires which branch back to code in ktlb.S
|
|
|
|
* Those instructions can only handle a signed 16-bit
|
|
|
|
* displacement.
|
|
|
|
*
|
|
|
|
* There is a binutils bug (bugzilla #4558) which causes
|
|
|
|
* the relocation overflow checks for such instructions to
|
|
|
|
* not be done correctly. So bintuils will not notice the
|
|
|
|
* error and will instead write junk into the relocation and
|
|
|
|
* you'll have an unbootable kernel.
|
|
|
|
*/
|
2012-05-19 14:02:44 -06:00
|
|
|
#include "ttable_64.S"
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2007-05-29 02:58:31 -06:00
|
|
|
! 0x0000000000428000
|
|
|
|
|
2008-12-03 04:11:52 -07:00
|
|
|
#include "systbls_64.S"
|
2006-02-23 03:28:25 -07:00
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
.data
|
|
|
|
.align 8
|
|
|
|
.globl prom_tba, tlb_type
|
|
|
|
prom_tba: .xword 0
|
|
|
|
tlb_type: .word 0 /* Must NOT end up in BSS */
|
2016-01-16 19:39:30 -07:00
|
|
|
EXPORT_SYMBOL(tlb_type)
|
2005-04-16 16:20:36 -06:00
|
|
|
.section ".fixup",#alloc,#execinstr
|
2005-09-28 21:41:45 -06:00
|
|
|
|
2009-02-08 23:00:55 -07:00
|
|
|
ENTRY(__retl_efault)
|
2005-09-28 21:41:45 -06:00
|
|
|
retl
|
|
|
|
mov -EFAULT, %o0
|
2009-02-08 23:00:55 -07:00
|
|
|
ENDPROC(__retl_efault)
|
|
|
|
|
|
|
|
ENTRY(__retl_o1)
|
|
|
|
retl
|
|
|
|
mov %o1, %o0
|
|
|
|
ENDPROC(__retl_o1)
|
2017-05-09 02:57:35 -06:00
|
|
|
|
|
|
|
ENTRY(__retl_o1_asi)
|
|
|
|
wr %o5, 0x0, %asi
|
|
|
|
retl
|
|
|
|
mov %o1, %o0
|
|
|
|
ENDPROC(__retl_o1_asi)
|