2006-02-04 01:10:01 -07:00
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/* winfixup.S: Handle cases where user stack pointer is found to be bogus.
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2005-04-16 16:20:36 -06:00
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*
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2006-02-04 01:10:01 -07:00
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* Copyright (C) 1997, 2006 David S. Miller (davem@davemloft.net)
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2005-04-16 16:20:36 -06:00
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*/
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#include <asm/asi.h>
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#include <asm/head.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/spitfire.h>
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#include <asm/thread_info.h>
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.text
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2006-02-04 01:10:01 -07:00
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/* It used to be the case that these register window fault
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* handlers could run via the save and restore instructions
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* done by the trap entry and exit code. They now do the
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* window spill/fill by hand, so that case no longer can occur.
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*/
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2005-04-16 16:20:36 -06:00
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.align 32
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fill_fixup:
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2006-02-02 22:55:10 -07:00
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TRAP_LOAD_THREAD_REG(%g6, %g1)
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2006-02-04 01:10:01 -07:00
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rdpr %tstate, %g1
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and %g1, TSTATE_CWP, %g1
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or %g4, FAULT_CODE_WINFIXUP, %g4
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stb %g4, [%g6 + TI_FAULT_CODE]
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stx %g5, [%g6 + TI_FAULT_ADDR]
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wrpr %g1, %cwp
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ba,pt %xcc, etrap
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rd %pc, %g7
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call do_sparc64_fault
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add %sp, PTREGS_OFF, %o0
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2016-04-27 15:27:37 -06:00
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ba,a,pt %xcc, rtrap
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2005-04-16 16:20:36 -06:00
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2006-02-04 01:10:01 -07:00
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/* Be very careful about usage of the trap globals here.
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* You cannot touch %g5 as that has the fault information.
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2005-04-16 16:20:36 -06:00
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*/
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spill_fixup:
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2006-02-04 01:10:01 -07:00
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spill_fixup_mna:
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spill_fixup_dax:
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2006-02-02 22:55:10 -07:00
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TRAP_LOAD_THREAD_REG(%g6, %g1)
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2006-02-04 01:10:01 -07:00
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ldx [%g6 + TI_FLAGS], %g1
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sparc64: Make montmul/montsqr/mpmul usable in 32-bit threads.
The Montgomery Multiply, Montgomery Square, and Multiple-Precision
Multiply instructions work by loading a combination of the floating
point and multiple register windows worth of integer registers
with the inputs.
These values are 64-bit. But for 32-bit userland processes we only
save the low 32-bits of each integer register during a register spill.
This is because the register window save area is in the user stack and
has a fixed layout.
Therefore, the only way to use these instruction in 32-bit mode is to
perform the following sequence:
1) Load the top-32bits of a choosen integer register with a sentinel,
say "-1". This will be in the outer-most register window.
The idea is that we're trying to see if the outer-most register
window gets spilled, and thus the 64-bit values were truncated.
2) Load all the inputs for the montmul/montsqr/mpmul instruction,
down to the inner-most register window.
3) Execute the opcode.
4) Traverse back up to the outer-most register window.
5) Check the sentinel, if it's still "-1" store the results.
Otherwise retry the entire sequence.
This retry is extremely troublesome. If you're just unlucky and an
interrupt or other trap happens, it'll push that outer-most window to
the stack and clear the sentinel when we restore it.
We could retry forever and never make forward progress if interrupts
arrive at a fast enough rate (consider perf events as one example).
So we have do limited retries and fallback to software which is
extremely non-deterministic.
Luckily it's very straightforward to provide a mechanism to let
32-bit applications use a 64-bit stack. Stacks in 64-bit mode are
biased by 2047 bytes, which means that the lowest bit is set in the
actual %sp register value.
So if we see bit zero set in a 32-bit application's stack we treat
it like a 64-bit stack.
Runtime detection of such a facility is tricky, and cumbersome at
best. For example, just trying to use a biased stack and seeing if it
works is hard to recover from (the signal handler will need to use an
alt stack, plus something along the lines of longjmp). Therefore, we
add a system call to report a bitmask of arch specific features like
this in a cheap and less hairy way.
With help from Andy Polyakov.
Signed-off-by: David S. Miller <davem@davemloft.net>
2012-10-26 16:18:37 -06:00
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andcc %sp, 0x1, %g0
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movne %icc, 0, %g1
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2006-02-04 01:10:01 -07:00
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andcc %g1, _TIF_32BIT, %g0
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ldub [%g6 + TI_WSAVED], %g1
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sll %g1, 3, %g3
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add %g6, %g3, %g3
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stx %sp, [%g3 + TI_RWIN_SPTRS]
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sll %g1, 7, %g3
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bne,pt %xcc, 1f
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add %g6, %g3, %g3
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stx %l0, [%g3 + TI_REG_WINDOW + 0x00]
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stx %l1, [%g3 + TI_REG_WINDOW + 0x08]
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stx %l2, [%g3 + TI_REG_WINDOW + 0x10]
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stx %l3, [%g3 + TI_REG_WINDOW + 0x18]
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stx %l4, [%g3 + TI_REG_WINDOW + 0x20]
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stx %l5, [%g3 + TI_REG_WINDOW + 0x28]
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stx %l6, [%g3 + TI_REG_WINDOW + 0x30]
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stx %l7, [%g3 + TI_REG_WINDOW + 0x38]
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stx %i0, [%g3 + TI_REG_WINDOW + 0x40]
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stx %i1, [%g3 + TI_REG_WINDOW + 0x48]
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stx %i2, [%g3 + TI_REG_WINDOW + 0x50]
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stx %i3, [%g3 + TI_REG_WINDOW + 0x58]
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stx %i4, [%g3 + TI_REG_WINDOW + 0x60]
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stx %i5, [%g3 + TI_REG_WINDOW + 0x68]
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stx %i6, [%g3 + TI_REG_WINDOW + 0x70]
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ba,pt %xcc, 2f
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stx %i7, [%g3 + TI_REG_WINDOW + 0x78]
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1: stw %l0, [%g3 + TI_REG_WINDOW + 0x00]
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stw %l1, [%g3 + TI_REG_WINDOW + 0x04]
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stw %l2, [%g3 + TI_REG_WINDOW + 0x08]
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stw %l3, [%g3 + TI_REG_WINDOW + 0x0c]
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stw %l4, [%g3 + TI_REG_WINDOW + 0x10]
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stw %l5, [%g3 + TI_REG_WINDOW + 0x14]
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stw %l6, [%g3 + TI_REG_WINDOW + 0x18]
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stw %l7, [%g3 + TI_REG_WINDOW + 0x1c]
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stw %i0, [%g3 + TI_REG_WINDOW + 0x20]
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stw %i1, [%g3 + TI_REG_WINDOW + 0x24]
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stw %i2, [%g3 + TI_REG_WINDOW + 0x28]
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stw %i3, [%g3 + TI_REG_WINDOW + 0x2c]
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stw %i4, [%g3 + TI_REG_WINDOW + 0x30]
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stw %i5, [%g3 + TI_REG_WINDOW + 0x34]
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stw %i6, [%g3 + TI_REG_WINDOW + 0x38]
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stw %i7, [%g3 + TI_REG_WINDOW + 0x3c]
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2: add %g1, 1, %g1
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stb %g1, [%g6 + TI_WSAVED]
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rdpr %tstate, %g1
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andcc %g1, TSTATE_PRIV, %g0
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2005-04-16 16:20:36 -06:00
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saved
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2006-02-04 01:10:01 -07:00
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be,pn %xcc, 1f
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and %g1, TSTATE_CWP, %g1
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2005-04-16 16:20:36 -06:00
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retry
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2006-02-04 01:10:01 -07:00
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1: mov FAULT_CODE_WRITE | FAULT_CODE_DTLB | FAULT_CODE_WINFIXUP, %g4
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stb %g4, [%g6 + TI_FAULT_CODE]
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stx %g5, [%g6 + TI_FAULT_ADDR]
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wrpr %g1, %cwp
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ba,pt %xcc, etrap
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rd %pc, %g7
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call do_sparc64_fault
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add %sp, PTREGS_OFF, %o0
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2008-04-24 04:15:22 -06:00
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ba,a,pt %xcc, rtrap
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2005-04-16 16:20:36 -06:00
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winfix_mna:
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2006-02-04 01:10:01 -07:00
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andn %g3, 0x7f, %g3
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add %g3, 0x78, %g3
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wrpr %g3, %tnpc
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2005-04-16 16:20:36 -06:00
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done
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2006-02-04 01:10:01 -07:00
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fill_fixup_mna:
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rdpr %tstate, %g1
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and %g1, TSTATE_CWP, %g1
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wrpr %g1, %cwp
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ba,pt %xcc, etrap
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rd %pc, %g7
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2006-02-09 21:20:34 -07:00
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sethi %hi(tlb_type), %g1
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lduw [%g1 + %lo(tlb_type)], %g1
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cmp %g1, 3
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bne,pt %icc, 1f
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2006-02-04 01:10:01 -07:00
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add %sp, PTREGS_OFF, %o0
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2006-02-18 17:39:39 -07:00
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mov %l4, %o2
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2006-02-16 02:45:49 -07:00
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call sun4v_do_mna
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2006-02-18 17:39:39 -07:00
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mov %l5, %o1
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2008-04-24 04:15:22 -06:00
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ba,a,pt %xcc, rtrap
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2006-02-18 17:39:39 -07:00
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1: mov %l4, %o1
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mov %l5, %o2
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call mem_address_unaligned
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2006-02-09 21:20:34 -07:00
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nop
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2008-04-24 04:15:22 -06:00
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ba,a,pt %xcc, rtrap
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2005-04-16 16:20:36 -06:00
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winfix_dax:
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2006-02-04 01:10:01 -07:00
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andn %g3, 0x7f, %g3
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add %g3, 0x74, %g3
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wrpr %g3, %tnpc
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2005-04-16 16:20:36 -06:00
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done
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2006-02-04 01:10:01 -07:00
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fill_fixup_dax:
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rdpr %tstate, %g1
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and %g1, TSTATE_CWP, %g1
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wrpr %g1, %cwp
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ba,pt %xcc, etrap
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rd %pc, %g7
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2006-02-09 21:20:34 -07:00
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sethi %hi(tlb_type), %g1
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2006-02-04 01:10:01 -07:00
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mov %l4, %o1
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2006-02-09 21:20:34 -07:00
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lduw [%g1 + %lo(tlb_type)], %g1
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2006-02-04 01:10:01 -07:00
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mov %l5, %o2
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2006-02-09 21:20:34 -07:00
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cmp %g1, 3
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bne,pt %icc, 1f
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2006-02-04 01:10:01 -07:00
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add %sp, PTREGS_OFF, %o0
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2006-02-09 21:20:34 -07:00
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call sun4v_data_access_exception
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nop
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2008-04-24 04:15:22 -06:00
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ba,a,pt %xcc, rtrap
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arch/sparc: Avoid DCTI Couples
Avoid un-intended DCTI Couples. Use of DCTI couples is deprecated.
Also address the "Programming Note" for optimal performance.
Here is the complete text from Oracle SPARC Architecture Specs.
6.3.4.7 DCTI Couples
"A delayed control transfer instruction (DCTI) in the delay slot of
another DCTI is referred to as a “DCTI couple”. The use of DCTI couples
is deprecated in the Oracle SPARC Architecture; no new software should
place a DCTI in the delay slot of another DCTI, because on future Oracle
SPARC Architecture implementations DCTI couples may execute either
slowly or differently than the programmer assumes it will.
SPARC V8 and SPARC V9 Compatibility Note
The SPARC V8 architecture left behavior undefined for a DCTI couple. The
SPARC V9 architecture defined behavior in that case, but as of
UltraSPARC Architecture 2005, use of DCTI couples was deprecated.
Software should not expect high performance from DCTI couples, and
performance of DCTI couples should be expected to decline further in
future processors.
Programming Note
As noted in TABLE 6-5 on page 115, an annulled branch-always
(branch-always with a = 1) instruction is not architecturally a DCTI.
However, since not all implementations make that distinction, for
optimal performance, a DCTI should not be placed in the instruction word
immediately following an annulled branch-always instruction (BA,A or
BPA,A)."
Signed-off-by: Babu Moger <babu.moger@oracle.com>
Reviewed-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-17 14:52:21 -06:00
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nop
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2006-02-09 21:20:34 -07:00
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1: call spitfire_data_access_exception
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nop
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2008-04-24 04:15:22 -06:00
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ba,a,pt %xcc, rtrap
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arch/sparc: Avoid DCTI Couples
Avoid un-intended DCTI Couples. Use of DCTI couples is deprecated.
Also address the "Programming Note" for optimal performance.
Here is the complete text from Oracle SPARC Architecture Specs.
6.3.4.7 DCTI Couples
"A delayed control transfer instruction (DCTI) in the delay slot of
another DCTI is referred to as a “DCTI couple”. The use of DCTI couples
is deprecated in the Oracle SPARC Architecture; no new software should
place a DCTI in the delay slot of another DCTI, because on future Oracle
SPARC Architecture implementations DCTI couples may execute either
slowly or differently than the programmer assumes it will.
SPARC V8 and SPARC V9 Compatibility Note
The SPARC V8 architecture left behavior undefined for a DCTI couple. The
SPARC V9 architecture defined behavior in that case, but as of
UltraSPARC Architecture 2005, use of DCTI couples was deprecated.
Software should not expect high performance from DCTI couples, and
performance of DCTI couples should be expected to decline further in
future processors.
Programming Note
As noted in TABLE 6-5 on page 115, an annulled branch-always
(branch-always with a = 1) instruction is not architecturally a DCTI.
However, since not all implementations make that distinction, for
optimal performance, a DCTI should not be placed in the instruction word
immediately following an annulled branch-always instruction (BA,A or
BPA,A)."
Signed-off-by: Babu Moger <babu.moger@oracle.com>
Reviewed-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-03-17 14:52:21 -06:00
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nop
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