2008-11-12 14:27:09 -07:00
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/*
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* drivers/w1/masters/omap_hdq.c
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*
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2012-06-21 21:40:40 -06:00
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* Copyright (C) 2007,2012 Texas Instruments, Inc.
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2008-11-12 14:27:09 -07:00
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2008-11-12 14:27:09 -07:00
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#include <linux/err.h>
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#include <linux/io.h>
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2010-04-23 11:18:03 -06:00
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#include <linux/sched.h>
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2012-06-21 21:40:40 -06:00
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#include <linux/pm_runtime.h>
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2015-09-14 11:54:33 -06:00
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#include <linux/of.h>
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2008-11-12 14:27:09 -07:00
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#include "../w1.h"
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#include "../w1_int.h"
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#define MOD_NAME "OMAP_HDQ:"
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#define OMAP_HDQ_REVISION 0x00
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#define OMAP_HDQ_TX_DATA 0x04
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#define OMAP_HDQ_RX_DATA 0x08
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#define OMAP_HDQ_CTRL_STATUS 0x0c
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2015-09-14 11:54:33 -06:00
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#define OMAP_HDQ_CTRL_STATUS_SINGLE BIT(7)
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#define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK BIT(6)
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#define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE BIT(5)
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#define OMAP_HDQ_CTRL_STATUS_GO BIT(4)
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#define OMAP_HDQ_CTRL_STATUS_PRESENCE BIT(3)
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#define OMAP_HDQ_CTRL_STATUS_INITIALIZATION BIT(2)
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#define OMAP_HDQ_CTRL_STATUS_DIR BIT(1)
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2008-11-12 14:27:09 -07:00
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#define OMAP_HDQ_INT_STATUS 0x10
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2015-09-14 11:54:33 -06:00
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#define OMAP_HDQ_INT_STATUS_TXCOMPLETE BIT(2)
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#define OMAP_HDQ_INT_STATUS_RXCOMPLETE BIT(1)
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#define OMAP_HDQ_INT_STATUS_TIMEOUT BIT(0)
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2008-11-12 14:27:09 -07:00
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#define OMAP_HDQ_SYSCONFIG 0x14
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2015-09-14 11:54:33 -06:00
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#define OMAP_HDQ_SYSCONFIG_SOFTRESET BIT(1)
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#define OMAP_HDQ_SYSCONFIG_AUTOIDLE BIT(0)
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#define OMAP_HDQ_SYSCONFIG_NOIDLE 0x0
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2008-11-12 14:27:09 -07:00
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#define OMAP_HDQ_SYSSTATUS 0x18
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2015-09-14 11:54:33 -06:00
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#define OMAP_HDQ_SYSSTATUS_RESETDONE BIT(0)
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2008-11-12 14:27:09 -07:00
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#define OMAP_HDQ_FLAG_CLEAR 0
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#define OMAP_HDQ_FLAG_SET 1
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#define OMAP_HDQ_TIMEOUT (HZ/5)
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#define OMAP_HDQ_MAX_USER 4
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static DECLARE_WAIT_QUEUE_HEAD(hdq_wait_queue);
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static int w1_id;
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struct hdq_data {
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struct device *dev;
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void __iomem *hdq_base;
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/* lock status update */
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struct mutex hdq_mutex;
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int hdq_usecount;
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u8 hdq_irqstatus;
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/* device lock */
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spinlock_t hdq_spinlock;
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/*
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* Used to control the call to omap_hdq_get and omap_hdq_put.
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* HDQ Protocol: Write the CMD|REG_address first, followed by
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* the data wrire or read.
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*/
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int init_trans;
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2015-09-14 11:54:33 -06:00
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int rrw;
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/* mode: 0-HDQ 1-W1 */
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int mode;
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2008-11-12 14:27:09 -07:00
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};
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2012-11-19 11:21:43 -07:00
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static int omap_hdq_probe(struct platform_device *pdev);
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2012-11-19 11:26:23 -07:00
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static int omap_hdq_remove(struct platform_device *pdev);
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2008-11-12 14:27:09 -07:00
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2015-03-16 13:20:29 -06:00
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static const struct of_device_id omap_hdq_dt_ids[] = {
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2014-11-07 16:30:32 -07:00
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{ .compatible = "ti,omap3-1w" },
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2015-09-14 11:54:33 -06:00
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{ .compatible = "ti,am4372-hdq" },
|
2014-11-07 16:30:32 -07:00
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{}
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};
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MODULE_DEVICE_TABLE(of, omap_hdq_dt_ids);
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2008-11-12 14:27:09 -07:00
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static struct platform_driver omap_hdq_driver = {
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.probe = omap_hdq_probe,
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2012-11-19 11:21:14 -07:00
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.remove = omap_hdq_remove,
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2008-11-12 14:27:09 -07:00
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.driver = {
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.name = "omap_hdq",
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2014-11-07 16:30:32 -07:00
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.of_match_table = omap_hdq_dt_ids,
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2008-11-12 14:27:09 -07:00
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},
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};
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static u8 omap_w1_read_byte(void *_hdq);
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static void omap_w1_write_byte(void *_hdq, u8 byte);
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static u8 omap_w1_reset_bus(void *_hdq);
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static struct w1_bus_master omap_w1_master = {
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.read_byte = omap_w1_read_byte,
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.write_byte = omap_w1_write_byte,
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.reset_bus = omap_w1_reset_bus,
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};
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/* HDQ register I/O routines */
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static inline u8 hdq_reg_in(struct hdq_data *hdq_data, u32 offset)
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{
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2012-06-21 21:40:37 -06:00
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return __raw_readl(hdq_data->hdq_base + offset);
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2008-11-12 14:27:09 -07:00
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}
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static inline void hdq_reg_out(struct hdq_data *hdq_data, u32 offset, u8 val)
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{
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2012-06-21 21:40:37 -06:00
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__raw_writel(val, hdq_data->hdq_base + offset);
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2008-11-12 14:27:09 -07:00
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}
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static inline u8 hdq_reg_merge(struct hdq_data *hdq_data, u32 offset,
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u8 val, u8 mask)
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{
|
2012-06-21 21:40:37 -06:00
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u8 new_val = (__raw_readl(hdq_data->hdq_base + offset) & ~mask)
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2008-11-12 14:27:09 -07:00
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| (val & mask);
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2012-06-21 21:40:37 -06:00
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__raw_writel(new_val, hdq_data->hdq_base + offset);
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2008-11-12 14:27:09 -07:00
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return new_val;
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}
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|
2015-09-14 11:54:33 -06:00
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static void hdq_disable_interrupt(struct hdq_data *hdq_data, u32 offset,
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u32 mask)
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{
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u32 ie;
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ie = readl(hdq_data->hdq_base + offset);
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writel(ie & mask, hdq_data->hdq_base + offset);
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}
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|
2008-11-12 14:27:09 -07:00
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/*
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* Wait for one or more bits in flag change.
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* HDQ_FLAG_SET: wait until any bit in the flag is set.
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* HDQ_FLAG_CLEAR: wait until all bits in the flag are cleared.
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* return 0 on success and -ETIMEDOUT in the case of timeout.
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*/
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static int hdq_wait_for_flag(struct hdq_data *hdq_data, u32 offset,
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u8 flag, u8 flag_set, u8 *status)
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{
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int ret = 0;
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unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
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if (flag_set == OMAP_HDQ_FLAG_CLEAR) {
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/* wait for the flag clear */
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while (((*status = hdq_reg_in(hdq_data, offset)) & flag)
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&& time_before(jiffies, timeout)) {
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schedule_timeout_uninterruptible(1);
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}
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if (*status & flag)
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ret = -ETIMEDOUT;
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} else if (flag_set == OMAP_HDQ_FLAG_SET) {
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/* wait for the flag set */
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while (!((*status = hdq_reg_in(hdq_data, offset)) & flag)
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&& time_before(jiffies, timeout)) {
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schedule_timeout_uninterruptible(1);
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}
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if (!(*status & flag))
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ret = -ETIMEDOUT;
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} else
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return -EINVAL;
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return ret;
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}
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/* write out a byte and fill *status with HDQ_INT_STATUS */
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static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status)
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{
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int ret;
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u8 tmp_status;
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unsigned long irqflags;
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*status = 0;
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spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
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/* clear interrupt flags via a dummy read */
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hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
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|
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/* ISR loads it with new INT_STATUS */
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hdq_data->hdq_irqstatus = 0;
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spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
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hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val);
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/* set the GO bit */
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hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO,
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OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
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|
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/* wait for the TXCOMPLETE bit */
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ret = wait_event_timeout(hdq_wait_queue,
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hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
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if (ret == 0) {
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dev_dbg(hdq_data->dev, "TX wait elapsed\n");
|
2012-05-21 17:43:02 -06:00
|
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ret = -ETIMEDOUT;
|
2008-11-12 14:27:09 -07:00
|
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goto out;
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}
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*status = hdq_data->hdq_irqstatus;
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/* check irqstatus */
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if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) {
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|
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dev_dbg(hdq_data->dev, "timeout waiting for"
|
2012-05-21 17:43:02 -06:00
|
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|
" TXCOMPLETE/RXCOMPLETE, %x", *status);
|
2008-11-12 14:27:09 -07:00
|
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ret = -ETIMEDOUT;
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goto out;
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}
|
|
|
|
|
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|
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/* wait for the GO bit return to zero */
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ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
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|
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OMAP_HDQ_CTRL_STATUS_GO,
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OMAP_HDQ_FLAG_CLEAR, &tmp_status);
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if (ret) {
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|
|
|
dev_dbg(hdq_data->dev, "timeout waiting GO bit"
|
2012-05-21 17:43:02 -06:00
|
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" return to zero, %x", tmp_status);
|
2008-11-12 14:27:09 -07:00
|
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}
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out:
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return ret;
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|
|
|
}
|
|
|
|
|
|
|
|
/* HDQ Interrupt service routine */
|
|
|
|
static irqreturn_t hdq_isr(int irq, void *_hdq)
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|
|
{
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|
struct hdq_data *hdq_data = _hdq;
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unsigned long irqflags;
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|
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spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
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hdq_data->hdq_irqstatus = hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
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|
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spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
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|
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dev_dbg(hdq_data->dev, "hdq_isr: %x", hdq_data->hdq_irqstatus);
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if (hdq_data->hdq_irqstatus &
|
|
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(OMAP_HDQ_INT_STATUS_TXCOMPLETE | OMAP_HDQ_INT_STATUS_RXCOMPLETE
|
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|
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| OMAP_HDQ_INT_STATUS_TIMEOUT)) {
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|
|
/* wake up sleeping process */
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|
|
wake_up(&hdq_wait_queue);
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|
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}
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|
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|
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|
|
|
return IRQ_HANDLED;
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|
|
}
|
|
|
|
|
2015-09-14 11:54:33 -06:00
|
|
|
/* W1 search callback function in HDQ mode */
|
2008-11-19 16:36:50 -07:00
|
|
|
static void omap_w1_search_bus(void *_hdq, struct w1_master *master_dev,
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|
|
u8 search_type, w1_slave_found_callback slave_found)
|
2008-11-12 14:27:09 -07:00
|
|
|
{
|
|
|
|
u64 module_id, rn_le, cs, id;
|
|
|
|
|
|
|
|
if (w1_id)
|
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|
|
module_id = w1_id;
|
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|
|
else
|
|
|
|
module_id = 0x1;
|
|
|
|
|
|
|
|
rn_le = cpu_to_le64(module_id);
|
|
|
|
/*
|
|
|
|
* HDQ might not obey truly the 1-wire spec.
|
|
|
|
* So calculate CRC based on module parameter.
|
|
|
|
*/
|
|
|
|
cs = w1_calc_crc8((u8 *)&rn_le, 7);
|
|
|
|
id = (cs << 56) | module_id;
|
|
|
|
|
2008-11-19 16:36:50 -07:00
|
|
|
slave_found(master_dev, id);
|
2008-11-12 14:27:09 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int _omap_hdq_reset(struct hdq_data *hdq_data)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
u8 tmp_status;
|
|
|
|
|
2015-09-14 11:54:33 -06:00
|
|
|
hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
|
|
|
|
OMAP_HDQ_SYSCONFIG_SOFTRESET);
|
2008-11-12 14:27:09 -07:00
|
|
|
/*
|
2015-09-14 11:54:33 -06:00
|
|
|
* Select HDQ/1W mode & enable clocks.
|
2008-11-12 14:27:09 -07:00
|
|
|
* It is observed that INT flags can't be cleared via a read and GO/INIT
|
|
|
|
* won't return to zero if interrupt is disabled. So we always enable
|
|
|
|
* interrupt.
|
|
|
|
*/
|
|
|
|
hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
|
|
|
|
OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
|
|
|
|
OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
|
|
|
|
|
|
|
|
/* wait for reset to complete */
|
|
|
|
ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_SYSSTATUS,
|
|
|
|
OMAP_HDQ_SYSSTATUS_RESETDONE, OMAP_HDQ_FLAG_SET, &tmp_status);
|
|
|
|
if (ret)
|
|
|
|
dev_dbg(hdq_data->dev, "timeout waiting HDQ reset, %x",
|
|
|
|
tmp_status);
|
|
|
|
else {
|
|
|
|
hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
|
|
|
|
OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
|
2015-09-14 11:54:33 -06:00
|
|
|
OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK |
|
|
|
|
hdq_data->mode);
|
2008-11-12 14:27:09 -07:00
|
|
|
hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
|
|
|
|
OMAP_HDQ_SYSCONFIG_AUTOIDLE);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Issue break pulse to the device */
|
|
|
|
static int omap_hdq_break(struct hdq_data *hdq_data)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
u8 tmp_status;
|
|
|
|
unsigned long irqflags;
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
|
|
|
|
ret = -EINTR;
|
|
|
|
goto rtn;
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
|
|
|
|
/* clear interrupt flags via a dummy read */
|
|
|
|
hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
|
|
|
|
/* ISR loads it with new INT_STATUS */
|
|
|
|
hdq_data->hdq_irqstatus = 0;
|
|
|
|
spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
|
|
|
|
|
|
|
|
/* set the INIT and GO bit */
|
|
|
|
hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
|
|
|
|
OMAP_HDQ_CTRL_STATUS_INITIALIZATION | OMAP_HDQ_CTRL_STATUS_GO,
|
|
|
|
OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
|
|
|
|
OMAP_HDQ_CTRL_STATUS_GO);
|
|
|
|
|
|
|
|
/* wait for the TIMEOUT bit */
|
|
|
|
ret = wait_event_timeout(hdq_wait_queue,
|
|
|
|
hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
|
|
|
|
if (ret == 0) {
|
|
|
|
dev_dbg(hdq_data->dev, "break wait elapsed\n");
|
|
|
|
ret = -EINTR;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
tmp_status = hdq_data->hdq_irqstatus;
|
|
|
|
/* check irqstatus */
|
|
|
|
if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) {
|
|
|
|
dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x",
|
|
|
|
tmp_status);
|
|
|
|
ret = -ETIMEDOUT;
|
|
|
|
goto out;
|
|
|
|
}
|
2015-09-14 11:54:33 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* check for the presence detect bit to get
|
|
|
|
* set to show that the slave is responding
|
|
|
|
*/
|
|
|
|
if (!(hdq_reg_in(hdq_data, OMAP_HDQ_CTRL_STATUS) &
|
|
|
|
OMAP_HDQ_CTRL_STATUS_PRESENCE)) {
|
|
|
|
dev_dbg(hdq_data->dev, "Presence bit not set\n");
|
|
|
|
ret = -ETIMEDOUT;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2008-11-12 14:27:09 -07:00
|
|
|
/*
|
|
|
|
* wait for both INIT and GO bits rerurn to zero.
|
|
|
|
* zero wait time expected for interrupt mode.
|
|
|
|
*/
|
|
|
|
ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
|
|
|
|
OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
|
|
|
|
OMAP_HDQ_CTRL_STATUS_GO, OMAP_HDQ_FLAG_CLEAR,
|
|
|
|
&tmp_status);
|
|
|
|
if (ret)
|
|
|
|
dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits"
|
2012-05-21 17:43:02 -06:00
|
|
|
" return to zero, %x", tmp_status);
|
2008-11-12 14:27:09 -07:00
|
|
|
|
|
|
|
out:
|
|
|
|
mutex_unlock(&hdq_data->hdq_mutex);
|
|
|
|
rtn:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
u8 status;
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
|
|
|
|
if (ret < 0) {
|
|
|
|
ret = -EINTR;
|
|
|
|
goto rtn;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!hdq_data->hdq_usecount) {
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
|
|
|
|
hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
|
|
|
|
OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO,
|
|
|
|
OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
|
|
|
|
/*
|
2012-05-21 17:43:02 -06:00
|
|
|
* The RX comes immediately after TX.
|
2008-11-12 14:27:09 -07:00
|
|
|
*/
|
2012-05-21 17:43:02 -06:00
|
|
|
wait_event_timeout(hdq_wait_queue,
|
|
|
|
(hdq_data->hdq_irqstatus
|
|
|
|
& OMAP_HDQ_INT_STATUS_RXCOMPLETE),
|
|
|
|
OMAP_HDQ_TIMEOUT);
|
|
|
|
|
2008-11-12 14:27:09 -07:00
|
|
|
hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0,
|
|
|
|
OMAP_HDQ_CTRL_STATUS_DIR);
|
|
|
|
status = hdq_data->hdq_irqstatus;
|
|
|
|
/* check irqstatus */
|
|
|
|
if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
|
|
|
|
dev_dbg(hdq_data->dev, "timeout waiting for"
|
2012-05-21 17:43:02 -06:00
|
|
|
" RXCOMPLETE, %x", status);
|
2008-11-12 14:27:09 -07:00
|
|
|
ret = -ETIMEDOUT;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* the data is ready. Read it in! */
|
|
|
|
*val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA);
|
|
|
|
out:
|
|
|
|
mutex_unlock(&hdq_data->hdq_mutex);
|
|
|
|
rtn:
|
2012-05-21 17:43:02 -06:00
|
|
|
return ret;
|
2008-11-12 14:27:09 -07:00
|
|
|
|
|
|
|
}
|
|
|
|
|
2015-09-14 11:54:33 -06:00
|
|
|
/* Enable clocks and set the controller to HDQ/1W mode */
|
2008-11-12 14:27:09 -07:00
|
|
|
static int omap_hdq_get(struct hdq_data *hdq_data)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
|
|
|
|
if (ret < 0) {
|
|
|
|
ret = -EINTR;
|
|
|
|
goto rtn;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (OMAP_HDQ_MAX_USER == hdq_data->hdq_usecount) {
|
|
|
|
dev_dbg(hdq_data->dev, "attempt to exceed the max use count");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto out;
|
|
|
|
} else {
|
|
|
|
hdq_data->hdq_usecount++;
|
|
|
|
try_module_get(THIS_MODULE);
|
|
|
|
if (1 == hdq_data->hdq_usecount) {
|
2012-06-21 21:40:40 -06:00
|
|
|
|
|
|
|
pm_runtime_get_sync(hdq_data->dev);
|
2008-11-12 14:27:09 -07:00
|
|
|
|
2015-09-14 11:54:33 -06:00
|
|
|
/* make sure HDQ/1W is out of reset */
|
2008-11-12 14:27:09 -07:00
|
|
|
if (!(hdq_reg_in(hdq_data, OMAP_HDQ_SYSSTATUS) &
|
|
|
|
OMAP_HDQ_SYSSTATUS_RESETDONE)) {
|
|
|
|
ret = _omap_hdq_reset(hdq_data);
|
|
|
|
if (ret)
|
|
|
|
/* back up the count */
|
|
|
|
hdq_data->hdq_usecount--;
|
|
|
|
} else {
|
2015-09-14 11:54:33 -06:00
|
|
|
/* select HDQ/1W mode & enable clocks */
|
2008-11-12 14:27:09 -07:00
|
|
|
hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
|
|
|
|
OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
|
2015-09-14 11:54:33 -06:00
|
|
|
OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK |
|
|
|
|
hdq_data->mode);
|
2008-11-12 14:27:09 -07:00
|
|
|
hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
|
2015-09-14 11:54:33 -06:00
|
|
|
OMAP_HDQ_SYSCONFIG_NOIDLE);
|
2008-11-12 14:27:09 -07:00
|
|
|
hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
|
|
|
mutex_unlock(&hdq_data->hdq_mutex);
|
|
|
|
rtn:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Disable clocks to the module */
|
|
|
|
static int omap_hdq_put(struct hdq_data *hdq_data)
|
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
|
|
|
|
if (ret < 0)
|
|
|
|
return -EINTR;
|
|
|
|
|
2015-09-14 11:54:33 -06:00
|
|
|
hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
|
|
|
|
OMAP_HDQ_SYSCONFIG_AUTOIDLE);
|
2008-11-12 14:27:09 -07:00
|
|
|
if (0 == hdq_data->hdq_usecount) {
|
|
|
|
dev_dbg(hdq_data->dev, "attempt to decrement use count"
|
2012-05-21 17:43:02 -06:00
|
|
|
" when it is zero");
|
2008-11-12 14:27:09 -07:00
|
|
|
ret = -EINVAL;
|
|
|
|
} else {
|
|
|
|
hdq_data->hdq_usecount--;
|
|
|
|
module_put(THIS_MODULE);
|
2012-06-21 21:40:40 -06:00
|
|
|
if (0 == hdq_data->hdq_usecount)
|
|
|
|
pm_runtime_put_sync(hdq_data->dev);
|
2008-11-12 14:27:09 -07:00
|
|
|
}
|
|
|
|
mutex_unlock(&hdq_data->hdq_mutex);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-09-14 11:54:33 -06:00
|
|
|
/*
|
|
|
|
* W1 triplet callback function - used for searching ROM addresses.
|
|
|
|
* Registered only when controller is in 1-wire mode.
|
|
|
|
*/
|
|
|
|
static u8 omap_w1_triplet(void *_hdq, u8 bdir)
|
|
|
|
{
|
|
|
|
u8 id_bit, comp_bit;
|
|
|
|
int err;
|
|
|
|
u8 ret = 0x3; /* no slaves responded */
|
|
|
|
struct hdq_data *hdq_data = _hdq;
|
|
|
|
u8 ctrl = OMAP_HDQ_CTRL_STATUS_SINGLE | OMAP_HDQ_CTRL_STATUS_GO |
|
|
|
|
OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK;
|
|
|
|
u8 mask = ctrl | OMAP_HDQ_CTRL_STATUS_DIR;
|
|
|
|
|
|
|
|
omap_hdq_get(_hdq);
|
|
|
|
|
|
|
|
err = mutex_lock_interruptible(&hdq_data->hdq_mutex);
|
|
|
|
if (err < 0) {
|
|
|
|
dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
|
|
|
|
goto rtn;
|
|
|
|
}
|
|
|
|
|
|
|
|
hdq_data->hdq_irqstatus = 0;
|
|
|
|
/* read id_bit */
|
|
|
|
hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS,
|
|
|
|
ctrl | OMAP_HDQ_CTRL_STATUS_DIR, mask);
|
|
|
|
err = wait_event_timeout(hdq_wait_queue,
|
|
|
|
(hdq_data->hdq_irqstatus
|
|
|
|
& OMAP_HDQ_INT_STATUS_RXCOMPLETE),
|
|
|
|
OMAP_HDQ_TIMEOUT);
|
|
|
|
if (err == 0) {
|
|
|
|
dev_dbg(hdq_data->dev, "RX wait elapsed\n");
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
id_bit = (hdq_reg_in(_hdq, OMAP_HDQ_RX_DATA) & 0x01);
|
|
|
|
|
|
|
|
hdq_data->hdq_irqstatus = 0;
|
|
|
|
/* read comp_bit */
|
|
|
|
hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS,
|
|
|
|
ctrl | OMAP_HDQ_CTRL_STATUS_DIR, mask);
|
|
|
|
err = wait_event_timeout(hdq_wait_queue,
|
|
|
|
(hdq_data->hdq_irqstatus
|
|
|
|
& OMAP_HDQ_INT_STATUS_RXCOMPLETE),
|
|
|
|
OMAP_HDQ_TIMEOUT);
|
|
|
|
if (err == 0) {
|
|
|
|
dev_dbg(hdq_data->dev, "RX wait elapsed\n");
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
comp_bit = (hdq_reg_in(_hdq, OMAP_HDQ_RX_DATA) & 0x01);
|
|
|
|
|
|
|
|
if (id_bit && comp_bit) {
|
|
|
|
ret = 0x03; /* no slaves responded */
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
if (!id_bit && !comp_bit) {
|
|
|
|
/* Both bits are valid, take the direction given */
|
|
|
|
ret = bdir ? 0x04 : 0;
|
|
|
|
} else {
|
|
|
|
/* Only one bit is valid, take that direction */
|
|
|
|
bdir = id_bit;
|
|
|
|
ret = id_bit ? 0x05 : 0x02;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* write bdir bit */
|
|
|
|
hdq_reg_out(_hdq, OMAP_HDQ_TX_DATA, bdir);
|
|
|
|
hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS, ctrl, mask);
|
|
|
|
err = wait_event_timeout(hdq_wait_queue,
|
|
|
|
(hdq_data->hdq_irqstatus
|
|
|
|
& OMAP_HDQ_INT_STATUS_TXCOMPLETE),
|
|
|
|
OMAP_HDQ_TIMEOUT);
|
|
|
|
if (err == 0) {
|
|
|
|
dev_dbg(hdq_data->dev, "TX wait elapsed\n");
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS, 0,
|
|
|
|
OMAP_HDQ_CTRL_STATUS_SINGLE);
|
|
|
|
|
|
|
|
out:
|
|
|
|
mutex_unlock(&hdq_data->hdq_mutex);
|
|
|
|
rtn:
|
|
|
|
omap_hdq_put(_hdq);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* reset callback */
|
|
|
|
static u8 omap_w1_reset_bus(void *_hdq)
|
|
|
|
{
|
|
|
|
omap_hdq_get(_hdq);
|
|
|
|
omap_hdq_break(_hdq);
|
|
|
|
omap_hdq_put(_hdq);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-11-12 14:27:09 -07:00
|
|
|
/* Read a byte of data from the device */
|
|
|
|
static u8 omap_w1_read_byte(void *_hdq)
|
|
|
|
{
|
|
|
|
struct hdq_data *hdq_data = _hdq;
|
|
|
|
u8 val = 0;
|
|
|
|
int ret;
|
|
|
|
|
2015-09-14 11:54:33 -06:00
|
|
|
/* First write to initialize the transfer */
|
|
|
|
if (hdq_data->init_trans == 0)
|
|
|
|
omap_hdq_get(hdq_data);
|
|
|
|
|
2008-11-12 14:27:09 -07:00
|
|
|
ret = hdq_read_byte(hdq_data, &val);
|
|
|
|
if (ret) {
|
|
|
|
ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
|
|
|
|
return -EINTR;
|
|
|
|
}
|
|
|
|
hdq_data->init_trans = 0;
|
|
|
|
mutex_unlock(&hdq_data->hdq_mutex);
|
|
|
|
omap_hdq_put(hdq_data);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2015-09-14 11:54:33 -06:00
|
|
|
hdq_disable_interrupt(hdq_data, OMAP_HDQ_CTRL_STATUS,
|
|
|
|
~OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
|
|
|
|
|
2008-11-12 14:27:09 -07:00
|
|
|
/* Write followed by a read, release the module */
|
|
|
|
if (hdq_data->init_trans) {
|
|
|
|
ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
|
|
|
|
return -EINTR;
|
|
|
|
}
|
|
|
|
hdq_data->init_trans = 0;
|
|
|
|
mutex_unlock(&hdq_data->hdq_mutex);
|
|
|
|
omap_hdq_put(hdq_data);
|
|
|
|
}
|
|
|
|
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Write a byte of data to the device */
|
|
|
|
static void omap_w1_write_byte(void *_hdq, u8 byte)
|
|
|
|
{
|
|
|
|
struct hdq_data *hdq_data = _hdq;
|
|
|
|
int ret;
|
|
|
|
u8 status;
|
|
|
|
|
|
|
|
/* First write to initialize the transfer */
|
|
|
|
if (hdq_data->init_trans == 0)
|
|
|
|
omap_hdq_get(hdq_data);
|
|
|
|
|
2015-09-14 11:54:33 -06:00
|
|
|
/*
|
|
|
|
* We need to reset the slave before
|
|
|
|
* issuing the SKIP ROM command, else
|
|
|
|
* the slave will not work.
|
|
|
|
*/
|
|
|
|
if (byte == W1_SKIP_ROM)
|
|
|
|
omap_hdq_break(hdq_data);
|
|
|
|
|
2008-11-12 14:27:09 -07:00
|
|
|
ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
hdq_data->init_trans++;
|
|
|
|
mutex_unlock(&hdq_data->hdq_mutex);
|
|
|
|
|
|
|
|
ret = hdq_write_byte(hdq_data, byte, &status);
|
2012-05-21 17:43:02 -06:00
|
|
|
if (ret < 0) {
|
2008-11-12 14:27:09 -07:00
|
|
|
dev_dbg(hdq_data->dev, "TX failure:Ctrl status %x\n", status);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2011-03-30 19:57:33 -06:00
|
|
|
/* Second write, data transferred. Release the module */
|
2008-11-12 14:27:09 -07:00
|
|
|
if (hdq_data->init_trans > 1) {
|
|
|
|
omap_hdq_put(hdq_data);
|
|
|
|
ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
hdq_data->init_trans = 0;
|
|
|
|
mutex_unlock(&hdq_data->hdq_mutex);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-11-19 11:21:43 -07:00
|
|
|
static int omap_hdq_probe(struct platform_device *pdev)
|
2008-11-12 14:27:09 -07:00
|
|
|
{
|
2012-07-25 06:05:30 -06:00
|
|
|
struct device *dev = &pdev->dev;
|
2008-11-12 14:27:09 -07:00
|
|
|
struct hdq_data *hdq_data;
|
|
|
|
struct resource *res;
|
|
|
|
int ret, irq;
|
|
|
|
u8 rev;
|
2015-09-14 11:54:33 -06:00
|
|
|
const char *mode;
|
2008-11-12 14:27:09 -07:00
|
|
|
|
2012-07-25 06:05:30 -06:00
|
|
|
hdq_data = devm_kzalloc(dev, sizeof(*hdq_data), GFP_KERNEL);
|
2008-11-12 14:27:09 -07:00
|
|
|
if (!hdq_data) {
|
|
|
|
dev_dbg(&pdev->dev, "unable to allocate memory\n");
|
2012-07-25 06:05:30 -06:00
|
|
|
return -ENOMEM;
|
2008-11-12 14:27:09 -07:00
|
|
|
}
|
|
|
|
|
2012-07-25 06:05:30 -06:00
|
|
|
hdq_data->dev = dev;
|
2008-11-12 14:27:09 -07:00
|
|
|
platform_set_drvdata(pdev, hdq_data);
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2013-01-21 03:09:24 -07:00
|
|
|
hdq_data->hdq_base = devm_ioremap_resource(dev, res);
|
|
|
|
if (IS_ERR(hdq_data->hdq_base))
|
|
|
|
return PTR_ERR(hdq_data->hdq_base);
|
2008-11-12 14:27:09 -07:00
|
|
|
|
|
|
|
hdq_data->hdq_usecount = 0;
|
2015-09-14 11:54:33 -06:00
|
|
|
hdq_data->rrw = 0;
|
2008-11-12 14:27:09 -07:00
|
|
|
mutex_init(&hdq_data->hdq_mutex);
|
|
|
|
|
2012-06-21 21:40:40 -06:00
|
|
|
pm_runtime_enable(&pdev->dev);
|
2015-09-14 11:54:33 -06:00
|
|
|
ret = pm_runtime_get_sync(&pdev->dev);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_dbg(&pdev->dev, "pm_runtime_get_sync failed\n");
|
|
|
|
goto err_w1;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = _omap_hdq_reset(hdq_data);
|
|
|
|
if (ret) {
|
|
|
|
dev_dbg(&pdev->dev, "reset failed\n");
|
2017-01-08 17:13:00 -07:00
|
|
|
goto err_irq;
|
2015-09-14 11:54:33 -06:00
|
|
|
}
|
2008-11-12 14:27:09 -07:00
|
|
|
|
|
|
|
rev = hdq_reg_in(hdq_data, OMAP_HDQ_REVISION);
|
|
|
|
dev_info(&pdev->dev, "OMAP HDQ Hardware Rev %c.%c. Driver in %s mode\n",
|
|
|
|
(rev >> 4) + '0', (rev & 0x0f) + '0', "Interrupt");
|
|
|
|
|
|
|
|
spin_lock_init(&hdq_data->hdq_spinlock);
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
if (irq < 0) {
|
|
|
|
ret = -ENXIO;
|
|
|
|
goto err_irq;
|
|
|
|
}
|
|
|
|
|
2013-10-13 01:20:05 -06:00
|
|
|
ret = devm_request_irq(dev, irq, hdq_isr, 0, "omap_hdq", hdq_data);
|
2008-11-12 14:27:09 -07:00
|
|
|
if (ret < 0) {
|
|
|
|
dev_dbg(&pdev->dev, "could not request irq\n");
|
|
|
|
goto err_irq;
|
|
|
|
}
|
|
|
|
|
|
|
|
omap_hdq_break(hdq_data);
|
|
|
|
|
2012-06-21 21:40:40 -06:00
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
2008-11-12 14:27:09 -07:00
|
|
|
|
2015-09-14 11:54:33 -06:00
|
|
|
ret = of_property_read_string(pdev->dev.of_node, "ti,mode", &mode);
|
|
|
|
if (ret < 0 || !strcmp(mode, "hdq")) {
|
|
|
|
hdq_data->mode = 0;
|
|
|
|
omap_w1_master.search = omap_w1_search_bus;
|
|
|
|
} else {
|
|
|
|
hdq_data->mode = 1;
|
|
|
|
omap_w1_master.triplet = omap_w1_triplet;
|
|
|
|
}
|
|
|
|
|
2008-11-12 14:27:09 -07:00
|
|
|
omap_w1_master.data = hdq_data;
|
|
|
|
|
|
|
|
ret = w1_add_master_device(&omap_w1_master);
|
|
|
|
if (ret) {
|
|
|
|
dev_dbg(&pdev->dev, "Failure in registering w1 master\n");
|
|
|
|
goto err_w1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_irq:
|
2012-06-21 21:40:40 -06:00
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
|
|
err_w1:
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
2011-02-10 16:01:37 -07:00
|
|
|
|
2008-11-12 14:27:09 -07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-11-19 11:26:23 -07:00
|
|
|
static int omap_hdq_remove(struct platform_device *pdev)
|
2008-11-12 14:27:09 -07:00
|
|
|
{
|
|
|
|
struct hdq_data *hdq_data = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
mutex_lock(&hdq_data->hdq_mutex);
|
|
|
|
|
|
|
|
if (hdq_data->hdq_usecount) {
|
|
|
|
dev_dbg(&pdev->dev, "removed when use count is not zero\n");
|
2009-08-06 16:07:28 -06:00
|
|
|
mutex_unlock(&hdq_data->hdq_mutex);
|
2008-11-12 14:27:09 -07:00
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
mutex_unlock(&hdq_data->hdq_mutex);
|
|
|
|
|
|
|
|
/* remove module dependency */
|
2012-06-21 21:40:40 -06:00
|
|
|
pm_runtime_disable(&pdev->dev);
|
2008-11-12 14:27:09 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-07-25 06:05:29 -06:00
|
|
|
module_platform_driver(omap_hdq_driver);
|
2008-11-12 14:27:09 -07:00
|
|
|
|
|
|
|
module_param(w1_id, int, S_IRUSR);
|
2015-09-14 11:54:33 -06:00
|
|
|
MODULE_PARM_DESC(w1_id, "1-wire id for the slave detection in HDQ mode");
|
2008-11-12 14:27:09 -07:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Texas Instruments");
|
2015-09-14 11:54:33 -06:00
|
|
|
MODULE_DESCRIPTION("HDQ-1W driver Library");
|
2008-11-12 14:27:09 -07:00
|
|
|
MODULE_LICENSE("GPL");
|