blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
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/*
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* File: include/asm-blackfin/mach-bf537/blackfin.h
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* Based on:
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* Author:
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*
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* Created:
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* Description:
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*
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* Rev:
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*
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* Modified:
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*
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING.
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* If not, write to the Free Software Foundation,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef _MACH_BLACKFIN_H_
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#define _MACH_BLACKFIN_H_
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#define BF537_FAMILY
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#include "bf537.h"
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#include "mem_map.h"
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#include "defBF534.h"
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#include "anomaly.h"
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#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
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#include "defBF537.h"
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#endif
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2007-07-24 21:50:42 -06:00
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#if !defined(__ASSEMBLY__)
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blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
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#include "cdefBF534.h"
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/* UART 0*/
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#define bfin_read_UART_THR() bfin_read_UART0_THR()
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#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
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#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
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#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
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#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
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#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
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#define bfin_read_UART_IER() bfin_read_UART0_IER()
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#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
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#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
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#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
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#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
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#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
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#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
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#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
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#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
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#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
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#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
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#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
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#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
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#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
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#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
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#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
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#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
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#include "cdefBF537.h"
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#endif
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#endif
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/* MAP used DEFINES from BF533 to BF537 - so we don't need to change them in the driver, kernel, etc. */
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/* UART_IIR Register */
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#define STATUS(x) ((x << 1) & 0x06)
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#define STATUS_P1 0x02
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#define STATUS_P0 0x01
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/* UART 0*/
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/* DMA Channnel */
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#define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX()
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#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val)
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#define CH_UART_RX CH_UART0_RX
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#define bfin_read_CH_UART_TX() bfin_read_CH_UART0_TX()
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#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART0_TX(val)
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#define CH_UART_TX CH_UART0_TX
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/* System Interrupt Controller */
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#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART0_RX()
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#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART0_RX(val)
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#define IRQ_UART_RX IRQ_UART0_RX
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#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART0_TX()
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#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART0_TX(val)
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#define IRQ_UART_TX IRQ_UART0_TX
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#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART0_ERROR()
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#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART0_ERROR(val)
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#define IRQ_UART_ERROR IRQ_UART0_ERROR
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/* MMR Registers*/
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#define bfin_read_UART_THR() bfin_read_UART0_THR()
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#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
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#define UART_THR UART0_THR
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#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
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#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
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#define UART_RBR UART0_RBR
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#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
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#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
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#define UART_DLL UART0_DLL
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#define bfin_read_UART_IER() bfin_read_UART0_IER()
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#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
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#define UART_IER UART0_IER
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#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
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#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
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#define UART_DLH UART0_DLH
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#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
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#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
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#define UART_IIR UART0_IIR
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#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
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#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
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#define UART_LCR UART0_LCR
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#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
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#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
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#define UART_MCR UART0_MCR
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#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
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#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
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#define UART_LSR UART0_LSR
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#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
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#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
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#define UART_SCR UART0_SCR
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#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
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#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
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#define UART_GCTL UART0_GCTL
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/* DPMC*/
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#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
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#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
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#define STOPCK_OFF STOPCK
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/* PLL_DIV Masks */
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#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
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#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
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#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
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#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
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#endif
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