2019-06-04 02:11:33 -06:00
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// SPDX-License-Identifier: GPL-2.0-only
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2008-02-18 03:40:22 -07:00
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/*
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* ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
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*
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2008-09-29 13:14:11 -06:00
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* Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
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2008-02-18 03:40:22 -07:00
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* Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
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*
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2016-04-18 06:32:41 -06:00
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* DT support (c) 2016 Petr Kulhavy, Barix AG <petr@barix.com>
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* based on davinci-mcasp.c DT support
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*
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* TODO:
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* on DA850 implement HW FIFOs instead of DMA into DXR and DRR registers
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2008-02-18 03:40:22 -07:00
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2008-02-18 03:40:22 -07:00
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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2012-08-27 07:26:41 -06:00
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#include <linux/platform_data/davinci_asp.h>
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2008-02-18 03:40:22 -07:00
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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2015-03-03 07:45:18 -07:00
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#include <sound/dmaengine_pcm.h>
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2008-02-18 03:40:22 -07:00
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2015-03-03 07:45:18 -07:00
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#include "edma-pcm.h"
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2010-07-06 02:39:02 -06:00
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#include "davinci-i2s.h"
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2008-02-18 03:40:22 -07:00
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2018-01-28 19:46:04 -07:00
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#define DRV_NAME "davinci-i2s"
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2009-05-14 13:47:42 -06:00
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/*
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* NOTE: terminology here is confusing.
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*
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* - This driver supports the "Audio Serial Port" (ASP),
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* found on dm6446, dm355, and other DaVinci chips.
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*
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* - But it labels it a "Multi-channel Buffered Serial Port"
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* (McBSP) as on older chips like the dm642 ... which was
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* backward-compatible, possibly explaining that confusion.
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*
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* - OMAP chips have a controller called McBSP, which is
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* incompatible with the DaVinci flavor of McBSP.
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*
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* - Newer DaVinci chips have a controller called McASP,
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* incompatible with ASP and with either McBSP.
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*
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* In short: this uses ASP to implement I2S, not McBSP.
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* And it won't be the only DaVinci implemention of I2S.
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*/
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2008-02-18 03:40:22 -07:00
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#define DAVINCI_MCBSP_DRR_REG 0x00
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#define DAVINCI_MCBSP_DXR_REG 0x04
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#define DAVINCI_MCBSP_SPCR_REG 0x08
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#define DAVINCI_MCBSP_RCR_REG 0x0c
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#define DAVINCI_MCBSP_XCR_REG 0x10
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#define DAVINCI_MCBSP_SRGR_REG 0x14
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#define DAVINCI_MCBSP_PCR_REG 0x24
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#define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
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#define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
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#define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
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#define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
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#define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
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#define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
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#define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
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#define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
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#define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
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#define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
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2009-07-04 20:29:57 -06:00
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#define DAVINCI_MCBSP_RCR_RFIG (1 << 18)
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2008-02-18 03:40:22 -07:00
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#define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
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2010-07-06 02:39:02 -06:00
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#define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24)
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#define DAVINCI_MCBSP_RCR_RPHASE BIT(31)
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2008-02-18 03:40:22 -07:00
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#define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
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#define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
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#define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
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#define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
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#define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
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2010-07-06 02:39:02 -06:00
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#define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24)
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#define DAVINCI_MCBSP_XCR_XPHASE BIT(31)
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2008-02-18 03:40:22 -07:00
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#define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
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#define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
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#define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
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2010-07-06 02:39:02 -06:00
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#define DAVINCI_MCBSP_SRGR_CLKSM BIT(29)
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2008-02-18 03:40:22 -07:00
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#define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
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#define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
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#define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
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#define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
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2008-11-08 11:26:09 -07:00
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#define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
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2008-02-18 03:40:22 -07:00
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#define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
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#define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
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#define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
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#define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
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enum {
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DAVINCI_MCBSP_WORD_8 = 0,
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DAVINCI_MCBSP_WORD_12,
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DAVINCI_MCBSP_WORD_16,
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DAVINCI_MCBSP_WORD_20,
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DAVINCI_MCBSP_WORD_24,
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DAVINCI_MCBSP_WORD_32,
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};
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2009-11-18 17:49:51 -07:00
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static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = {
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[SNDRV_PCM_FORMAT_S8] = 1,
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[SNDRV_PCM_FORMAT_S16_LE] = 2,
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[SNDRV_PCM_FORMAT_S32_LE] = 4,
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};
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static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = {
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[SNDRV_PCM_FORMAT_S8] = DAVINCI_MCBSP_WORD_8,
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[SNDRV_PCM_FORMAT_S16_LE] = DAVINCI_MCBSP_WORD_16,
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[SNDRV_PCM_FORMAT_S32_LE] = DAVINCI_MCBSP_WORD_32,
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};
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static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = {
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[SNDRV_PCM_FORMAT_S8] = SNDRV_PCM_FORMAT_S16_LE,
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[SNDRV_PCM_FORMAT_S16_LE] = SNDRV_PCM_FORMAT_S32_LE,
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};
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2008-02-18 03:40:22 -07:00
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struct davinci_mcbsp_dev {
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2010-07-06 02:39:03 -06:00
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struct device *dev;
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2015-03-03 07:45:18 -07:00
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struct snd_dmaengine_dai_dma_data dma_data[2];
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int dma_request[2];
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2008-02-18 03:40:22 -07:00
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void __iomem *base;
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2009-07-04 20:29:57 -06:00
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#define MOD_DSP_A 0
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#define MOD_DSP_B 1
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int mode;
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2009-07-04 20:29:52 -06:00
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u32 pcr;
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2008-02-18 03:40:22 -07:00
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struct clk *clk;
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2009-11-18 17:49:51 -07:00
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/*
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* Combining both channels into 1 element will at least double the
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* amount of time between servicing the dma channel, increase
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* effiency, and reduce the chance of overrun/underrun. But,
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* it will result in the left & right channels being swapped.
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*
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* If relabeling the left and right channels is not possible,
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* you may want to let the codec know to swap them back.
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*
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* It may allow x10 the amount of time to service dma requests,
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* if the codec is master and is using an unnecessarily fast bit clock
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* (ie. tlvaic23b), independent of the sample rate. So, having an
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* entire frame at once means it can be serviced at the sample rate
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* instead of the bit clock rate.
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*
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* In the now unlikely case that an underrun still
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* occurs, both the left and right samples will be repeated
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* so that no pops are heard, and the left and right channels
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* won't end up being swapped because of the underrun.
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*/
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unsigned enable_channel_combine:1;
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2010-07-06 02:39:02 -06:00
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unsigned int fmt;
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int clk_div;
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2010-07-06 02:39:03 -06:00
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int clk_input_pin;
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2010-07-06 02:39:04 -06:00
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bool i2s_accurate_sck;
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2008-02-18 03:40:22 -07:00
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};
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static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
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int reg, u32 val)
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{
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__raw_writel(val, dev->base + reg);
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}
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static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
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{
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return __raw_readl(dev->base + reg);
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}
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2009-07-04 20:29:52 -06:00
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static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
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{
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u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
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/* The clock needs to toggle to complete reset.
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* So, fake it by toggling the clk polarity.
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*/
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
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}
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2009-07-04 20:29:53 -06:00
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static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
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struct snd_pcm_substream *substream)
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2008-02-18 03:40:22 -07:00
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{
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2009-07-04 20:29:52 -06:00
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int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
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2009-07-04 20:29:51 -06:00
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u32 spcr;
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2009-07-04 20:29:52 -06:00
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u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
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2008-11-11 21:56:31 -07:00
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2009-07-04 20:29:55 -06:00
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/* Enable transmitter or receiver */
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2009-07-04 20:29:51 -06:00
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spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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2009-07-04 20:29:55 -06:00
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spcr |= mask;
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if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
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/* Start frame sync */
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spcr |= DAVINCI_MCBSP_SPCR_FRST;
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}
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2009-07-04 20:29:51 -06:00
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
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2008-02-18 03:40:22 -07:00
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}
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2009-07-04 20:29:53 -06:00
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static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
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2008-02-18 03:40:22 -07:00
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{
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2009-07-04 20:29:51 -06:00
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u32 spcr;
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2008-02-18 03:40:22 -07:00
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/* Reset transmitter/receiver and sample rate/frame sync generators */
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2009-07-04 20:29:51 -06:00
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spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
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spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
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2009-07-04 20:29:52 -06:00
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spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
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2009-07-04 20:29:51 -06:00
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davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
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2009-07-04 20:29:52 -06:00
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toggle_clock(dev, playback);
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2008-02-18 03:40:22 -07:00
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}
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2008-12-18 12:36:43 -07:00
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#define DEFAULT_BITPERSAMPLE 16
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2008-07-07 09:07:42 -06:00
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static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
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2008-02-18 03:40:22 -07:00
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unsigned int fmt)
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{
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2010-03-17 14:15:21 -06:00
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struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
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2008-12-18 12:36:43 -07:00
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unsigned int pcr;
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unsigned int srgr;
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2011-09-30 01:55:33 -06:00
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bool inv_fs = false;
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2010-07-06 02:39:02 -06:00
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/* Attention srgr is updated by hw_params! */
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2008-12-18 12:36:43 -07:00
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srgr = DAVINCI_MCBSP_SRGR_FSGM |
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DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
|
|
|
|
DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
|
2008-02-18 03:40:22 -07:00
|
|
|
|
2010-07-06 02:39:02 -06:00
|
|
|
dev->fmt = fmt;
|
2009-07-04 20:29:57 -06:00
|
|
|
/* set master/slave audio interface */
|
2008-02-18 03:40:22 -07:00
|
|
|
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_CBS_CFS:
|
2008-12-18 12:36:43 -07:00
|
|
|
/* cpu is master */
|
|
|
|
pcr = DAVINCI_MCBSP_PCR_FSXM |
|
|
|
|
DAVINCI_MCBSP_PCR_FSRM |
|
|
|
|
DAVINCI_MCBSP_PCR_CLKXM |
|
|
|
|
DAVINCI_MCBSP_PCR_CLKRM;
|
2008-02-18 03:40:22 -07:00
|
|
|
break;
|
2008-11-08 11:26:09 -07:00
|
|
|
case SND_SOC_DAIFMT_CBM_CFS:
|
2010-07-06 02:39:03 -06:00
|
|
|
pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
|
|
|
|
/*
|
|
|
|
* Selection of the clock input pin that is the
|
|
|
|
* input for the Sample Rate Generator.
|
|
|
|
* McBSP FSR and FSX are driven by the Sample Rate
|
|
|
|
* Generator.
|
|
|
|
*/
|
|
|
|
switch (dev->clk_input_pin) {
|
|
|
|
case MCBSP_CLKS:
|
|
|
|
pcr |= DAVINCI_MCBSP_PCR_CLKXM |
|
|
|
|
DAVINCI_MCBSP_PCR_CLKRM;
|
|
|
|
break;
|
|
|
|
case MCBSP_CLKR:
|
|
|
|
pcr |= DAVINCI_MCBSP_PCR_SCLKME;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_err(dev->dev, "bad clk_input_pin\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2008-11-08 11:26:09 -07:00
|
|
|
break;
|
2008-02-18 03:40:22 -07:00
|
|
|
case SND_SOC_DAIFMT_CBM_CFM:
|
2008-12-18 12:36:43 -07:00
|
|
|
/* codec is master */
|
|
|
|
pcr = 0;
|
2008-02-18 03:40:22 -07:00
|
|
|
break;
|
|
|
|
default:
|
2008-12-18 12:36:43 -07:00
|
|
|
printk(KERN_ERR "%s:bad master\n", __func__);
|
2008-02-18 03:40:22 -07:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2009-07-04 20:29:57 -06:00
|
|
|
/* interface format */
|
2008-12-18 12:36:44 -07:00
|
|
|
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_I2S:
|
2008-12-19 13:05:24 -07:00
|
|
|
/* Davinci doesn't support TRUE I2S, but some codecs will have
|
|
|
|
* the left and right channels contiguous. This allows
|
|
|
|
* dsp_a mode to be used with an inverted normal frame clk.
|
|
|
|
* If your codec is master and does not have contiguous
|
|
|
|
* channels, then you will have sound on only one channel.
|
|
|
|
* Try using a different mode, or codec as slave.
|
|
|
|
*
|
|
|
|
* The TLV320AIC33 is an example of a codec where this works.
|
|
|
|
* It has a variable bit clock frequency allowing it to have
|
|
|
|
* valid data on every bit clock.
|
|
|
|
*
|
|
|
|
* The TLV320AIC23 is an example of a codec where this does not
|
|
|
|
* work. It has a fixed bit clock frequency with progressively
|
|
|
|
* more empty bit clock slots between channels as the sample
|
|
|
|
* rate is lowered.
|
|
|
|
*/
|
2011-09-30 01:55:33 -06:00
|
|
|
inv_fs = true;
|
2018-08-03 10:28:24 -06:00
|
|
|
/* fall through */
|
2008-12-19 13:05:24 -07:00
|
|
|
case SND_SOC_DAIFMT_DSP_A:
|
2009-07-04 20:29:57 -06:00
|
|
|
dev->mode = MOD_DSP_A;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_DSP_B:
|
|
|
|
dev->mode = MOD_DSP_B;
|
2008-12-18 12:36:44 -07:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printk(KERN_ERR "%s:bad format\n", __func__);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2008-02-18 03:40:22 -07:00
|
|
|
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
|
2008-12-19 13:05:23 -07:00
|
|
|
case SND_SOC_DAIFMT_NB_NF:
|
2008-12-18 12:36:41 -07:00
|
|
|
/* CLKRP Receive clock polarity,
|
|
|
|
* 1 - sampled on rising edge of CLKR
|
|
|
|
* valid on rising edge
|
|
|
|
* CLKXP Transmit clock polarity,
|
|
|
|
* 1 - clocked on falling edge of CLKX
|
|
|
|
* valid on rising edge
|
|
|
|
* FSRP Receive frame sync pol, 0 - active high
|
|
|
|
* FSXP Transmit frame sync pol, 0 - active high
|
|
|
|
*/
|
2008-12-18 12:36:43 -07:00
|
|
|
pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
|
2008-02-18 03:40:22 -07:00
|
|
|
break;
|
2008-12-19 13:05:23 -07:00
|
|
|
case SND_SOC_DAIFMT_IB_IF:
|
2008-12-18 12:36:41 -07:00
|
|
|
/* CLKRP Receive clock polarity,
|
|
|
|
* 0 - sampled on falling edge of CLKR
|
|
|
|
* valid on falling edge
|
|
|
|
* CLKXP Transmit clock polarity,
|
|
|
|
* 0 - clocked on rising edge of CLKX
|
|
|
|
* valid on falling edge
|
|
|
|
* FSRP Receive frame sync pol, 1 - active low
|
|
|
|
* FSXP Transmit frame sync pol, 1 - active low
|
|
|
|
*/
|
2008-12-18 12:36:43 -07:00
|
|
|
pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
|
2008-02-18 03:40:22 -07:00
|
|
|
break;
|
2008-12-19 13:05:23 -07:00
|
|
|
case SND_SOC_DAIFMT_NB_IF:
|
2008-12-18 12:36:41 -07:00
|
|
|
/* CLKRP Receive clock polarity,
|
|
|
|
* 1 - sampled on rising edge of CLKR
|
|
|
|
* valid on rising edge
|
|
|
|
* CLKXP Transmit clock polarity,
|
|
|
|
* 1 - clocked on falling edge of CLKX
|
|
|
|
* valid on rising edge
|
|
|
|
* FSRP Receive frame sync pol, 1 - active low
|
|
|
|
* FSXP Transmit frame sync pol, 1 - active low
|
|
|
|
*/
|
2008-12-18 12:36:43 -07:00
|
|
|
pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
|
|
|
|
DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
|
2008-02-18 03:40:22 -07:00
|
|
|
break;
|
2008-12-19 13:05:23 -07:00
|
|
|
case SND_SOC_DAIFMT_IB_NF:
|
2008-12-18 12:36:41 -07:00
|
|
|
/* CLKRP Receive clock polarity,
|
|
|
|
* 0 - sampled on falling edge of CLKR
|
|
|
|
* valid on falling edge
|
|
|
|
* CLKXP Transmit clock polarity,
|
|
|
|
* 0 - clocked on rising edge of CLKX
|
|
|
|
* valid on falling edge
|
|
|
|
* FSRP Receive frame sync pol, 0 - active high
|
|
|
|
* FSXP Transmit frame sync pol, 0 - active high
|
|
|
|
*/
|
2008-02-18 03:40:22 -07:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2011-09-30 01:55:33 -06:00
|
|
|
if (inv_fs == true)
|
|
|
|
pcr ^= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
|
2008-12-18 12:36:43 -07:00
|
|
|
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
|
2009-07-04 20:29:52 -06:00
|
|
|
dev->pcr = pcr;
|
2008-12-18 12:36:43 -07:00
|
|
|
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
|
2008-02-18 03:40:22 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-07-06 02:39:02 -06:00
|
|
|
static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
|
|
|
|
int div_id, int div)
|
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
|
2010-07-06 02:39:02 -06:00
|
|
|
|
|
|
|
if (div_id != DAVINCI_MCBSP_CLKGDV)
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
dev->clk_div = div;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-02-18 03:40:22 -07:00
|
|
|
static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
|
2008-11-18 15:11:38 -07:00
|
|
|
struct snd_pcm_hw_params *params,
|
|
|
|
struct snd_soc_dai *dai)
|
2008-02-18 03:40:22 -07:00
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
|
2008-02-18 03:40:22 -07:00
|
|
|
struct snd_interval *i = NULL;
|
2010-07-06 02:39:02 -06:00
|
|
|
int mcbsp_word_length, master;
|
|
|
|
unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
|
2009-07-04 20:29:51 -06:00
|
|
|
u32 spcr;
|
2009-11-18 17:49:51 -07:00
|
|
|
snd_pcm_format_t fmt;
|
|
|
|
unsigned element_cnt = 1;
|
2008-02-18 03:40:22 -07:00
|
|
|
|
|
|
|
/* general line settings */
|
2009-07-04 20:29:51 -06:00
|
|
|
spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
|
2008-11-17 22:31:03 -07:00
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
|
2009-07-04 20:29:51 -06:00
|
|
|
spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
|
|
|
|
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
|
2008-11-17 22:31:03 -07:00
|
|
|
} else {
|
2009-07-04 20:29:51 -06:00
|
|
|
spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
|
|
|
|
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
|
2008-11-17 22:31:03 -07:00
|
|
|
}
|
2008-02-18 03:40:22 -07:00
|
|
|
|
2010-07-06 02:39:02 -06:00
|
|
|
master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
|
|
|
|
fmt = params_format(params);
|
|
|
|
mcbsp_word_length = asp_word_length[fmt];
|
2008-02-18 03:40:22 -07:00
|
|
|
|
2010-07-06 02:39:02 -06:00
|
|
|
switch (master) {
|
|
|
|
case SND_SOC_DAIFMT_CBS_CFS:
|
|
|
|
freq = clk_get_rate(dev->clk);
|
|
|
|
srgr = DAVINCI_MCBSP_SRGR_FSGM |
|
|
|
|
DAVINCI_MCBSP_SRGR_CLKSM;
|
|
|
|
srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
|
|
|
|
8 - 1);
|
2010-07-06 02:39:04 -06:00
|
|
|
if (dev->i2s_accurate_sck) {
|
|
|
|
clk_div = 256;
|
|
|
|
do {
|
|
|
|
framesize = (freq / (--clk_div)) /
|
|
|
|
params->rate_num *
|
|
|
|
params->rate_den;
|
|
|
|
} while (((framesize < 33) || (framesize > 4095)) &&
|
|
|
|
(clk_div));
|
|
|
|
clk_div--;
|
|
|
|
srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
|
|
|
|
} else {
|
|
|
|
/* symmetric waveforms */
|
|
|
|
clk_div = freq / (mcbsp_word_length * 16) /
|
|
|
|
params->rate_num * params->rate_den;
|
|
|
|
srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
|
|
|
|
16 - 1);
|
|
|
|
}
|
2010-07-06 02:39:02 -06:00
|
|
|
clk_div &= 0xFF;
|
|
|
|
srgr |= clk_div;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_CBM_CFS:
|
|
|
|
srgr = DAVINCI_MCBSP_SRGR_FSGM;
|
|
|
|
clk_div = dev->clk_div - 1;
|
|
|
|
srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
|
|
|
|
srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1);
|
|
|
|
clk_div &= 0xFF;
|
|
|
|
srgr |= clk_div;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_CBM_CFM:
|
|
|
|
/* Clock and frame sync given from external sources */
|
|
|
|
i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
|
|
|
|
srgr = DAVINCI_MCBSP_SRGR_FSGM;
|
|
|
|
srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
|
|
|
|
pr_debug("%s - %d FWID set: re-read srgr = %X\n",
|
|
|
|
__func__, __LINE__, snd_interval_value(i) - 1);
|
|
|
|
|
|
|
|
i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
|
|
|
|
srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2009-07-04 20:29:51 -06:00
|
|
|
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
|
2008-02-18 03:40:22 -07:00
|
|
|
|
2009-07-04 20:29:57 -06:00
|
|
|
rcr = DAVINCI_MCBSP_RCR_RFIG;
|
|
|
|
xcr = DAVINCI_MCBSP_XCR_XFIG;
|
|
|
|
if (dev->mode == MOD_DSP_B) {
|
|
|
|
rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
|
|
|
|
xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
|
|
|
|
} else {
|
|
|
|
rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
|
|
|
|
xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
|
|
|
|
}
|
2008-02-18 03:40:22 -07:00
|
|
|
/* Determine xfer data type */
|
2009-11-18 17:49:51 -07:00
|
|
|
fmt = params_format(params);
|
|
|
|
if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) {
|
2008-08-26 07:47:55 -06:00
|
|
|
printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
|
2008-02-18 03:40:22 -07:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2009-11-18 17:49:51 -07:00
|
|
|
if (params_channels(params) == 2) {
|
|
|
|
element_cnt = 2;
|
|
|
|
if (double_fmt[fmt] && dev->enable_channel_combine) {
|
|
|
|
element_cnt = 1;
|
|
|
|
fmt = double_fmt[fmt];
|
|
|
|
}
|
2010-07-06 02:39:02 -06:00
|
|
|
switch (master) {
|
|
|
|
case SND_SOC_DAIFMT_CBS_CFS:
|
|
|
|
case SND_SOC_DAIFMT_CBS_CFM:
|
|
|
|
rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
|
|
|
|
xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
|
|
|
|
rcr |= DAVINCI_MCBSP_RCR_RPHASE;
|
|
|
|
xcr |= DAVINCI_MCBSP_XCR_XPHASE;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_CBM_CFM:
|
|
|
|
case SND_SOC_DAIFMT_CBM_CFS:
|
|
|
|
rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
|
|
|
|
xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2009-11-18 17:49:51 -07:00
|
|
|
}
|
|
|
|
mcbsp_word_length = asp_word_length[fmt];
|
2010-07-06 02:39:02 -06:00
|
|
|
|
|
|
|
switch (master) {
|
|
|
|
case SND_SOC_DAIFMT_CBS_CFS:
|
|
|
|
case SND_SOC_DAIFMT_CBS_CFM:
|
|
|
|
rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
|
|
|
|
xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_CBM_CFM:
|
|
|
|
case SND_SOC_DAIFMT_CBM_CFS:
|
|
|
|
rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
|
|
|
|
xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2008-02-18 03:40:22 -07:00
|
|
|
|
2009-07-04 20:29:57 -06:00
|
|
|
rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
|
|
|
|
DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
|
|
|
|
xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
|
|
|
|
DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
|
2008-02-18 03:40:22 -07:00
|
|
|
|
2009-07-04 20:29:57 -06:00
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
|
|
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
|
|
|
|
else
|
|
|
|
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
|
2010-07-06 02:39:02 -06:00
|
|
|
|
|
|
|
pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr);
|
|
|
|
pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr);
|
|
|
|
pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr);
|
2008-02-18 03:40:22 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-07-04 20:29:59 -06:00
|
|
|
static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
|
2009-07-04 20:29:59 -06:00
|
|
|
int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
|
2019-08-30 04:38:39 -06:00
|
|
|
u32 spcr;
|
|
|
|
u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
|
|
|
|
|
2009-07-04 20:29:59 -06:00
|
|
|
davinci_mcbsp_stop(dev, playback);
|
2019-08-30 04:38:39 -06:00
|
|
|
|
|
|
|
spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
|
|
|
|
if (spcr & mask) {
|
|
|
|
/* start off disabled */
|
|
|
|
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
|
|
|
|
spcr & ~mask);
|
|
|
|
toggle_clock(dev, playback);
|
|
|
|
}
|
|
|
|
if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
|
|
|
|
DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
|
|
|
|
/* Start the sample generator */
|
|
|
|
spcr |= DAVINCI_MCBSP_SPCR_GRST;
|
|
|
|
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (playback) {
|
|
|
|
/* Enable the transmitter */
|
|
|
|
spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
|
|
|
|
spcr |= DAVINCI_MCBSP_SPCR_XRST;
|
|
|
|
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
|
|
|
|
|
|
|
|
/* wait for any unexpected frame sync error to occur */
|
|
|
|
udelay(100);
|
|
|
|
|
|
|
|
/* Disable the transmitter to clear any outstanding XSYNCERR */
|
|
|
|
spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
|
|
|
|
spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
|
|
|
|
davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
|
|
|
|
toggle_clock(dev, playback);
|
|
|
|
}
|
|
|
|
|
2009-07-04 20:29:59 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-11-18 15:11:38 -07:00
|
|
|
static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
|
|
|
|
struct snd_soc_dai *dai)
|
2008-02-18 03:40:22 -07:00
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
|
2008-02-18 03:40:22 -07:00
|
|
|
int ret = 0;
|
2009-07-04 20:29:53 -06:00
|
|
|
int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
|
2008-02-18 03:40:22 -07:00
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
2009-07-04 20:29:53 -06:00
|
|
|
davinci_mcbsp_start(dev, substream);
|
2008-02-18 03:40:22 -07:00
|
|
|
break;
|
|
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
2009-07-04 20:29:53 -06:00
|
|
|
davinci_mcbsp_stop(dev, playback);
|
2008-02-18 03:40:22 -07:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ret = -EINVAL;
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2009-07-04 20:29:59 -06:00
|
|
|
static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
|
2009-07-04 20:29:59 -06:00
|
|
|
int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
|
|
|
|
davinci_mcbsp_stop(dev, playback);
|
|
|
|
}
|
|
|
|
|
2009-06-05 04:28:23 -06:00
|
|
|
#define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
|
2019-08-30 04:38:38 -06:00
|
|
|
#define DAVINCI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
|
|
|
|
SNDRV_PCM_FMTBIT_S32_LE)
|
2009-06-05 04:28:23 -06:00
|
|
|
|
2011-11-23 03:40:40 -07:00
|
|
|
static const struct snd_soc_dai_ops davinci_i2s_dai_ops = {
|
2009-07-07 12:18:46 -06:00
|
|
|
.shutdown = davinci_i2s_shutdown,
|
|
|
|
.prepare = davinci_i2s_prepare,
|
2009-06-05 04:28:23 -06:00
|
|
|
.trigger = davinci_i2s_trigger,
|
|
|
|
.hw_params = davinci_i2s_hw_params,
|
|
|
|
.set_fmt = davinci_i2s_set_dai_fmt,
|
2010-07-06 02:39:02 -06:00
|
|
|
.set_clkdiv = davinci_i2s_dai_set_clkdiv,
|
2009-06-05 04:28:23 -06:00
|
|
|
|
|
|
|
};
|
|
|
|
|
2015-03-03 07:45:18 -07:00
|
|
|
static int davinci_i2s_dai_probe(struct snd_soc_dai *dai)
|
|
|
|
{
|
|
|
|
struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
|
|
|
|
|
|
|
|
dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
|
|
|
|
dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
static struct snd_soc_dai_driver davinci_i2s_dai = {
|
2015-03-03 07:45:18 -07:00
|
|
|
.probe = davinci_i2s_dai_probe,
|
2009-06-05 04:28:23 -06:00
|
|
|
.playback = {
|
|
|
|
.channels_min = 2,
|
|
|
|
.channels_max = 2,
|
|
|
|
.rates = DAVINCI_I2S_RATES,
|
2019-08-30 04:38:38 -06:00
|
|
|
.formats = DAVINCI_I2S_FORMATS,
|
|
|
|
},
|
2009-06-05 04:28:23 -06:00
|
|
|
.capture = {
|
|
|
|
.channels_min = 2,
|
|
|
|
.channels_max = 2,
|
|
|
|
.rates = DAVINCI_I2S_RATES,
|
2019-08-30 04:38:38 -06:00
|
|
|
.formats = DAVINCI_I2S_FORMATS,
|
|
|
|
},
|
2009-06-05 04:28:23 -06:00
|
|
|
.ops = &davinci_i2s_dai_ops,
|
|
|
|
|
|
|
|
};
|
|
|
|
|
2013-03-21 04:30:54 -06:00
|
|
|
static const struct snd_soc_component_driver davinci_i2s_component = {
|
2018-01-28 19:46:04 -07:00
|
|
|
.name = DRV_NAME,
|
2013-03-21 04:30:54 -06:00
|
|
|
};
|
|
|
|
|
2009-06-05 04:28:23 -06:00
|
|
|
static int davinci_i2s_probe(struct platform_device *pdev)
|
2008-02-18 03:40:22 -07:00
|
|
|
{
|
2016-04-18 06:32:41 -06:00
|
|
|
struct snd_dmaengine_dai_dma_data *dma_data;
|
2008-02-18 03:40:22 -07:00
|
|
|
struct davinci_mcbsp_dev *dev;
|
2015-08-24 02:47:36 -06:00
|
|
|
struct resource *mem, *res;
|
|
|
|
void __iomem *io_base;
|
2015-03-03 07:45:18 -07:00
|
|
|
int *dma;
|
2008-02-18 03:40:22 -07:00
|
|
|
int ret;
|
|
|
|
|
2016-04-18 06:32:41 -06:00
|
|
|
mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
|
|
|
|
if (!mem) {
|
|
|
|
dev_warn(&pdev->dev,
|
|
|
|
"\"mpu\" mem resource not found, using index 0\n");
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!mem) {
|
|
|
|
dev_err(&pdev->dev, "no mem resource?\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-08-24 02:47:36 -06:00
|
|
|
io_base = devm_ioremap_resource(&pdev->dev, mem);
|
|
|
|
if (IS_ERR(io_base))
|
|
|
|
return PTR_ERR(io_base);
|
2008-02-18 03:40:22 -07:00
|
|
|
|
2011-12-29 09:51:22 -07:00
|
|
|
dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcbsp_dev),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!dev)
|
|
|
|
return -ENOMEM;
|
2010-07-19 01:01:16 -06:00
|
|
|
|
2015-08-24 02:47:36 -06:00
|
|
|
dev->base = io_base;
|
2008-02-18 03:40:22 -07:00
|
|
|
|
2016-04-18 06:32:41 -06:00
|
|
|
/* setup DMA, first TX, then RX */
|
|
|
|
dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
|
|
|
|
dma_data->addr = (dma_addr_t)(mem->start + DAVINCI_MCBSP_DXR_REG);
|
2008-02-18 03:40:22 -07:00
|
|
|
|
2009-06-05 04:28:23 -06:00
|
|
|
res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
|
2016-04-18 06:32:41 -06:00
|
|
|
if (res) {
|
|
|
|
dma = &dev->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
|
|
|
|
*dma = res->start;
|
|
|
|
dma_data->filter_data = dma;
|
|
|
|
} else if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
|
|
|
|
dma_data->filter_data = "tx";
|
|
|
|
} else {
|
|
|
|
dev_err(&pdev->dev, "Missing DMA tx resource\n");
|
|
|
|
return -ENODEV;
|
2009-06-05 04:28:23 -06:00
|
|
|
}
|
2016-04-18 06:32:41 -06:00
|
|
|
|
|
|
|
dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE];
|
|
|
|
dma_data->addr = (dma_addr_t)(mem->start + DAVINCI_MCBSP_DRR_REG);
|
2009-06-05 04:28:23 -06:00
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
|
2016-04-18 06:32:41 -06:00
|
|
|
if (res) {
|
|
|
|
dma = &dev->dma_request[SNDRV_PCM_STREAM_CAPTURE];
|
|
|
|
*dma = res->start;
|
|
|
|
dma_data->filter_data = dma;
|
|
|
|
} else if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
|
|
|
|
dma_data->filter_data = "rx";
|
|
|
|
} else {
|
|
|
|
dev_err(&pdev->dev, "Missing DMA rx resource\n");
|
|
|
|
return -ENODEV;
|
2009-06-05 04:28:23 -06:00
|
|
|
}
|
2016-04-18 06:32:41 -06:00
|
|
|
|
|
|
|
dev->clk = clk_get(&pdev->dev, NULL);
|
|
|
|
if (IS_ERR(dev->clk))
|
|
|
|
return -ENODEV;
|
|
|
|
clk_enable(dev->clk);
|
2009-06-05 04:28:23 -06:00
|
|
|
|
2015-03-03 07:45:18 -07:00
|
|
|
dev->dev = &pdev->dev;
|
2010-03-17 14:15:21 -06:00
|
|
|
dev_set_drvdata(&pdev->dev, dev);
|
|
|
|
|
2013-03-21 04:30:54 -06:00
|
|
|
ret = snd_soc_register_component(&pdev->dev, &davinci_i2s_component,
|
|
|
|
&davinci_i2s_dai, 1);
|
2009-06-05 04:28:23 -06:00
|
|
|
if (ret != 0)
|
2011-12-29 09:51:22 -07:00
|
|
|
goto err_release_clk;
|
2009-06-05 04:28:23 -06:00
|
|
|
|
2015-03-03 07:45:18 -07:00
|
|
|
ret = edma_pcm_platform_register(&pdev->dev);
|
2012-08-27 07:26:39 -06:00
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
|
2013-03-21 04:30:54 -06:00
|
|
|
goto err_unregister_component;
|
2012-08-27 07:26:39 -06:00
|
|
|
}
|
|
|
|
|
2008-02-18 03:40:22 -07:00
|
|
|
return 0;
|
|
|
|
|
2013-03-21 04:30:54 -06:00
|
|
|
err_unregister_component:
|
|
|
|
snd_soc_unregister_component(&pdev->dev);
|
2011-02-09 06:09:53 -07:00
|
|
|
err_release_clk:
|
|
|
|
clk_disable(dev->clk);
|
|
|
|
clk_put(dev->clk);
|
2008-02-18 03:40:22 -07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2009-06-05 04:28:23 -06:00
|
|
|
static int davinci_i2s_remove(struct platform_device *pdev)
|
2008-02-18 03:40:22 -07:00
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
struct davinci_mcbsp_dev *dev = dev_get_drvdata(&pdev->dev);
|
2008-02-18 03:40:22 -07:00
|
|
|
|
2013-03-21 04:30:54 -06:00
|
|
|
snd_soc_unregister_component(&pdev->dev);
|
2012-08-27 07:26:39 -06:00
|
|
|
|
2008-02-18 03:40:22 -07:00
|
|
|
clk_disable(dev->clk);
|
|
|
|
clk_put(dev->clk);
|
|
|
|
dev->clk = NULL;
|
|
|
|
|
2009-06-05 04:28:23 -06:00
|
|
|
return 0;
|
|
|
|
}
|
2009-03-02 18:41:00 -07:00
|
|
|
|
2016-04-18 06:32:41 -06:00
|
|
|
static const struct of_device_id davinci_i2s_match[] = {
|
|
|
|
{ .compatible = "ti,da850-mcbsp" },
|
|
|
|
{},
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, davinci_i2s_match);
|
|
|
|
|
2009-06-05 04:28:23 -06:00
|
|
|
static struct platform_driver davinci_mcbsp_driver = {
|
|
|
|
.probe = davinci_i2s_probe,
|
|
|
|
.remove = davinci_i2s_remove,
|
|
|
|
.driver = {
|
ASoC: davinci: fixes for multi-component
Multi-component commit f0fba2ad broke a few things which this patch should
fix. Tested on the DM355 EVM. I've been as careful as I can, but it would be
good if those with access to other Davinci boards could test.
--
The multi-component commit put the initialisation of
snd_soc_dai.[capture|playback]_dma_data into snd_soc_dai_ops.hw_params of the
McBSP, McASP & VCIF drivers (davinci-i2s.c, davinci-mcasp.c & davinci-vcif.c).
The initialisation had to be moved from the probe function in these drivers
because davinci_*_dai changed from snd_soc_dai to snd_soc_dai_driver.
Unfortunately, the DMA params pointer is needed by davinci_pcm_open (in
davinci-pcm.c) before hw_params is called. I have moved the initialisation to
a new snd_soc_dai_ops.startup function in each of these drivers. This fix
indicates that all platforms that use davinci-pcm must have been broken and
need to test with this fix.
--
The multi-component commit also changed the McBSP driver name from
"davinci-asp" to "davinci-i2s" in davinci-i2s.c without updating the board
level references to the driver name. This change is understandable, as there
is a similarly named "davinci-mcasp" driver in davinci-mcasp.c.
There is probably no 'correct' name for this driver. The DM6446 datasheet
calls it the "ASP" and describes it as a "specialised McBSP". The DM355
datasheet calls it the "ASP" and describes it as a "specialised ASP". The
DM365 datasheet calls it the "McBSP". Rather than fix this problem by
reverting to "davinci-asp", I've elected to avoid future confusion with the
"davinci-mcasp" driver by changing it to "davinci-mcbsp", which is also
consistent with the names of the functions in the driver. There are other
fixes required, so it was never going to be as simple as a revert anyway.
--
The DM365 only has one McBSP port (of the McBSP platforms, only the DM355 has
2 ports), so I've changed the the id of the platform_device from 0 to -1.
--
In davinci-evm.c, the DM6446 EVM can no longer share a snd_soc_dai_link
structure with the DM355 EVM as they use different cpu DAI names (the DM355
has 2 ports and the EVM uses the second port, but the DM6446 only has 1 port).
This also means that the 2 boards need different snd_soc_card structures.
--
The codec_name entries in davinci-evm.c didn't match the i2c ids in the board
files. I have only checked and fixed the details of the names used for the
McBSP based platforms. Someone with a McASP based platform (eg DA8xx) should
check the others.
Signed-off-by: Chris Paulson-Ellis <chris@edesix.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2010-11-16 05:27:09 -07:00
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.name = "davinci-mcbsp",
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2016-04-18 06:32:41 -06:00
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.of_match_table = of_match_ptr(davinci_i2s_match),
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2009-06-05 04:28:23 -06:00
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},
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2008-02-18 03:40:22 -07:00
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};
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2011-11-24 19:09:27 -07:00
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module_platform_driver(davinci_mcbsp_driver);
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2008-12-03 12:26:35 -07:00
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2008-02-18 03:40:22 -07:00
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MODULE_AUTHOR("Vladimir Barinov");
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MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
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MODULE_LICENSE("GPL");
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