2013-02-15 02:11:57 -07:00
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/*
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* GHES/EDAC Linux driver
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*
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* This file may be distributed under the terms of the GNU General Public
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* License version 2.
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*
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2014-02-07 03:03:07 -07:00
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* Copyright (c) 2013 by Mauro Carvalho Chehab
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2013-02-15 02:11:57 -07:00
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*
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* Red Hat Inc. http://www.redhat.com
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*/
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2013-02-15 05:06:38 -07:00
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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2013-02-15 02:11:57 -07:00
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#include <acpi/ghes.h>
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#include <linux/edac.h>
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2013-02-14 05:11:08 -07:00
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#include <linux/dmi.h>
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2016-10-29 11:16:34 -06:00
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#include "edac_module.h"
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ghes_edac: Fix RAS tracing
With the current version of CPER, there's no way to associate an
error with the memory error. So, the error location in EDAC
layers is unused.
As CPER has its own idea about memory architectural layers, just
output whatever is there inside the driver's detail at the RAS
tracepoint.
The EDAC location keeps untouched, in the case that, in some future,
we could actually map the error into the dimm labels.
Now, the error message:
[ 72.396625] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 0
[ 72.396627] {1}[Hardware Error]: APEI generic hardware error status
[ 72.396628] {1}[Hardware Error]: severity: 2, corrected
[ 72.396630] {1}[Hardware Error]: section: 0, severity: 2, corrected
[ 72.396632] {1}[Hardware Error]: flags: 0x01
[ 72.396634] {1}[Hardware Error]: primary
[ 72.396635] {1}[Hardware Error]: section_type: memory error
[ 72.396637] {1}[Hardware Error]: error_status: 0x0000000000000400
[ 72.396638] {1}[Hardware Error]: node: 3
[ 72.396639] {1}[Hardware Error]: card: 0
[ 72.396640] {1}[Hardware Error]: module: 0
[ 72.396641] {1}[Hardware Error]: device: 0
[ 72.396643] {1}[Hardware Error]: error_type: 18, unknown
[ 72.396666] EDAC MC0: 1 CE reserved error (18) on unknown label (node:3 card:0 module:0 page:0x0 offset:0x0 grain:0 syndrome:0x0 - status(0x0000000000000400): Storage error in DRAM memory)
Is properly represented on the trace event:
kworker/0:2-584 [000] .... 72.396657: mc_event: 1 Corrected error: reserved error (18) on unknown label (mc:0 location:-1:-1:-1 address:0x00000000 grain:1 syndrome:0x00000000 APEI location: node:3 card:0 module:0 status(0x0000000000000400): Storage error in DRAM memory)
Tested on a 4 sockets E5-4650 Sandy Bridge machine.
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2013-02-19 17:35:41 -07:00
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#include <ras/ras_event.h>
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2013-02-15 02:11:57 -07:00
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struct ghes_edac_pvt {
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struct list_head list;
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struct ghes *ghes;
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struct mem_ctl_info *mci;
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2013-02-19 15:24:12 -07:00
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/* Buffers for the error handling routine */
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ghes_edac: Fix RAS tracing
With the current version of CPER, there's no way to associate an
error with the memory error. So, the error location in EDAC
layers is unused.
As CPER has its own idea about memory architectural layers, just
output whatever is there inside the driver's detail at the RAS
tracepoint.
The EDAC location keeps untouched, in the case that, in some future,
we could actually map the error into the dimm labels.
Now, the error message:
[ 72.396625] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 0
[ 72.396627] {1}[Hardware Error]: APEI generic hardware error status
[ 72.396628] {1}[Hardware Error]: severity: 2, corrected
[ 72.396630] {1}[Hardware Error]: section: 0, severity: 2, corrected
[ 72.396632] {1}[Hardware Error]: flags: 0x01
[ 72.396634] {1}[Hardware Error]: primary
[ 72.396635] {1}[Hardware Error]: section_type: memory error
[ 72.396637] {1}[Hardware Error]: error_status: 0x0000000000000400
[ 72.396638] {1}[Hardware Error]: node: 3
[ 72.396639] {1}[Hardware Error]: card: 0
[ 72.396640] {1}[Hardware Error]: module: 0
[ 72.396641] {1}[Hardware Error]: device: 0
[ 72.396643] {1}[Hardware Error]: error_type: 18, unknown
[ 72.396666] EDAC MC0: 1 CE reserved error (18) on unknown label (node:3 card:0 module:0 page:0x0 offset:0x0 grain:0 syndrome:0x0 - status(0x0000000000000400): Storage error in DRAM memory)
Is properly represented on the trace event:
kworker/0:2-584 [000] .... 72.396657: mc_event: 1 Corrected error: reserved error (18) on unknown label (mc:0 location:-1:-1:-1 address:0x00000000 grain:1 syndrome:0x00000000 APEI location: node:3 card:0 module:0 status(0x0000000000000400): Storage error in DRAM memory)
Tested on a 4 sockets E5-4650 Sandy Bridge machine.
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2013-02-19 17:35:41 -07:00
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char detail_location[240];
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2013-02-19 15:24:12 -07:00
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char other_detail[160];
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char msg[80];
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2013-02-15 02:11:57 -07:00
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};
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2017-08-16 02:33:44 -06:00
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static atomic_t ghes_init = ATOMIC_INIT(0);
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static struct ghes_edac_pvt *ghes_pvt;
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2013-02-15 02:11:57 -07:00
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2017-08-16 02:33:44 -06:00
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/*
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* Sync with other, potentially concurrent callers of
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* ghes_edac_report_mem_error(). We don't know what the
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* "inventive" firmware would do.
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*/
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static DEFINE_SPINLOCK(ghes_lock);
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2013-02-15 05:06:38 -07:00
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2017-08-23 16:54:45 -06:00
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/* "ghes_edac.force_load=1" skips the platform check */
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static bool __read_mostly force_load;
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module_param(force_load, bool, 0);
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2013-02-14 05:11:08 -07:00
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/* Memory Device - Type 17 of SMBIOS spec */
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struct memdev_dmi_entry {
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u8 type;
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u8 length;
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u16 handle;
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u16 phys_mem_array_handle;
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u16 mem_err_info_handle;
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u16 total_width;
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u16 data_width;
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u16 size;
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u8 form_factor;
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u8 device_set;
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u8 device_locator;
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u8 bank_locator;
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u8 memory_type;
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u16 type_detail;
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u16 speed;
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u8 manufacturer;
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u8 serial_number;
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u8 asset_tag;
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u8 part_number;
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u8 attributes;
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u32 extended_size;
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u16 conf_mem_clk_speed;
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} __attribute__((__packed__));
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struct ghes_edac_dimm_fill {
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struct mem_ctl_info *mci;
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unsigned count;
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};
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static void ghes_edac_count_dimms(const struct dmi_header *dh, void *arg)
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{
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int *num_dimm = arg;
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if (dh->type == DMI_ENTRY_MEM_DEVICE)
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(*num_dimm)++;
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}
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2018-09-18 19:59:00 -06:00
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static int get_dimm_smbios_index(u16 handle)
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{
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struct mem_ctl_info *mci = ghes_pvt->mci;
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int i;
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for (i = 0; i < mci->tot_dimms; i++) {
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if (mci->dimms[i]->smbios_handle == handle)
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return i;
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}
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return -1;
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}
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2013-02-14 05:11:08 -07:00
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static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg)
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{
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struct ghes_edac_dimm_fill *dimm_fill = arg;
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struct mem_ctl_info *mci = dimm_fill->mci;
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if (dh->type == DMI_ENTRY_MEM_DEVICE) {
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struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh;
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struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
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mci->n_layers,
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dimm_fill->count, 0, 0);
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2018-05-12 06:32:43 -06:00
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u16 rdr_mask = BIT(7) | BIT(13);
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2013-02-14 05:11:08 -07:00
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if (entry->size == 0xffff) {
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2013-02-15 05:06:38 -07:00
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pr_info("Can't get DIMM%i size\n",
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dimm_fill->count);
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2013-02-14 05:11:08 -07:00
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dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
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} else if (entry->size == 0x7fff) {
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dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
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} else {
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2018-05-12 06:32:43 -06:00
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if (entry->size & BIT(15))
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dimm->nr_pages = MiB_TO_PAGES((entry->size & 0x7fff) << 10);
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2013-02-14 05:11:08 -07:00
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else
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dimm->nr_pages = MiB_TO_PAGES(entry->size);
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}
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switch (entry->memory_type) {
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case 0x12:
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2018-05-12 06:32:43 -06:00
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if (entry->type_detail & BIT(13))
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2013-02-14 05:11:08 -07:00
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dimm->mtype = MEM_RDDR;
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else
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dimm->mtype = MEM_DDR;
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break;
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case 0x13:
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2018-05-12 06:32:43 -06:00
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if (entry->type_detail & BIT(13))
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2013-02-14 05:11:08 -07:00
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dimm->mtype = MEM_RDDR2;
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else
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dimm->mtype = MEM_DDR2;
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break;
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case 0x14:
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dimm->mtype = MEM_FB_DDR2;
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break;
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case 0x18:
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2018-05-12 06:32:43 -06:00
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if (entry->type_detail & BIT(12))
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2018-05-09 16:20:30 -06:00
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dimm->mtype = MEM_NVDIMM;
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2018-05-12 06:32:43 -06:00
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else if (entry->type_detail & BIT(13))
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2013-02-14 05:11:08 -07:00
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dimm->mtype = MEM_RDDR3;
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else
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dimm->mtype = MEM_DDR3;
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break;
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2018-05-09 16:20:30 -06:00
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case 0x1a:
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2018-05-12 06:32:43 -06:00
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if (entry->type_detail & BIT(12))
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2018-05-09 16:20:30 -06:00
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dimm->mtype = MEM_NVDIMM;
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2018-05-12 06:32:43 -06:00
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else if (entry->type_detail & BIT(13))
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2018-05-09 16:20:30 -06:00
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dimm->mtype = MEM_RDDR4;
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else
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dimm->mtype = MEM_DDR4;
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break;
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2013-02-14 05:11:08 -07:00
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default:
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2018-05-12 06:32:43 -06:00
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if (entry->type_detail & BIT(6))
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2013-02-14 05:11:08 -07:00
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dimm->mtype = MEM_RMBS;
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2018-05-12 06:32:43 -06:00
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else if ((entry->type_detail & rdr_mask) == rdr_mask)
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2013-02-14 05:11:08 -07:00
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dimm->mtype = MEM_RDR;
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2018-05-12 06:32:43 -06:00
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else if (entry->type_detail & BIT(7))
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2013-02-14 05:11:08 -07:00
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dimm->mtype = MEM_SDR;
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2018-05-12 06:32:43 -06:00
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else if (entry->type_detail & BIT(9))
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2013-02-14 05:11:08 -07:00
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dimm->mtype = MEM_EDO;
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else
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dimm->mtype = MEM_UNKNOWN;
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}
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/*
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* Actually, we can only detect if the memory has bits for
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* checksum or not
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*/
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if (entry->total_width == entry->data_width)
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dimm->edac_mode = EDAC_NONE;
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else
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dimm->edac_mode = EDAC_SECDED;
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dimm->dtype = DEV_UNKNOWN;
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dimm->grain = 128; /* Likely, worse case */
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/*
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* FIXME: It shouldn't be hard to also fill the DIMM labels
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*/
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if (dimm->nr_pages) {
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2013-02-15 05:06:38 -07:00
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edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
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2015-09-16 14:53:29 -06:00
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dimm_fill->count, edac_mem_types[dimm->mtype],
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2013-02-14 05:11:08 -07:00
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PAGES_TO_MiB(dimm->nr_pages),
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(dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
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2013-02-15 05:06:38 -07:00
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edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
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2013-02-14 05:11:08 -07:00
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entry->memory_type, entry->type_detail,
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entry->total_width, entry->data_width);
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}
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2018-09-18 19:59:00 -06:00
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dimm->smbios_handle = entry->handle;
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2013-02-14 05:11:08 -07:00
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dimm_fill->count++;
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}
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}
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2018-04-30 15:33:50 -06:00
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void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
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2013-02-15 02:11:57 -07:00
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{
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2013-02-15 02:36:27 -07:00
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enum hw_event_mc_err_type type;
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struct edac_raw_error_desc *e;
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struct mem_ctl_info *mci;
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2017-08-16 02:33:44 -06:00
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struct ghes_edac_pvt *pvt = ghes_pvt;
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unsigned long flags;
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2013-02-19 15:24:12 -07:00
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char *p;
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ghes_edac: Fix RAS tracing
With the current version of CPER, there's no way to associate an
error with the memory error. So, the error location in EDAC
layers is unused.
As CPER has its own idea about memory architectural layers, just
output whatever is there inside the driver's detail at the RAS
tracepoint.
The EDAC location keeps untouched, in the case that, in some future,
we could actually map the error into the dimm labels.
Now, the error message:
[ 72.396625] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 0
[ 72.396627] {1}[Hardware Error]: APEI generic hardware error status
[ 72.396628] {1}[Hardware Error]: severity: 2, corrected
[ 72.396630] {1}[Hardware Error]: section: 0, severity: 2, corrected
[ 72.396632] {1}[Hardware Error]: flags: 0x01
[ 72.396634] {1}[Hardware Error]: primary
[ 72.396635] {1}[Hardware Error]: section_type: memory error
[ 72.396637] {1}[Hardware Error]: error_status: 0x0000000000000400
[ 72.396638] {1}[Hardware Error]: node: 3
[ 72.396639] {1}[Hardware Error]: card: 0
[ 72.396640] {1}[Hardware Error]: module: 0
[ 72.396641] {1}[Hardware Error]: device: 0
[ 72.396643] {1}[Hardware Error]: error_type: 18, unknown
[ 72.396666] EDAC MC0: 1 CE reserved error (18) on unknown label (node:3 card:0 module:0 page:0x0 offset:0x0 grain:0 syndrome:0x0 - status(0x0000000000000400): Storage error in DRAM memory)
Is properly represented on the trace event:
kworker/0:2-584 [000] .... 72.396657: mc_event: 1 Corrected error: reserved error (18) on unknown label (mc:0 location:-1:-1:-1 address:0x00000000 grain:1 syndrome:0x00000000 APEI location: node:3 card:0 module:0 status(0x0000000000000400): Storage error in DRAM memory)
Tested on a 4 sockets E5-4650 Sandy Bridge machine.
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2013-02-19 17:35:41 -07:00
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u8 grain_bits;
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2013-02-15 02:36:27 -07:00
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2018-04-23 06:16:46 -06:00
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if (!pvt)
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2013-02-15 02:36:27 -07:00
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return;
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2017-08-16 02:33:44 -06:00
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/*
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* We can do the locking below because GHES defers error processing
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* from NMI to IRQ context. Whenever that changes, we'd at least
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* know.
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*/
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if (WARN_ON_ONCE(in_nmi()))
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return;
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spin_lock_irqsave(&ghes_lock, flags);
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2013-02-15 02:36:27 -07:00
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mci = pvt->mci;
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e = &mci->error_desc;
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/* Cleans the error report buffer */
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memset(e, 0, sizeof (*e));
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e->error_count = 1;
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2013-02-19 15:24:12 -07:00
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strcpy(e->label, "unknown label");
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e->msg = pvt->msg;
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e->other_detail = pvt->other_detail;
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e->top_layer = -1;
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e->mid_layer = -1;
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e->low_layer = -1;
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*pvt->other_detail = '\0';
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*pvt->msg = '\0';
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2013-02-15 02:36:27 -07:00
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switch (sev) {
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case GHES_SEV_CORRECTED:
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type = HW_EVENT_ERR_CORRECTED;
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break;
|
|
|
|
case GHES_SEV_RECOVERABLE:
|
|
|
|
type = HW_EVENT_ERR_UNCORRECTED;
|
|
|
|
break;
|
|
|
|
case GHES_SEV_PANIC:
|
|
|
|
type = HW_EVENT_ERR_FATAL;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
case GHES_SEV_NO:
|
|
|
|
type = HW_EVENT_ERR_INFO;
|
|
|
|
}
|
|
|
|
|
2013-02-19 15:24:12 -07:00
|
|
|
edac_dbg(1, "error validation_bits: 0x%08llx\n",
|
|
|
|
(long long)mem_err->validation_bits);
|
|
|
|
|
|
|
|
/* Error type, mapped on e->msg */
|
|
|
|
if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
|
|
|
|
p = pvt->msg;
|
|
|
|
switch (mem_err->error_type) {
|
|
|
|
case 0:
|
|
|
|
p += sprintf(p, "Unknown");
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
p += sprintf(p, "No error");
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
p += sprintf(p, "Single-bit ECC");
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
p += sprintf(p, "Multi-bit ECC");
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
p += sprintf(p, "Single-symbol ChipKill ECC");
|
|
|
|
break;
|
|
|
|
case 5:
|
|
|
|
p += sprintf(p, "Multi-symbol ChipKill ECC");
|
|
|
|
break;
|
|
|
|
case 6:
|
|
|
|
p += sprintf(p, "Master abort");
|
|
|
|
break;
|
|
|
|
case 7:
|
|
|
|
p += sprintf(p, "Target abort");
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
p += sprintf(p, "Parity Error");
|
|
|
|
break;
|
|
|
|
case 9:
|
|
|
|
p += sprintf(p, "Watchdog timeout");
|
|
|
|
break;
|
|
|
|
case 10:
|
|
|
|
p += sprintf(p, "Invalid address");
|
|
|
|
break;
|
|
|
|
case 11:
|
|
|
|
p += sprintf(p, "Mirror Broken");
|
|
|
|
break;
|
|
|
|
case 12:
|
|
|
|
p += sprintf(p, "Memory Sparing");
|
|
|
|
break;
|
|
|
|
case 13:
|
|
|
|
p += sprintf(p, "Scrub corrected error");
|
|
|
|
break;
|
|
|
|
case 14:
|
|
|
|
p += sprintf(p, "Scrub uncorrected error");
|
|
|
|
break;
|
|
|
|
case 15:
|
|
|
|
p += sprintf(p, "Physical Memory Map-out event");
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
p += sprintf(p, "reserved error (%d)",
|
|
|
|
mem_err->error_type);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
strcpy(pvt->msg, "unknown error");
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Error address */
|
2013-10-18 15:30:13 -06:00
|
|
|
if (mem_err->validation_bits & CPER_MEM_VALID_PA) {
|
2013-02-19 15:24:12 -07:00
|
|
|
e->page_frame_number = mem_err->physical_addr >> PAGE_SHIFT;
|
|
|
|
e->offset_in_page = mem_err->physical_addr & ~PAGE_MASK;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Error grain */
|
2013-10-18 15:30:13 -06:00
|
|
|
if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
|
2013-02-19 15:24:12 -07:00
|
|
|
e->grain = ~(mem_err->physical_addr_mask & ~PAGE_MASK);
|
|
|
|
|
|
|
|
/* Memory error location, mapped on e->location */
|
|
|
|
p = e->location;
|
|
|
|
if (mem_err->validation_bits & CPER_MEM_VALID_NODE)
|
|
|
|
p += sprintf(p, "node:%d ", mem_err->node);
|
|
|
|
if (mem_err->validation_bits & CPER_MEM_VALID_CARD)
|
|
|
|
p += sprintf(p, "card:%d ", mem_err->card);
|
|
|
|
if (mem_err->validation_bits & CPER_MEM_VALID_MODULE)
|
|
|
|
p += sprintf(p, "module:%d ", mem_err->module);
|
2013-10-18 15:30:38 -06:00
|
|
|
if (mem_err->validation_bits & CPER_MEM_VALID_RANK_NUMBER)
|
|
|
|
p += sprintf(p, "rank:%d ", mem_err->rank);
|
2013-02-19 15:24:12 -07:00
|
|
|
if (mem_err->validation_bits & CPER_MEM_VALID_BANK)
|
|
|
|
p += sprintf(p, "bank:%d ", mem_err->bank);
|
|
|
|
if (mem_err->validation_bits & CPER_MEM_VALID_ROW)
|
|
|
|
p += sprintf(p, "row:%d ", mem_err->row);
|
|
|
|
if (mem_err->validation_bits & CPER_MEM_VALID_COLUMN)
|
|
|
|
p += sprintf(p, "col:%d ", mem_err->column);
|
|
|
|
if (mem_err->validation_bits & CPER_MEM_VALID_BIT_POSITION)
|
|
|
|
p += sprintf(p, "bit_pos:%d ", mem_err->bit_pos);
|
2013-10-18 15:30:38 -06:00
|
|
|
if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
|
|
|
|
const char *bank = NULL, *device = NULL;
|
2018-09-18 19:59:00 -06:00
|
|
|
int index = -1;
|
|
|
|
|
2013-10-18 15:30:38 -06:00
|
|
|
dmi_memdev_name(mem_err->mem_dev_handle, &bank, &device);
|
|
|
|
if (bank != NULL && device != NULL)
|
|
|
|
p += sprintf(p, "DIMM location:%s %s ", bank, device);
|
|
|
|
else
|
|
|
|
p += sprintf(p, "DIMM DMI handle: 0x%.4x ",
|
|
|
|
mem_err->mem_dev_handle);
|
2018-09-18 19:59:00 -06:00
|
|
|
|
|
|
|
index = get_dimm_smbios_index(mem_err->mem_dev_handle);
|
|
|
|
if (index >= 0) {
|
|
|
|
e->top_layer = index;
|
|
|
|
e->enable_per_layer_report = true;
|
|
|
|
}
|
|
|
|
|
2013-10-18 15:30:38 -06:00
|
|
|
}
|
2013-02-19 15:24:12 -07:00
|
|
|
if (p > e->location)
|
|
|
|
*(p - 1) = '\0';
|
|
|
|
|
|
|
|
/* All other fields are mapped on e->other_detail */
|
|
|
|
p = pvt->other_detail;
|
|
|
|
if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_STATUS) {
|
|
|
|
u64 status = mem_err->error_status;
|
|
|
|
|
|
|
|
p += sprintf(p, "status(0x%016llx): ", (long long)status);
|
|
|
|
switch ((status >> 8) & 0xff) {
|
|
|
|
case 1:
|
|
|
|
p += sprintf(p, "Error detected internal to the component ");
|
|
|
|
break;
|
|
|
|
case 16:
|
|
|
|
p += sprintf(p, "Error detected in the bus ");
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
p += sprintf(p, "Storage error in DRAM memory ");
|
|
|
|
break;
|
|
|
|
case 5:
|
|
|
|
p += sprintf(p, "Storage error in TLB ");
|
|
|
|
break;
|
|
|
|
case 6:
|
|
|
|
p += sprintf(p, "Storage error in cache ");
|
|
|
|
break;
|
|
|
|
case 7:
|
|
|
|
p += sprintf(p, "Error in one or more functional units ");
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
p += sprintf(p, "component failed self test ");
|
|
|
|
break;
|
|
|
|
case 9:
|
|
|
|
p += sprintf(p, "Overflow or undervalue of internal queue ");
|
|
|
|
break;
|
|
|
|
case 17:
|
|
|
|
p += sprintf(p, "Virtual address not found on IO-TLB or IO-PDIR ");
|
|
|
|
break;
|
|
|
|
case 18:
|
|
|
|
p += sprintf(p, "Improper access error ");
|
|
|
|
break;
|
|
|
|
case 19:
|
|
|
|
p += sprintf(p, "Access to a memory address which is not mapped to any component ");
|
|
|
|
break;
|
|
|
|
case 20:
|
|
|
|
p += sprintf(p, "Loss of Lockstep ");
|
|
|
|
break;
|
|
|
|
case 21:
|
|
|
|
p += sprintf(p, "Response not associated with a request ");
|
|
|
|
break;
|
|
|
|
case 22:
|
|
|
|
p += sprintf(p, "Bus parity error - must also set the A, C, or D Bits ");
|
|
|
|
break;
|
|
|
|
case 23:
|
|
|
|
p += sprintf(p, "Detection of a PATH_ERROR ");
|
|
|
|
break;
|
|
|
|
case 25:
|
|
|
|
p += sprintf(p, "Bus operation timeout ");
|
|
|
|
break;
|
|
|
|
case 26:
|
|
|
|
p += sprintf(p, "A read was issued to data that has been poisoned ");
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
p += sprintf(p, "reserved ");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (mem_err->validation_bits & CPER_MEM_VALID_REQUESTOR_ID)
|
|
|
|
p += sprintf(p, "requestorID: 0x%016llx ",
|
|
|
|
(long long)mem_err->requestor_id);
|
|
|
|
if (mem_err->validation_bits & CPER_MEM_VALID_RESPONDER_ID)
|
|
|
|
p += sprintf(p, "responderID: 0x%016llx ",
|
|
|
|
(long long)mem_err->responder_id);
|
|
|
|
if (mem_err->validation_bits & CPER_MEM_VALID_TARGET_ID)
|
|
|
|
p += sprintf(p, "targetID: 0x%016llx ",
|
|
|
|
(long long)mem_err->responder_id);
|
|
|
|
if (p > pvt->other_detail)
|
|
|
|
*(p - 1) = '\0';
|
2013-02-15 02:36:27 -07:00
|
|
|
|
ghes_edac: Fix RAS tracing
With the current version of CPER, there's no way to associate an
error with the memory error. So, the error location in EDAC
layers is unused.
As CPER has its own idea about memory architectural layers, just
output whatever is there inside the driver's detail at the RAS
tracepoint.
The EDAC location keeps untouched, in the case that, in some future,
we could actually map the error into the dimm labels.
Now, the error message:
[ 72.396625] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 0
[ 72.396627] {1}[Hardware Error]: APEI generic hardware error status
[ 72.396628] {1}[Hardware Error]: severity: 2, corrected
[ 72.396630] {1}[Hardware Error]: section: 0, severity: 2, corrected
[ 72.396632] {1}[Hardware Error]: flags: 0x01
[ 72.396634] {1}[Hardware Error]: primary
[ 72.396635] {1}[Hardware Error]: section_type: memory error
[ 72.396637] {1}[Hardware Error]: error_status: 0x0000000000000400
[ 72.396638] {1}[Hardware Error]: node: 3
[ 72.396639] {1}[Hardware Error]: card: 0
[ 72.396640] {1}[Hardware Error]: module: 0
[ 72.396641] {1}[Hardware Error]: device: 0
[ 72.396643] {1}[Hardware Error]: error_type: 18, unknown
[ 72.396666] EDAC MC0: 1 CE reserved error (18) on unknown label (node:3 card:0 module:0 page:0x0 offset:0x0 grain:0 syndrome:0x0 - status(0x0000000000000400): Storage error in DRAM memory)
Is properly represented on the trace event:
kworker/0:2-584 [000] .... 72.396657: mc_event: 1 Corrected error: reserved error (18) on unknown label (mc:0 location:-1:-1:-1 address:0x00000000 grain:1 syndrome:0x00000000 APEI location: node:3 card:0 module:0 status(0x0000000000000400): Storage error in DRAM memory)
Tested on a 4 sockets E5-4650 Sandy Bridge machine.
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2013-02-19 17:35:41 -07:00
|
|
|
/* Generate the trace event */
|
|
|
|
grain_bits = fls_long(e->grain);
|
2014-08-01 02:25:14 -06:00
|
|
|
snprintf(pvt->detail_location, sizeof(pvt->detail_location),
|
|
|
|
"APEI location: %s %s", e->location, e->other_detail);
|
ghes_edac: Fix RAS tracing
With the current version of CPER, there's no way to associate an
error with the memory error. So, the error location in EDAC
layers is unused.
As CPER has its own idea about memory architectural layers, just
output whatever is there inside the driver's detail at the RAS
tracepoint.
The EDAC location keeps untouched, in the case that, in some future,
we could actually map the error into the dimm labels.
Now, the error message:
[ 72.396625] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 0
[ 72.396627] {1}[Hardware Error]: APEI generic hardware error status
[ 72.396628] {1}[Hardware Error]: severity: 2, corrected
[ 72.396630] {1}[Hardware Error]: section: 0, severity: 2, corrected
[ 72.396632] {1}[Hardware Error]: flags: 0x01
[ 72.396634] {1}[Hardware Error]: primary
[ 72.396635] {1}[Hardware Error]: section_type: memory error
[ 72.396637] {1}[Hardware Error]: error_status: 0x0000000000000400
[ 72.396638] {1}[Hardware Error]: node: 3
[ 72.396639] {1}[Hardware Error]: card: 0
[ 72.396640] {1}[Hardware Error]: module: 0
[ 72.396641] {1}[Hardware Error]: device: 0
[ 72.396643] {1}[Hardware Error]: error_type: 18, unknown
[ 72.396666] EDAC MC0: 1 CE reserved error (18) on unknown label (node:3 card:0 module:0 page:0x0 offset:0x0 grain:0 syndrome:0x0 - status(0x0000000000000400): Storage error in DRAM memory)
Is properly represented on the trace event:
kworker/0:2-584 [000] .... 72.396657: mc_event: 1 Corrected error: reserved error (18) on unknown label (mc:0 location:-1:-1:-1 address:0x00000000 grain:1 syndrome:0x00000000 APEI location: node:3 card:0 module:0 status(0x0000000000000400): Storage error in DRAM memory)
Tested on a 4 sockets E5-4650 Sandy Bridge machine.
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2013-02-19 17:35:41 -07:00
|
|
|
trace_mc_event(type, e->msg, e->label, e->error_count,
|
|
|
|
mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer,
|
2015-10-20 05:45:38 -06:00
|
|
|
(e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,
|
ghes_edac: Fix RAS tracing
With the current version of CPER, there's no way to associate an
error with the memory error. So, the error location in EDAC
layers is unused.
As CPER has its own idea about memory architectural layers, just
output whatever is there inside the driver's detail at the RAS
tracepoint.
The EDAC location keeps untouched, in the case that, in some future,
we could actually map the error into the dimm labels.
Now, the error message:
[ 72.396625] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 0
[ 72.396627] {1}[Hardware Error]: APEI generic hardware error status
[ 72.396628] {1}[Hardware Error]: severity: 2, corrected
[ 72.396630] {1}[Hardware Error]: section: 0, severity: 2, corrected
[ 72.396632] {1}[Hardware Error]: flags: 0x01
[ 72.396634] {1}[Hardware Error]: primary
[ 72.396635] {1}[Hardware Error]: section_type: memory error
[ 72.396637] {1}[Hardware Error]: error_status: 0x0000000000000400
[ 72.396638] {1}[Hardware Error]: node: 3
[ 72.396639] {1}[Hardware Error]: card: 0
[ 72.396640] {1}[Hardware Error]: module: 0
[ 72.396641] {1}[Hardware Error]: device: 0
[ 72.396643] {1}[Hardware Error]: error_type: 18, unknown
[ 72.396666] EDAC MC0: 1 CE reserved error (18) on unknown label (node:3 card:0 module:0 page:0x0 offset:0x0 grain:0 syndrome:0x0 - status(0x0000000000000400): Storage error in DRAM memory)
Is properly represented on the trace event:
kworker/0:2-584 [000] .... 72.396657: mc_event: 1 Corrected error: reserved error (18) on unknown label (mc:0 location:-1:-1:-1 address:0x00000000 grain:1 syndrome:0x00000000 APEI location: node:3 card:0 module:0 status(0x0000000000000400): Storage error in DRAM memory)
Tested on a 4 sockets E5-4650 Sandy Bridge machine.
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2013-02-19 17:35:41 -07:00
|
|
|
grain_bits, e->syndrome, pvt->detail_location);
|
|
|
|
|
2013-02-15 02:36:27 -07:00
|
|
|
edac_raw_mc_handle_error(type, mci, e);
|
2017-08-16 02:33:44 -06:00
|
|
|
spin_unlock_irqrestore(&ghes_lock, flags);
|
2013-02-15 02:11:57 -07:00
|
|
|
}
|
|
|
|
|
2017-08-23 16:54:45 -06:00
|
|
|
/*
|
|
|
|
* Known systems that are safe to enable this module.
|
|
|
|
*/
|
|
|
|
static struct acpi_platform_list plat_list[] = {
|
|
|
|
{"HPE ", "Server ", 0, ACPI_SIG_FADT, all_versions},
|
|
|
|
{ } /* End */
|
|
|
|
};
|
|
|
|
|
2013-02-15 02:11:57 -07:00
|
|
|
int ghes_edac_register(struct ghes *ghes, struct device *dev)
|
|
|
|
{
|
2013-02-14 05:11:08 -07:00
|
|
|
bool fake = false;
|
|
|
|
int rc, num_dimm = 0;
|
2013-02-15 02:11:57 -07:00
|
|
|
struct mem_ctl_info *mci;
|
|
|
|
struct edac_mc_layer layers[1];
|
2013-02-14 05:11:08 -07:00
|
|
|
struct ghes_edac_dimm_fill dimm_fill;
|
2018-05-18 05:13:31 -06:00
|
|
|
int idx = -1;
|
2017-08-23 16:54:45 -06:00
|
|
|
|
2018-05-18 05:13:31 -06:00
|
|
|
if (IS_ENABLED(CONFIG_X86)) {
|
|
|
|
/* Check if safe to enable on this system */
|
|
|
|
idx = acpi_match_platform_list(plat_list);
|
|
|
|
if (!force_load && idx < 0)
|
|
|
|
return -ENODEV;
|
|
|
|
} else {
|
|
|
|
idx = 0;
|
|
|
|
}
|
2013-02-14 05:11:08 -07:00
|
|
|
|
2017-08-16 02:33:44 -06:00
|
|
|
/*
|
|
|
|
* We have only one logical memory controller to which all DIMMs belong.
|
|
|
|
*/
|
|
|
|
if (atomic_inc_return(&ghes_init) > 1)
|
|
|
|
return 0;
|
|
|
|
|
2013-02-14 05:11:08 -07:00
|
|
|
/* Get the number of DIMMs */
|
|
|
|
dmi_walk(ghes_edac_count_dimms, &num_dimm);
|
|
|
|
|
|
|
|
/* Check if we've got a bogus BIOS */
|
|
|
|
if (num_dimm == 0) {
|
|
|
|
fake = true;
|
|
|
|
num_dimm = 1;
|
|
|
|
}
|
2013-02-15 02:11:57 -07:00
|
|
|
|
|
|
|
layers[0].type = EDAC_MC_LAYER_ALL_MEM;
|
2013-02-14 05:11:08 -07:00
|
|
|
layers[0].size = num_dimm;
|
2013-02-15 02:11:57 -07:00
|
|
|
layers[0].is_virt_csrow = true;
|
|
|
|
|
2017-08-16 02:33:44 -06:00
|
|
|
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_edac_pvt));
|
2013-02-15 02:11:57 -07:00
|
|
|
if (!mci) {
|
2013-02-15 05:06:38 -07:00
|
|
|
pr_info("Can't allocate memory for EDAC data\n");
|
2013-02-15 02:11:57 -07:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2017-08-16 02:33:44 -06:00
|
|
|
ghes_pvt = mci->pvt_info;
|
|
|
|
ghes_pvt->ghes = ghes;
|
|
|
|
ghes_pvt->mci = mci;
|
2013-02-15 02:11:57 -07:00
|
|
|
|
2017-08-16 02:33:44 -06:00
|
|
|
mci->pdev = dev;
|
2013-02-15 02:11:57 -07:00
|
|
|
mci->mtype_cap = MEM_FLAG_EMPTY;
|
|
|
|
mci->edac_ctl_cap = EDAC_FLAG_NONE;
|
|
|
|
mci->edac_cap = EDAC_FLAG_NONE;
|
|
|
|
mci->mod_name = "ghes_edac.c";
|
|
|
|
mci->ctl_name = "ghes_edac";
|
|
|
|
mci->dev_name = "ghes";
|
|
|
|
|
2017-08-23 16:54:45 -06:00
|
|
|
if (fake) {
|
|
|
|
pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
|
|
|
|
pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
|
|
|
|
pr_info("work on such system. Use this driver with caution\n");
|
|
|
|
} else if (idx < 0) {
|
2017-08-16 02:33:44 -06:00
|
|
|
pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n");
|
|
|
|
pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n");
|
|
|
|
pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
|
|
|
|
pr_info("If you find incorrect reports, please contact your hardware vendor\n");
|
|
|
|
pr_info("to correct its BIOS.\n");
|
|
|
|
pr_info("This system has %d DIMM sockets.\n", num_dimm);
|
2013-02-15 05:06:38 -07:00
|
|
|
}
|
|
|
|
|
2013-02-14 05:11:08 -07:00
|
|
|
if (!fake) {
|
2017-08-16 02:33:44 -06:00
|
|
|
dimm_fill.count = 0;
|
|
|
|
dimm_fill.mci = mci;
|
|
|
|
dmi_walk(ghes_edac_dmidecode, &dimm_fill);
|
2013-02-14 05:11:08 -07:00
|
|
|
} else {
|
|
|
|
struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
|
|
|
|
mci->n_layers, 0, 0, 0);
|
2013-02-15 02:11:57 -07:00
|
|
|
|
2013-02-15 05:06:38 -07:00
|
|
|
dimm->nr_pages = 1;
|
2013-02-14 05:11:08 -07:00
|
|
|
dimm->grain = 128;
|
|
|
|
dimm->mtype = MEM_UNKNOWN;
|
|
|
|
dimm->dtype = DEV_UNKNOWN;
|
|
|
|
dimm->edac_mode = EDAC_SECDED;
|
|
|
|
}
|
2013-02-15 02:11:57 -07:00
|
|
|
|
|
|
|
rc = edac_mc_add_mc(mci);
|
|
|
|
if (rc < 0) {
|
2013-02-15 05:06:38 -07:00
|
|
|
pr_info("Can't register at EDAC core\n");
|
2013-02-15 02:11:57 -07:00
|
|
|
edac_mc_free(mci);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ghes_edac_unregister(struct ghes *ghes)
|
|
|
|
{
|
|
|
|
struct mem_ctl_info *mci;
|
2017-08-16 02:33:44 -06:00
|
|
|
|
2018-04-26 04:16:49 -06:00
|
|
|
if (!ghes_pvt)
|
|
|
|
return;
|
|
|
|
|
2017-08-16 02:33:44 -06:00
|
|
|
mci = ghes_pvt->mci;
|
|
|
|
edac_mc_del_mc(mci->pdev);
|
|
|
|
edac_mc_free(mci);
|
2013-02-15 02:11:57 -07:00
|
|
|
}
|