2016-11-10 07:29:37 -07:00
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/*
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* Copyright (C) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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* Copyright (C) 2014 Endless Mobile
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* Written by:
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* Jasper St. Pierre <jstpierre@mecheye.net>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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2018-11-06 02:40:02 -07:00
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#include <linux/bitfield.h>
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2016-11-10 07:29:37 -07:00
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#include <linux/platform_device.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_plane_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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2018-11-19 03:02:39 -07:00
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#include <drm/drm_gem_framebuffer_helper.h>
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2016-11-10 07:29:37 -07:00
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#include <drm/drm_rect.h>
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#include "meson_plane.h"
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#include "meson_vpp.h"
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#include "meson_viu.h"
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#include "meson_canvas.h"
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#include "meson_registers.h"
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2018-11-06 02:40:02 -07:00
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/* OSD_SCI_WH_M1 */
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#define SCI_WH_M1_W(w) FIELD_PREP(GENMASK(28, 16), w)
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#define SCI_WH_M1_H(h) FIELD_PREP(GENMASK(12, 0), h)
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/* OSD_SCO_H_START_END */
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/* OSD_SCO_V_START_END */
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#define SCO_HV_START(start) FIELD_PREP(GENMASK(27, 16), start)
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#define SCO_HV_END(end) FIELD_PREP(GENMASK(11, 0), end)
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/* OSD_SC_CTRL0 */
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#define SC_CTRL0_PATH_EN BIT(3)
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#define SC_CTRL0_SEL_OSD1 BIT(2)
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/* OSD_VSC_CTRL0 */
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#define VSC_BANK_LEN(value) FIELD_PREP(GENMASK(2, 0), value)
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#define VSC_TOP_INI_RCV_NUM(value) FIELD_PREP(GENMASK(6, 3), value)
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#define VSC_TOP_RPT_L0_NUM(value) FIELD_PREP(GENMASK(9, 8), value)
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#define VSC_BOT_INI_RCV_NUM(value) FIELD_PREP(GENMASK(14, 11), value)
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#define VSC_BOT_RPT_L0_NUM(value) FIELD_PREP(GENMASK(17, 16), value)
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#define VSC_PROG_INTERLACE BIT(23)
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#define VSC_VERTICAL_SCALER_EN BIT(24)
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/* OSD_VSC_INI_PHASE */
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#define VSC_INI_PHASE_BOT(bottom) FIELD_PREP(GENMASK(31, 16), bottom)
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#define VSC_INI_PHASE_TOP(top) FIELD_PREP(GENMASK(15, 0), top)
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/* OSD_HSC_CTRL0 */
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#define HSC_BANK_LENGTH(value) FIELD_PREP(GENMASK(2, 0), value)
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#define HSC_INI_RCV_NUM0(value) FIELD_PREP(GENMASK(6, 3), value)
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#define HSC_RPT_P0_NUM0(value) FIELD_PREP(GENMASK(9, 8), value)
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#define HSC_HORIZ_SCALER_EN BIT(22)
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/* VPP_OSD_VSC_PHASE_STEP */
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/* VPP_OSD_HSC_PHASE_STEP */
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#define SC_PHASE_STEP(value) FIELD_PREP(GENMASK(27, 0), value)
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2016-11-10 07:29:37 -07:00
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struct meson_plane {
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struct drm_plane base;
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struct meson_drm *priv;
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2018-11-28 03:07:34 -07:00
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bool enabled;
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2016-11-10 07:29:37 -07:00
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};
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#define to_meson_plane(x) container_of(x, struct meson_plane, base)
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2018-11-06 02:40:02 -07:00
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#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
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2016-11-10 07:29:37 -07:00
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static int meson_plane_atomic_check(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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struct drm_crtc_state *crtc_state;
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2017-01-02 08:09:59 -07:00
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if (!state->crtc)
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return 0;
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2016-11-10 07:29:37 -07:00
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crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
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if (IS_ERR(crtc_state))
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return PTR_ERR(crtc_state);
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2018-11-06 02:40:02 -07:00
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/*
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* Only allow :
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* - Upscaling up to 5x, vertical and horizontal
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* - Final coordinates must match crtc size
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*/
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2018-01-23 10:08:57 -07:00
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return drm_atomic_helper_check_plane_state(state, crtc_state,
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2018-11-06 02:40:02 -07:00
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FRAC_16_16(1, 5),
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2017-11-01 14:16:19 -06:00
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DRM_PLANE_HELPER_NO_SCALING,
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2018-11-06 02:40:02 -07:00
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false, true);
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2016-11-10 07:29:37 -07:00
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}
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/* Takes a fixed 16.16 number and converts it to integer. */
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static inline int64_t fixed16_to_int(int64_t value)
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{
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return value >> 16;
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}
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static void meson_plane_atomic_update(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct meson_plane *meson_plane = to_meson_plane(plane);
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struct drm_plane_state *state = plane->state;
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2018-11-06 02:40:02 -07:00
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struct drm_rect dest = drm_plane_state_dest(state);
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2016-11-10 07:29:37 -07:00
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struct meson_drm *priv = meson_plane->priv;
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2018-11-06 02:40:02 -07:00
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struct drm_framebuffer *fb = state->fb;
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2016-11-10 07:29:37 -07:00
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struct drm_gem_cma_object *gem;
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unsigned long flags;
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2018-11-06 02:40:02 -07:00
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int vsc_ini_rcv_num, vsc_ini_rpt_p0_num;
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int vsc_bot_rcv_num, vsc_bot_rpt_p0_num;
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int hsc_ini_rcv_num, hsc_ini_rpt_p0_num;
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int hf_phase_step, vf_phase_step;
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int src_w, src_h, dst_w, dst_h;
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int bot_ini_phase;
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int hf_bank_len;
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int vf_bank_len;
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2018-11-05 03:45:08 -07:00
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u8 canvas_id_osd1;
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2016-11-10 07:29:37 -07:00
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/*
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* Update Coordinates
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* Update Formats
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* Update Buffer
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* Enable Plane
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*/
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spin_lock_irqsave(&priv->drm->event_lock, flags);
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/* Enable OSD and BLK0, set max global alpha */
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priv->viu.osd1_ctrl_stat = OSD_ENABLE |
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(0xFF << OSD_GLOBAL_ALPHA_SHIFT) |
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OSD_BLK0_ENABLE;
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2018-11-05 03:45:08 -07:00
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if (priv->canvas)
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canvas_id_osd1 = priv->canvas_id_osd1;
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else
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canvas_id_osd1 = MESON_CANVAS_ID_OSD1;
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2016-11-10 07:29:37 -07:00
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/* Set up BLK0 to point to the right canvas */
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2018-11-05 03:45:08 -07:00
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priv->viu.osd1_blk0_cfg[0] = ((canvas_id_osd1 << OSD_CANVAS_SEL) |
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2016-11-10 07:29:37 -07:00
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OSD_ENDIANNESS_LE);
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/* On GXBB, Use the old non-HDR RGB2YUV converter */
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if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
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priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB;
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2016-12-14 14:32:55 -07:00
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switch (fb->format->format) {
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2016-11-10 07:29:37 -07:00
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case DRM_FORMAT_XRGB8888:
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/* For XRGB, replace the pixel's alpha by 0xFF */
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writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN,
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priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
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priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
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OSD_COLOR_MATRIX_32_ARGB;
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break;
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case DRM_FORMAT_ARGB8888:
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/* For ARGB, use the pixel's alpha */
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writel_bits_relaxed(OSD_REPLACE_EN, 0,
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priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
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priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
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OSD_COLOR_MATRIX_32_ARGB;
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break;
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case DRM_FORMAT_RGB888:
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priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_24 |
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OSD_COLOR_MATRIX_24_RGB;
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break;
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case DRM_FORMAT_RGB565:
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priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_16 |
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OSD_COLOR_MATRIX_16_RGB565;
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break;
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};
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2018-11-06 02:40:02 -07:00
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/* Default scaler parameters */
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vsc_bot_rcv_num = 0;
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vsc_bot_rpt_p0_num = 0;
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hf_bank_len = 4;
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vf_bank_len = 4;
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if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
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vsc_bot_rcv_num = 6;
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vsc_bot_rpt_p0_num = 2;
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}
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hsc_ini_rcv_num = hf_bank_len;
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vsc_ini_rcv_num = vf_bank_len;
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hsc_ini_rpt_p0_num = (hf_bank_len / 2) - 1;
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vsc_ini_rpt_p0_num = (vf_bank_len / 2) - 1;
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src_w = fixed16_to_int(state->src_w);
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src_h = fixed16_to_int(state->src_h);
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dst_w = state->crtc_w;
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dst_h = state->crtc_h;
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2018-11-06 02:40:01 -07:00
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/*
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* When the output is interlaced, the OSD must switch between
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* each field using the INTERLACE_SEL_ODD (0) of VIU_OSD1_BLK0_CFG_W0
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* at each vsync.
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* But the vertical scaler can provide such funtionnality if
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* is configured for 2:1 scaling with interlace options enabled.
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*/
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2016-11-10 07:29:37 -07:00
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if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
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dest.y1 /= 2;
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dest.y2 /= 2;
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2018-11-06 02:40:02 -07:00
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dst_h /= 2;
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}
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hf_phase_step = ((src_w << 18) / dst_w) << 6;
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vf_phase_step = (src_h << 20) / dst_h;
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if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
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bot_ini_phase = ((vf_phase_step / 2) >> 4);
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else
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bot_ini_phase = 0;
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2018-11-06 02:40:01 -07:00
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2018-11-06 02:40:02 -07:00
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vf_phase_step = (vf_phase_step << 4);
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2018-11-06 02:40:01 -07:00
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2018-11-06 02:40:02 -07:00
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/* In interlaced mode, scaler is always active */
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if (src_h != dst_h || src_w != dst_w) {
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priv->viu.osd_sc_i_wh_m1 = SCI_WH_M1_W(src_w - 1) |
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SCI_WH_M1_H(src_h - 1);
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priv->viu.osd_sc_o_h_start_end = SCO_HV_START(dest.x1) |
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SCO_HV_END(dest.x2 - 1);
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priv->viu.osd_sc_o_v_start_end = SCO_HV_START(dest.y1) |
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SCO_HV_END(dest.y2 - 1);
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/* Enable OSD Scaler */
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priv->viu.osd_sc_ctrl0 = SC_CTRL0_PATH_EN | SC_CTRL0_SEL_OSD1;
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} else {
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priv->viu.osd_sc_i_wh_m1 = 0;
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priv->viu.osd_sc_o_h_start_end = 0;
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priv->viu.osd_sc_o_v_start_end = 0;
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priv->viu.osd_sc_ctrl0 = 0;
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}
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2018-11-06 02:40:01 -07:00
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2018-11-06 02:40:02 -07:00
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/* In interlaced mode, vertical scaler is always active */
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if (src_h != dst_h) {
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2018-11-06 02:40:01 -07:00
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priv->viu.osd_sc_v_ctrl0 =
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2018-11-06 02:40:02 -07:00
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VSC_BANK_LEN(vf_bank_len) |
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VSC_TOP_INI_RCV_NUM(vsc_ini_rcv_num) |
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VSC_TOP_RPT_L0_NUM(vsc_ini_rpt_p0_num) |
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VSC_VERTICAL_SCALER_EN;
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if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
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priv->viu.osd_sc_v_ctrl0 |=
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VSC_BOT_INI_RCV_NUM(vsc_bot_rcv_num) |
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VSC_BOT_RPT_L0_NUM(vsc_bot_rpt_p0_num) |
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VSC_PROG_INTERLACE;
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priv->viu.osd_sc_v_phase_step = SC_PHASE_STEP(vf_phase_step);
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priv->viu.osd_sc_v_ini_phase = VSC_INI_PHASE_BOT(bot_ini_phase);
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} else {
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priv->viu.osd_sc_v_ctrl0 = 0;
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priv->viu.osd_sc_v_phase_step = 0;
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priv->viu.osd_sc_v_ini_phase = 0;
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}
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/* Horizontal scaler is only used if width does not match */
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if (src_w != dst_w) {
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priv->viu.osd_sc_h_ctrl0 =
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HSC_BANK_LENGTH(hf_bank_len) |
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HSC_INI_RCV_NUM0(hsc_ini_rcv_num) |
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HSC_RPT_P0_NUM0(hsc_ini_rpt_p0_num) |
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HSC_HORIZ_SCALER_EN;
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priv->viu.osd_sc_h_phase_step = SC_PHASE_STEP(hf_phase_step);
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2018-11-06 02:40:01 -07:00
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priv->viu.osd_sc_h_ini_phase = 0;
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} else {
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priv->viu.osd_sc_h_ctrl0 = 0;
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2018-11-06 02:40:02 -07:00
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priv->viu.osd_sc_h_phase_step = 0;
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priv->viu.osd_sc_h_ini_phase = 0;
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2018-11-06 02:40:01 -07:00
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}
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2016-11-10 07:29:37 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* The format of these registers is (x2 << 16 | x1),
|
|
|
|
* where x2 is exclusive.
|
|
|
|
* e.g. +30x1920 would be (1919 << 16) | 30
|
|
|
|
*/
|
2018-11-06 02:40:02 -07:00
|
|
|
priv->viu.osd1_blk0_cfg[1] =
|
|
|
|
((fixed16_to_int(state->src.x2) - 1) << 16) |
|
|
|
|
fixed16_to_int(state->src.x1);
|
|
|
|
priv->viu.osd1_blk0_cfg[2] =
|
|
|
|
((fixed16_to_int(state->src.y2) - 1) << 16) |
|
|
|
|
fixed16_to_int(state->src.y1);
|
2016-11-10 07:29:37 -07:00
|
|
|
priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1;
|
|
|
|
priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1;
|
|
|
|
|
|
|
|
/* Update Canvas with buffer address */
|
|
|
|
gem = drm_fb_cma_get_gem_obj(fb, 0);
|
|
|
|
|
2018-02-15 03:19:36 -07:00
|
|
|
priv->viu.osd1_addr = gem->paddr;
|
|
|
|
priv->viu.osd1_stride = fb->pitches[0];
|
|
|
|
priv->viu.osd1_height = fb->height;
|
2016-11-10 07:29:37 -07:00
|
|
|
|
2018-11-28 03:07:34 -07:00
|
|
|
if (!meson_plane->enabled) {
|
|
|
|
/* Reset OSD1 before enabling it on GXL+ SoCs */
|
|
|
|
if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
|
|
|
|
meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
|
|
|
|
meson_viu_osd1_reset(priv);
|
|
|
|
|
|
|
|
meson_plane->enabled = true;
|
|
|
|
}
|
|
|
|
|
2016-11-10 07:29:37 -07:00
|
|
|
spin_unlock_irqrestore(&priv->drm->event_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void meson_plane_atomic_disable(struct drm_plane *plane,
|
|
|
|
struct drm_plane_state *old_state)
|
|
|
|
{
|
|
|
|
struct meson_plane *meson_plane = to_meson_plane(plane);
|
|
|
|
struct meson_drm *priv = meson_plane->priv;
|
|
|
|
|
|
|
|
/* Disable OSD1 */
|
|
|
|
writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0,
|
|
|
|
priv->io_base + _REG(VPP_MISC));
|
|
|
|
|
2018-11-28 03:07:34 -07:00
|
|
|
meson_plane->enabled = false;
|
|
|
|
|
2016-11-10 07:29:37 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct drm_plane_helper_funcs meson_plane_helper_funcs = {
|
|
|
|
.atomic_check = meson_plane_atomic_check,
|
|
|
|
.atomic_disable = meson_plane_atomic_disable,
|
|
|
|
.atomic_update = meson_plane_atomic_update,
|
2018-11-19 03:02:39 -07:00
|
|
|
.prepare_fb = drm_gem_fb_prepare_fb,
|
2016-11-10 07:29:37 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_plane_funcs meson_plane_funcs = {
|
|
|
|
.update_plane = drm_atomic_helper_update_plane,
|
|
|
|
.disable_plane = drm_atomic_helper_disable_plane,
|
|
|
|
.destroy = drm_plane_cleanup,
|
|
|
|
.reset = drm_atomic_helper_plane_reset,
|
|
|
|
.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
|
|
|
|
.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const uint32_t supported_drm_formats[] = {
|
|
|
|
DRM_FORMAT_ARGB8888,
|
|
|
|
DRM_FORMAT_XRGB8888,
|
|
|
|
DRM_FORMAT_RGB888,
|
|
|
|
DRM_FORMAT_RGB565,
|
|
|
|
};
|
|
|
|
|
|
|
|
int meson_plane_create(struct meson_drm *priv)
|
|
|
|
{
|
|
|
|
struct meson_plane *meson_plane;
|
|
|
|
struct drm_plane *plane;
|
|
|
|
|
|
|
|
meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!meson_plane)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
meson_plane->priv = priv;
|
|
|
|
plane = &meson_plane->base;
|
|
|
|
|
|
|
|
drm_universal_plane_init(priv->drm, plane, 0xFF,
|
|
|
|
&meson_plane_funcs,
|
|
|
|
supported_drm_formats,
|
|
|
|
ARRAY_SIZE(supported_drm_formats),
|
2017-07-23 21:46:38 -06:00
|
|
|
NULL,
|
2016-11-10 07:29:37 -07:00
|
|
|
DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane");
|
|
|
|
|
|
|
|
drm_plane_helper_add(plane, &meson_plane_helper_funcs);
|
|
|
|
|
|
|
|
priv->primary_plane = plane;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|