2017-05-27 10:09:35 -06:00
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/*
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* Copyright (C) 2016 Free Electrons
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* Copyright (C) 2016 NextThing Co
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <linux/clk-provider.h>
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#include "sun4i_hdmi.h"
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struct sun4i_tmds {
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struct clk_hw hw;
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struct sun4i_hdmi *hdmi;
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drm/sun4i: hdmi: Add support for controller hardware variants
The HDMI controller found in earlier Allwinner SoCs have slight
differences between the A10, A10s, and the A31:
- Need different initial values for the PLL related registers
- Different behavior of the DDC and TMDS clocks
- Different register layout for the DDC portion
- Separate DDC parent clock on the A31
- Explicit reset control
For the A31, the HDMI TMDS clock has a different value offset for
the divider. The HDMI DDC block is different from the one in the
other SoCs. As far as the DDC clock goes, it has no pre-divider,
as it is clocked from a slower parent clock, not the TMDS clock.
The divider offset from the register value is different. And the
clock control register is at a different offset.
A new variant data structure is created to store pointers to the
above functions, structures, and the different initial values.
Another flag notates whether there is a separate DDC parent clock.
If not, the TMDS clock is passed to the DDC clock create function,
as before.
Regmap fields are used to deal with the different register layout
of the DDC block.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010032008.682-8-wens@csie.org
2017-10-09 21:20:04 -06:00
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u8 div_offset;
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2017-05-27 10:09:35 -06:00
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};
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static inline struct sun4i_tmds *hw_to_tmds(struct clk_hw *hw)
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{
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return container_of(hw, struct sun4i_tmds, hw);
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}
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static unsigned long sun4i_tmds_calc_divider(unsigned long rate,
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unsigned long parent_rate,
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drm/sun4i: hdmi: Add support for controller hardware variants
The HDMI controller found in earlier Allwinner SoCs have slight
differences between the A10, A10s, and the A31:
- Need different initial values for the PLL related registers
- Different behavior of the DDC and TMDS clocks
- Different register layout for the DDC portion
- Separate DDC parent clock on the A31
- Explicit reset control
For the A31, the HDMI TMDS clock has a different value offset for
the divider. The HDMI DDC block is different from the one in the
other SoCs. As far as the DDC clock goes, it has no pre-divider,
as it is clocked from a slower parent clock, not the TMDS clock.
The divider offset from the register value is different. And the
clock control register is at a different offset.
A new variant data structure is created to store pointers to the
above functions, structures, and the different initial values.
Another flag notates whether there is a separate DDC parent clock.
If not, the TMDS clock is passed to the DDC clock create function,
as before.
Regmap fields are used to deal with the different register layout
of the DDC block.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010032008.682-8-wens@csie.org
2017-10-09 21:20:04 -06:00
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u8 div_offset,
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2017-05-27 10:09:35 -06:00
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u8 *div,
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bool *half)
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{
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unsigned long best_rate = 0;
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u8 best_m = 0, m;
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2018-10-21 10:34:45 -06:00
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bool is_double = false;
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2017-05-27 10:09:35 -06:00
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drm/sun4i: hdmi: Add support for controller hardware variants
The HDMI controller found in earlier Allwinner SoCs have slight
differences between the A10, A10s, and the A31:
- Need different initial values for the PLL related registers
- Different behavior of the DDC and TMDS clocks
- Different register layout for the DDC portion
- Separate DDC parent clock on the A31
- Explicit reset control
For the A31, the HDMI TMDS clock has a different value offset for
the divider. The HDMI DDC block is different from the one in the
other SoCs. As far as the DDC clock goes, it has no pre-divider,
as it is clocked from a slower parent clock, not the TMDS clock.
The divider offset from the register value is different. And the
clock control register is at a different offset.
A new variant data structure is created to store pointers to the
above functions, structures, and the different initial values.
Another flag notates whether there is a separate DDC parent clock.
If not, the TMDS clock is passed to the DDC clock create function,
as before.
Regmap fields are used to deal with the different register layout
of the DDC block.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010032008.682-8-wens@csie.org
2017-10-09 21:20:04 -06:00
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for (m = div_offset ?: 1; m < (16 + div_offset); m++) {
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2017-05-27 10:09:35 -06:00
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u8 d;
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for (d = 1; d < 3; d++) {
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unsigned long tmp_rate;
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tmp_rate = parent_rate / m / d;
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if (tmp_rate > rate)
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continue;
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if (!best_rate ||
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(rate - tmp_rate) < (rate - best_rate)) {
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best_rate = tmp_rate;
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best_m = m;
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2018-10-21 10:34:46 -06:00
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is_double = (d == 2) ? true : false;
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2017-05-27 10:09:35 -06:00
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}
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}
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}
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if (div && half) {
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*div = best_m;
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*half = is_double;
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}
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return best_rate;
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}
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static int sun4i_tmds_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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drm/sun4i: hdmi: Add support for controller hardware variants
The HDMI controller found in earlier Allwinner SoCs have slight
differences between the A10, A10s, and the A31:
- Need different initial values for the PLL related registers
- Different behavior of the DDC and TMDS clocks
- Different register layout for the DDC portion
- Separate DDC parent clock on the A31
- Explicit reset control
For the A31, the HDMI TMDS clock has a different value offset for
the divider. The HDMI DDC block is different from the one in the
other SoCs. As far as the DDC clock goes, it has no pre-divider,
as it is clocked from a slower parent clock, not the TMDS clock.
The divider offset from the register value is different. And the
clock control register is at a different offset.
A new variant data structure is created to store pointers to the
above functions, structures, and the different initial values.
Another flag notates whether there is a separate DDC parent clock.
If not, the TMDS clock is passed to the DDC clock create function,
as before.
Regmap fields are used to deal with the different register layout
of the DDC block.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010032008.682-8-wens@csie.org
2017-10-09 21:20:04 -06:00
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struct sun4i_tmds *tmds = hw_to_tmds(hw);
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2017-10-09 21:20:02 -06:00
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struct clk_hw *parent = NULL;
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2017-05-27 10:09:35 -06:00
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unsigned long best_parent = 0;
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unsigned long rate = req->rate;
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int best_div = 1, best_half = 1;
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2017-10-09 21:20:02 -06:00
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int i, j, p;
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2017-05-27 10:09:35 -06:00
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/*
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* We only consider PLL3, since the TCON is very likely to be
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* clocked from it, and to have the same rate than our HDMI
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* clock, so we should not need to do anything.
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*/
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2017-10-09 21:20:02 -06:00
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for (p = 0; p < clk_hw_get_num_parents(hw); p++) {
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parent = clk_hw_get_parent_by_index(hw, p);
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if (!parent)
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continue;
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for (i = 1; i < 3; i++) {
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drm/sun4i: hdmi: Add support for controller hardware variants
The HDMI controller found in earlier Allwinner SoCs have slight
differences between the A10, A10s, and the A31:
- Need different initial values for the PLL related registers
- Different behavior of the DDC and TMDS clocks
- Different register layout for the DDC portion
- Separate DDC parent clock on the A31
- Explicit reset control
For the A31, the HDMI TMDS clock has a different value offset for
the divider. The HDMI DDC block is different from the one in the
other SoCs. As far as the DDC clock goes, it has no pre-divider,
as it is clocked from a slower parent clock, not the TMDS clock.
The divider offset from the register value is different. And the
clock control register is at a different offset.
A new variant data structure is created to store pointers to the
above functions, structures, and the different initial values.
Another flag notates whether there is a separate DDC parent clock.
If not, the TMDS clock is passed to the DDC clock create function,
as before.
Regmap fields are used to deal with the different register layout
of the DDC block.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010032008.682-8-wens@csie.org
2017-10-09 21:20:04 -06:00
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for (j = tmds->div_offset ?: 1;
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j < (16 + tmds->div_offset); j++) {
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2017-10-09 21:20:02 -06:00
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unsigned long ideal = rate * i * j;
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unsigned long rounded;
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rounded = clk_hw_round_rate(parent, ideal);
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if (rounded == ideal) {
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best_parent = rounded;
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best_half = i;
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best_div = j;
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goto out;
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}
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2018-01-08 19:03:23 -07:00
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if (!best_parent ||
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abs(rate - rounded / i / j) <
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abs(rate - best_parent / best_half /
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best_div)) {
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2017-10-09 21:20:02 -06:00
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best_parent = rounded;
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2018-01-08 19:03:23 -07:00
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best_half = i;
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2018-01-08 19:03:22 -07:00
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best_div = j;
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2017-10-09 21:20:02 -06:00
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}
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2017-05-27 10:09:35 -06:00
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}
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}
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}
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2017-10-09 21:20:02 -06:00
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if (!parent)
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return -EINVAL;
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2017-05-27 10:09:35 -06:00
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out:
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req->rate = best_parent / best_half / best_div;
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req->best_parent_rate = best_parent;
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req->best_parent_hw = parent;
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return 0;
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}
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static unsigned long sun4i_tmds_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct sun4i_tmds *tmds = hw_to_tmds(hw);
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u32 reg;
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reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
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if (reg & SUN4I_HDMI_PAD_CTRL1_HALVE_CLK)
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parent_rate /= 2;
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reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
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drm/sun4i: hdmi: Add support for controller hardware variants
The HDMI controller found in earlier Allwinner SoCs have slight
differences between the A10, A10s, and the A31:
- Need different initial values for the PLL related registers
- Different behavior of the DDC and TMDS clocks
- Different register layout for the DDC portion
- Separate DDC parent clock on the A31
- Explicit reset control
For the A31, the HDMI TMDS clock has a different value offset for
the divider. The HDMI DDC block is different from the one in the
other SoCs. As far as the DDC clock goes, it has no pre-divider,
as it is clocked from a slower parent clock, not the TMDS clock.
The divider offset from the register value is different. And the
clock control register is at a different offset.
A new variant data structure is created to store pointers to the
above functions, structures, and the different initial values.
Another flag notates whether there is a separate DDC parent clock.
If not, the TMDS clock is passed to the DDC clock create function,
as before.
Regmap fields are used to deal with the different register layout
of the DDC block.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010032008.682-8-wens@csie.org
2017-10-09 21:20:04 -06:00
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reg = ((reg >> 4) & 0xf) + tmds->div_offset;
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2017-05-27 10:09:35 -06:00
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if (!reg)
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reg = 1;
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return parent_rate / reg;
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}
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static int sun4i_tmds_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct sun4i_tmds *tmds = hw_to_tmds(hw);
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bool half;
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u32 reg;
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u8 div;
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drm/sun4i: hdmi: Add support for controller hardware variants
The HDMI controller found in earlier Allwinner SoCs have slight
differences between the A10, A10s, and the A31:
- Need different initial values for the PLL related registers
- Different behavior of the DDC and TMDS clocks
- Different register layout for the DDC portion
- Separate DDC parent clock on the A31
- Explicit reset control
For the A31, the HDMI TMDS clock has a different value offset for
the divider. The HDMI DDC block is different from the one in the
other SoCs. As far as the DDC clock goes, it has no pre-divider,
as it is clocked from a slower parent clock, not the TMDS clock.
The divider offset from the register value is different. And the
clock control register is at a different offset.
A new variant data structure is created to store pointers to the
above functions, structures, and the different initial values.
Another flag notates whether there is a separate DDC parent clock.
If not, the TMDS clock is passed to the DDC clock create function,
as before.
Regmap fields are used to deal with the different register layout
of the DDC block.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010032008.682-8-wens@csie.org
2017-10-09 21:20:04 -06:00
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sun4i_tmds_calc_divider(rate, parent_rate, tmds->div_offset,
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&div, &half);
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2017-05-27 10:09:35 -06:00
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reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
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reg &= ~SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
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if (half)
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reg |= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
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writel(reg, tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
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reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
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reg &= ~SUN4I_HDMI_PLL_CTRL_DIV_MASK;
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drm/sun4i: hdmi: Add support for controller hardware variants
The HDMI controller found in earlier Allwinner SoCs have slight
differences between the A10, A10s, and the A31:
- Need different initial values for the PLL related registers
- Different behavior of the DDC and TMDS clocks
- Different register layout for the DDC portion
- Separate DDC parent clock on the A31
- Explicit reset control
For the A31, the HDMI TMDS clock has a different value offset for
the divider. The HDMI DDC block is different from the one in the
other SoCs. As far as the DDC clock goes, it has no pre-divider,
as it is clocked from a slower parent clock, not the TMDS clock.
The divider offset from the register value is different. And the
clock control register is at a different offset.
A new variant data structure is created to store pointers to the
above functions, structures, and the different initial values.
Another flag notates whether there is a separate DDC parent clock.
If not, the TMDS clock is passed to the DDC clock create function,
as before.
Regmap fields are used to deal with the different register layout
of the DDC block.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010032008.682-8-wens@csie.org
2017-10-09 21:20:04 -06:00
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writel(reg | SUN4I_HDMI_PLL_CTRL_DIV(div - tmds->div_offset),
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2017-05-27 10:09:35 -06:00
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tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
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return 0;
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}
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static u8 sun4i_tmds_get_parent(struct clk_hw *hw)
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{
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struct sun4i_tmds *tmds = hw_to_tmds(hw);
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u32 reg;
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reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_DBG0_REG);
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return ((reg & SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK) >>
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SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_SHIFT);
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}
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static int sun4i_tmds_set_parent(struct clk_hw *hw, u8 index)
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{
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struct sun4i_tmds *tmds = hw_to_tmds(hw);
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u32 reg;
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if (index > 1)
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return -EINVAL;
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reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_DBG0_REG);
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reg &= ~SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK;
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writel(reg | SUN4I_HDMI_PLL_DBG0_TMDS_PARENT(index),
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tmds->hdmi->base + SUN4I_HDMI_PLL_DBG0_REG);
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return 0;
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}
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static const struct clk_ops sun4i_tmds_ops = {
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.determine_rate = sun4i_tmds_determine_rate,
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.recalc_rate = sun4i_tmds_recalc_rate,
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.set_rate = sun4i_tmds_set_rate,
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.get_parent = sun4i_tmds_get_parent,
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.set_parent = sun4i_tmds_set_parent,
|
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};
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int sun4i_tmds_create(struct sun4i_hdmi *hdmi)
|
|
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|
{
|
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struct clk_init_data init;
|
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|
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struct sun4i_tmds *tmds;
|
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const char *parents[2];
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parents[0] = __clk_get_name(hdmi->pll0_clk);
|
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|
|
if (!parents[0])
|
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|
|
return -ENODEV;
|
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parents[1] = __clk_get_name(hdmi->pll1_clk);
|
|
|
|
if (!parents[1])
|
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|
|
return -ENODEV;
|
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|
|
tmds = devm_kzalloc(hdmi->dev, sizeof(*tmds), GFP_KERNEL);
|
|
|
|
if (!tmds)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
init.name = "hdmi-tmds";
|
|
|
|
init.ops = &sun4i_tmds_ops;
|
|
|
|
init.parent_names = parents;
|
|
|
|
init.num_parents = 2;
|
|
|
|
init.flags = CLK_SET_RATE_PARENT;
|
|
|
|
|
|
|
|
tmds->hdmi = hdmi;
|
|
|
|
tmds->hw.init = &init;
|
drm/sun4i: hdmi: Add support for controller hardware variants
The HDMI controller found in earlier Allwinner SoCs have slight
differences between the A10, A10s, and the A31:
- Need different initial values for the PLL related registers
- Different behavior of the DDC and TMDS clocks
- Different register layout for the DDC portion
- Separate DDC parent clock on the A31
- Explicit reset control
For the A31, the HDMI TMDS clock has a different value offset for
the divider. The HDMI DDC block is different from the one in the
other SoCs. As far as the DDC clock goes, it has no pre-divider,
as it is clocked from a slower parent clock, not the TMDS clock.
The divider offset from the register value is different. And the
clock control register is at a different offset.
A new variant data structure is created to store pointers to the
above functions, structures, and the different initial values.
Another flag notates whether there is a separate DDC parent clock.
If not, the TMDS clock is passed to the DDC clock create function,
as before.
Regmap fields are used to deal with the different register layout
of the DDC block.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171010032008.682-8-wens@csie.org
2017-10-09 21:20:04 -06:00
|
|
|
tmds->div_offset = hdmi->variant->tmds_clk_div_offset;
|
2017-05-27 10:09:35 -06:00
|
|
|
|
|
|
|
hdmi->tmds_clk = devm_clk_register(hdmi->dev, &tmds->hw);
|
|
|
|
if (IS_ERR(hdmi->tmds_clk))
|
|
|
|
return PTR_ERR(hdmi->tmds_clk);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|