2008-10-08 06:00:58 -06:00
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/*
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* linux/arch/arm/mach-omap2/cpuidle34xx.c
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*
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* OMAP3 CPU IDLE Routines
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*
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* Copyright (C) 2008 Texas Instruments, Inc.
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* Rajendra Nayak <rnayak@ti.com>
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Karthik Dasu <karthik-dp@ti.com>
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*
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* Copyright (C) 2006 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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*
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* Copyright (C) 2005 Texas Instruments, Inc.
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* Based on pm.c for omap2
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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2009-03-20 07:21:02 -06:00
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#include <linux/sched.h>
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2008-10-08 06:00:58 -06:00
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#include <linux/cpuidle.h>
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#include <plat/prcm.h>
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2008-10-08 06:01:22 -06:00
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#include <plat/irqs.h>
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2010-12-21 21:05:16 -07:00
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#include "powerdomain.h"
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2010-12-21 21:05:15 -07:00
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#include "clockdomain.h"
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2008-10-28 18:32:11 -06:00
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#include <plat/serial.h>
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2008-10-08 06:00:58 -06:00
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2008-10-28 18:30:07 -06:00
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#include "pm.h"
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2010-10-08 11:40:20 -06:00
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#include "control.h"
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2008-10-28 18:30:07 -06:00
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2008-10-08 06:00:58 -06:00
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#ifdef CONFIG_CPU_IDLE
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2009-03-13 10:04:25 -06:00
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#define OMAP3_MAX_STATES 7
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#define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */
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#define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */
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#define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */
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#define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */
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#define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */
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#define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */
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#define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */
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2008-10-08 06:00:58 -06:00
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2010-01-28 10:46:43 -07:00
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#define OMAP3_STATE_MAX OMAP3_STATE_C7
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2011-01-12 00:56:15 -07:00
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#define CPUIDLE_FLAG_CHECK_BM 0x10000 /* use omap3_enter_idle_bm() */
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2008-10-08 06:00:58 -06:00
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struct omap3_processor_cx {
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u8 valid;
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u8 type;
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2011-05-09 04:02:13 -06:00
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u32 exit_latency;
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2008-10-08 06:00:58 -06:00
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u32 mpu_state;
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u32 core_state;
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2011-05-09 04:02:13 -06:00
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u32 target_residency;
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2008-10-08 06:00:58 -06:00
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u32 flags;
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2011-02-11 08:12:12 -07:00
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const char *desc;
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2008-10-08 06:00:58 -06:00
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};
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struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
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struct omap3_processor_cx current_cx_state;
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2010-09-08 17:37:42 -06:00
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struct powerdomain *mpu_pd, *core_pd, *per_pd;
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struct powerdomain *cam_pd;
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2008-10-08 06:00:58 -06:00
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2009-12-15 17:37:18 -07:00
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/*
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* The latencies/thresholds for various C states have
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* to be configured from the respective board files.
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* These are some default values (which might not provide
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* the best power savings) used on boards which do not
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* pass these details from the board file.
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*/
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static struct cpuidle_params cpuidle_params_table[] = {
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/* C1 */
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2011-05-09 04:02:13 -06:00
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{2 + 2, 5, 1},
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2009-12-15 17:37:18 -07:00
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/* C2 */
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2011-05-09 04:02:13 -06:00
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{10 + 10, 30, 1},
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2009-12-15 17:37:18 -07:00
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/* C3 */
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2011-05-09 04:02:13 -06:00
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{50 + 50, 300, 1},
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2009-12-15 17:37:18 -07:00
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/* C4 */
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2011-05-09 04:02:13 -06:00
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{1500 + 1800, 4000, 1},
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2009-12-15 17:37:18 -07:00
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/* C5 */
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2011-05-09 04:02:13 -06:00
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{2500 + 7500, 12000, 1},
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2009-12-15 17:37:18 -07:00
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/* C6 */
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2011-05-09 04:02:13 -06:00
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{3000 + 8500, 15000, 1},
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2009-12-15 17:37:18 -07:00
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/* C7 */
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2011-05-09 04:02:13 -06:00
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{10000 + 30000, 300000, 1},
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2009-12-15 17:37:18 -07:00
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};
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2008-10-08 06:00:58 -06:00
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static int omap3_idle_bm_check(void)
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{
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2008-10-08 06:01:22 -06:00
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if (!omap3_can_sleep())
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return 1;
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2008-10-08 06:00:58 -06:00
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return 0;
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}
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2009-03-13 10:19:16 -06:00
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static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
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struct clockdomain *clkdm)
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{
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2011-02-25 16:06:48 -07:00
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clkdm_allow_idle(clkdm);
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2009-03-13 10:19:16 -06:00
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return 0;
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}
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static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
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struct clockdomain *clkdm)
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{
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2011-02-25 16:06:48 -07:00
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clkdm_deny_idle(clkdm);
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2009-03-13 10:19:16 -06:00
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return 0;
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}
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2008-10-08 06:00:58 -06:00
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/**
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* omap3_enter_idle - Programs OMAP3 to enter the specified state
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* @dev: cpuidle device
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* @state: The target state to be programmed
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*
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* Called from the CPUidle framework to program the device to the
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* specified target state selected by the governor.
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*/
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static int omap3_enter_idle(struct cpuidle_device *dev,
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struct cpuidle_state *state)
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{
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struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
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struct timespec ts_preidle, ts_postidle, ts_idle;
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2008-10-28 18:30:07 -06:00
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u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
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2008-10-08 06:00:58 -06:00
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current_cx_state = *cx;
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/* Used to keep track of the total time in idle */
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getnstimeofday(&ts_preidle);
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local_irq_disable();
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local_fiq_disable();
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2008-10-28 02:59:05 -06:00
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pwrdm_set_next_pwrst(mpu_pd, mpu_state);
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pwrdm_set_next_pwrst(core_pd, core_state);
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2008-10-08 06:01:22 -06:00
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2009-03-20 07:21:02 -06:00
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if (omap_irq_pending() || need_resched())
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2008-10-08 06:01:22 -06:00
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goto return_sleep_time;
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2008-10-08 06:00:58 -06:00
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2009-03-13 10:19:16 -06:00
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if (cx->type == OMAP3_STATE_C1) {
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pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
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pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
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}
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2008-10-08 06:00:58 -06:00
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/* Execute ARM wfi */
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omap_sram_idle();
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2009-03-13 10:19:16 -06:00
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if (cx->type == OMAP3_STATE_C1) {
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pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
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pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
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}
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2008-10-08 06:01:22 -06:00
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return_sleep_time:
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2008-10-08 06:00:58 -06:00
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getnstimeofday(&ts_postidle);
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ts_idle = timespec_sub(ts_postidle, ts_preidle);
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local_irq_enable();
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local_fiq_enable();
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2009-10-26 07:10:40 -06:00
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return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
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2008-10-08 06:00:58 -06:00
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}
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2010-01-28 10:46:43 -07:00
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/**
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* next_valid_state - Find next valid c-state
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* @dev: cpuidle device
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* @state: Currently selected c-state
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*
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* If the current state is valid, it is returned back to the caller.
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* Else, this function searches for a lower c-state which is still
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* valid (as defined in omap3_power_states[]).
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*/
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static struct cpuidle_state *next_valid_state(struct cpuidle_device *dev,
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struct cpuidle_state *curr)
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{
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struct cpuidle_state *next = NULL;
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struct omap3_processor_cx *cx;
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cx = (struct omap3_processor_cx *)cpuidle_get_statedata(curr);
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/* Check if current state is valid */
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if (cx->valid) {
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return curr;
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} else {
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u8 idx = OMAP3_STATE_MAX;
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/*
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* Reach the current state starting at highest C-state
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*/
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for (; idx >= OMAP3_STATE_C1; idx--) {
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if (&dev->states[idx] == curr) {
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next = &dev->states[idx];
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break;
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}
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}
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/*
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* Should never hit this condition.
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*/
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WARN_ON(next == NULL);
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/*
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* Drop to next valid state.
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* Start search from the next (lower) state.
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*/
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idx--;
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for (; idx >= OMAP3_STATE_C1; idx--) {
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struct omap3_processor_cx *cx;
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cx = cpuidle_get_statedata(&dev->states[idx]);
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if (cx->valid) {
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next = &dev->states[idx];
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break;
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}
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}
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/*
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* C1 and C2 are always valid.
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* So, no need to check for 'next==NULL' outside this loop.
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*/
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}
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return next;
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}
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2008-10-08 06:00:58 -06:00
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/**
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* omap3_enter_idle_bm - Checks for any bus activity
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* @dev: cpuidle device
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* @state: The target state to be programmed
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*
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* Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This
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* function checks for any pending activity and then programs the
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* device to the specified or a safer state.
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*/
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static int omap3_enter_idle_bm(struct cpuidle_device *dev,
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struct cpuidle_state *state)
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{
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2010-01-28 10:46:43 -07:00
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struct cpuidle_state *new_state = next_valid_state(dev, state);
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2010-09-08 17:37:42 -06:00
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u32 core_next_state, per_next_state = 0, per_saved_state = 0;
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u32 cam_state;
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struct omap3_processor_cx *cx;
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int ret;
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2008-10-28 18:32:11 -06:00
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2008-10-08 06:00:58 -06:00
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if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
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2008-10-28 18:32:11 -06:00
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BUG_ON(!dev->safe_state);
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new_state = dev->safe_state;
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2010-09-08 17:37:42 -06:00
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goto select_state;
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}
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cx = cpuidle_get_statedata(state);
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core_next_state = cx->core_state;
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/*
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* FIXME: we currently manage device-specific idle states
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* for PER and CORE in combination with CPU-specific
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* idle states. This is wrong, and device-specific
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tree-wide: fix comment/printk typos
"gadget", "through", "command", "maintain", "maintain", "controller", "address",
"between", "initiali[zs]e", "instead", "function", "select", "already",
"equal", "access", "management", "hierarchy", "registration", "interest",
"relative", "memory", "offset", "already",
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2010-11-01 13:38:34 -06:00
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* idle management needs to be separated out into
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2010-09-08 17:37:42 -06:00
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* its own code.
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*/
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/*
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* Prevent idle completely if CAM is active.
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* CAM does not have wakeup capability in OMAP3.
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*/
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cam_state = pwrdm_read_pwrst(cam_pd);
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if (cam_state == PWRDM_POWER_ON) {
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new_state = dev->safe_state;
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goto select_state;
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}
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/*
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* Prevent PER off if CORE is not in retention or off as this
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* would disable PER wakeups completely.
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*/
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per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
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if ((per_next_state == PWRDM_POWER_OFF) &&
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2010-10-01 09:35:47 -06:00
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(core_next_state > PWRDM_POWER_RET))
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2010-09-08 17:37:42 -06:00
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per_next_state = PWRDM_POWER_RET;
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2008-10-28 18:32:11 -06:00
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2010-09-08 17:37:42 -06:00
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/* Are we changing PER target state? */
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if (per_next_state != per_saved_state)
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pwrdm_set_next_pwrst(per_pd, per_next_state);
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select_state:
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2008-10-28 18:32:11 -06:00
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dev->last_state = new_state;
|
2010-09-08 17:37:42 -06:00
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ret = omap3_enter_idle(dev, new_state);
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/* Restore original PER state if it was modified */
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if (per_next_state != per_saved_state)
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pwrdm_set_next_pwrst(per_pd, per_saved_state);
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return ret;
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2008-10-08 06:00:58 -06:00
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}
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DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
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|
2010-01-28 10:46:43 -07:00
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/**
|
2010-12-20 13:05:08 -07:00
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* omap3_cpuidle_update_states() - Update the cpuidle states
|
2011-03-30 19:57:33 -06:00
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* @mpu_deepest_state: Enable states up to and including this for mpu domain
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* @core_deepest_state: Enable states up to and including this for core domain
|
2010-01-28 10:46:43 -07:00
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*
|
2010-12-20 13:05:08 -07:00
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* This goes through the list of states available and enables and disables the
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|
|
* validity of C states based on deepest state that can be achieved for the
|
|
|
|
* variable domain
|
2010-01-28 10:46:43 -07:00
|
|
|
*/
|
2010-12-20 13:05:08 -07:00
|
|
|
void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state)
|
2010-01-28 10:46:43 -07:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
|
|
|
|
struct omap3_processor_cx *cx = &omap3_power_states[i];
|
|
|
|
|
2010-12-20 13:05:08 -07:00
|
|
|
if ((cx->mpu_state >= mpu_deepest_state) &&
|
|
|
|
(cx->core_state >= core_deepest_state)) {
|
2010-01-28 10:46:43 -07:00
|
|
|
cx->valid = 1;
|
|
|
|
} else {
|
2010-12-20 13:05:08 -07:00
|
|
|
cx->valid = 0;
|
2010-01-28 10:46:43 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-12-15 17:37:18 -07:00
|
|
|
void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (!cpuidle_board_params)
|
|
|
|
return;
|
|
|
|
|
|
|
|
for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
|
2009-10-29 02:30:19 -06:00
|
|
|
cpuidle_params_table[i].valid =
|
|
|
|
cpuidle_board_params[i].valid;
|
2011-05-09 04:02:13 -06:00
|
|
|
cpuidle_params_table[i].exit_latency =
|
|
|
|
cpuidle_board_params[i].exit_latency;
|
|
|
|
cpuidle_params_table[i].target_residency =
|
|
|
|
cpuidle_board_params[i].target_residency;
|
2009-12-15 17:37:18 -07:00
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2008-10-08 06:00:58 -06:00
|
|
|
/* omap3_init_power_states - Initialises the OMAP3 specific C states.
|
|
|
|
*
|
|
|
|
* Below is the desciption of each C state.
|
2009-03-13 10:19:16 -06:00
|
|
|
* C1 . MPU WFI + Core active
|
|
|
|
* C2 . MPU WFI + Core inactive
|
|
|
|
* C3 . MPU CSWR + Core inactive
|
|
|
|
* C4 . MPU OFF + Core inactive
|
|
|
|
* C5 . MPU CSWR + Core CSWR
|
|
|
|
* C6 . MPU OFF + Core CSWR
|
|
|
|
* C7 . MPU OFF + Core OFF
|
2008-10-08 06:00:58 -06:00
|
|
|
*/
|
|
|
|
void omap_init_power_states(void)
|
|
|
|
{
|
|
|
|
/* C1 . MPU WFI + Core active */
|
2009-10-29 02:30:19 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C1].valid =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C1].valid;
|
2008-10-08 06:00:58 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
|
2011-05-09 04:02:13 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C1].exit_latency =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C1].exit_latency;
|
|
|
|
omap3_power_states[OMAP3_STATE_C1].target_residency =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C1].target_residency;
|
2008-10-08 06:00:58 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
|
|
|
|
omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
|
|
|
|
omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
|
2011-02-11 08:12:12 -07:00
|
|
|
omap3_power_states[OMAP3_STATE_C1].desc = "MPU ON + CORE ON";
|
2008-10-08 06:00:58 -06:00
|
|
|
|
2009-03-13 10:19:16 -06:00
|
|
|
/* C2 . MPU WFI + Core inactive */
|
2009-10-29 02:30:19 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C2].valid =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C2].valid;
|
2008-10-08 06:00:58 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
|
2011-05-09 04:02:13 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C2].exit_latency =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C2].exit_latency;
|
|
|
|
omap3_power_states[OMAP3_STATE_C2].target_residency =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C2].target_residency;
|
2009-03-13 10:19:16 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
|
2008-10-08 06:00:58 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
|
2010-09-08 17:37:42 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID |
|
|
|
|
CPUIDLE_FLAG_CHECK_BM;
|
2011-02-11 08:12:12 -07:00
|
|
|
omap3_power_states[OMAP3_STATE_C2].desc = "MPU ON + CORE ON";
|
2008-10-08 06:00:58 -06:00
|
|
|
|
2009-03-13 10:19:16 -06:00
|
|
|
/* C3 . MPU CSWR + Core inactive */
|
2009-10-29 02:30:19 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C3].valid =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C3].valid;
|
2008-10-08 06:00:58 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
|
2011-05-09 04:02:13 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C3].exit_latency =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C3].exit_latency;
|
|
|
|
omap3_power_states[OMAP3_STATE_C3].target_residency =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C3].target_residency;
|
2009-03-13 10:19:16 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET;
|
2008-10-08 06:00:58 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
|
2008-10-28 18:32:11 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
|
|
|
|
CPUIDLE_FLAG_CHECK_BM;
|
2011-02-11 08:12:12 -07:00
|
|
|
omap3_power_states[OMAP3_STATE_C3].desc = "MPU RET + CORE ON";
|
2008-10-08 06:00:58 -06:00
|
|
|
|
2009-03-13 10:19:16 -06:00
|
|
|
/* C4 . MPU OFF + Core inactive */
|
2009-10-29 02:30:19 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C4].valid =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C4].valid;
|
2008-10-08 06:00:58 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
|
2011-05-09 04:02:13 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C4].exit_latency =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C4].exit_latency;
|
|
|
|
omap3_power_states[OMAP3_STATE_C4].target_residency =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C4].target_residency;
|
2009-03-13 10:19:16 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF;
|
|
|
|
omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
|
2008-10-08 06:00:58 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
|
|
|
|
CPUIDLE_FLAG_CHECK_BM;
|
2011-02-11 08:12:12 -07:00
|
|
|
omap3_power_states[OMAP3_STATE_C4].desc = "MPU OFF + CORE ON";
|
2008-10-08 06:00:58 -06:00
|
|
|
|
2009-03-13 10:19:16 -06:00
|
|
|
/* C5 . MPU CSWR + Core CSWR*/
|
2009-10-29 02:30:19 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C5].valid =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C5].valid;
|
2008-10-08 06:00:58 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
|
2011-05-09 04:02:13 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C5].exit_latency =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C5].exit_latency;
|
|
|
|
omap3_power_states[OMAP3_STATE_C5].target_residency =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C5].target_residency;
|
2009-03-13 10:19:16 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET;
|
2008-10-08 06:00:58 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
|
|
|
|
omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
|
|
|
|
CPUIDLE_FLAG_CHECK_BM;
|
2011-02-11 08:12:12 -07:00
|
|
|
omap3_power_states[OMAP3_STATE_C5].desc = "MPU RET + CORE RET";
|
2008-10-08 06:00:58 -06:00
|
|
|
|
2009-03-13 10:19:16 -06:00
|
|
|
/* C6 . MPU OFF + Core CSWR */
|
2009-10-29 02:30:19 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C6].valid =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C6].valid;
|
2008-10-08 06:00:58 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
|
2011-05-09 04:02:13 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C6].exit_latency =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C6].exit_latency;
|
|
|
|
omap3_power_states[OMAP3_STATE_C6].target_residency =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C6].target_residency;
|
2008-10-08 06:00:58 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
|
2009-03-13 10:19:16 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
|
2008-10-08 06:00:58 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
|
|
|
|
CPUIDLE_FLAG_CHECK_BM;
|
2011-02-11 08:12:12 -07:00
|
|
|
omap3_power_states[OMAP3_STATE_C6].desc = "MPU OFF + CORE RET";
|
2009-03-13 10:19:16 -06:00
|
|
|
|
|
|
|
/* C7 . MPU OFF + Core OFF */
|
2009-10-29 02:30:19 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C7].valid =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C7].valid;
|
2009-03-13 10:19:16 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
|
2011-05-09 04:02:13 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C7].exit_latency =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C7].exit_latency;
|
|
|
|
omap3_power_states[OMAP3_STATE_C7].target_residency =
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C7].target_residency;
|
2009-03-13 10:19:16 -06:00
|
|
|
omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF;
|
|
|
|
omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
|
|
|
|
omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
|
|
|
|
CPUIDLE_FLAG_CHECK_BM;
|
2011-02-11 08:12:12 -07:00
|
|
|
omap3_power_states[OMAP3_STATE_C7].desc = "MPU OFF + CORE OFF";
|
2010-12-20 13:05:09 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
|
|
|
|
* enable OFF mode in a stable form for previous revisions.
|
|
|
|
* we disable C7 state as a result.
|
|
|
|
*/
|
|
|
|
if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
|
|
|
|
omap3_power_states[OMAP3_STATE_C7].valid = 0;
|
|
|
|
cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
|
2011-01-31 06:35:25 -07:00
|
|
|
pr_warn("%s: core off state C7 disabled due to i583\n",
|
2010-12-20 13:05:09 -07:00
|
|
|
__func__);
|
|
|
|
}
|
2008-10-08 06:00:58 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
struct cpuidle_driver omap3_idle_driver = {
|
|
|
|
.name = "omap3_idle",
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* omap3_idle_init - Init routine for OMAP3 idle
|
|
|
|
*
|
|
|
|
* Registers the OMAP3 specific cpuidle driver with the cpuidle
|
|
|
|
* framework with the valid set of states.
|
|
|
|
*/
|
2008-09-26 02:04:20 -06:00
|
|
|
int __init omap3_idle_init(void)
|
2008-10-08 06:00:58 -06:00
|
|
|
{
|
|
|
|
int i, count = 0;
|
|
|
|
struct omap3_processor_cx *cx;
|
|
|
|
struct cpuidle_state *state;
|
|
|
|
struct cpuidle_device *dev;
|
|
|
|
|
|
|
|
mpu_pd = pwrdm_lookup("mpu_pwrdm");
|
2008-10-08 06:01:22 -06:00
|
|
|
core_pd = pwrdm_lookup("core_pwrdm");
|
2010-09-08 17:37:42 -06:00
|
|
|
per_pd = pwrdm_lookup("per_pwrdm");
|
|
|
|
cam_pd = pwrdm_lookup("cam_pwrdm");
|
2008-10-08 06:00:58 -06:00
|
|
|
|
|
|
|
omap_init_power_states();
|
|
|
|
cpuidle_register_driver(&omap3_idle_driver);
|
|
|
|
|
|
|
|
dev = &per_cpu(omap3_idle_dev, smp_processor_id());
|
|
|
|
|
2009-03-13 10:04:25 -06:00
|
|
|
for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
|
2008-10-08 06:00:58 -06:00
|
|
|
cx = &omap3_power_states[i];
|
|
|
|
state = &dev->states[count];
|
|
|
|
|
|
|
|
if (!cx->valid)
|
|
|
|
continue;
|
|
|
|
cpuidle_set_statedata(state, cx);
|
2011-05-09 04:02:13 -06:00
|
|
|
state->exit_latency = cx->exit_latency;
|
|
|
|
state->target_residency = cx->target_residency;
|
2008-10-08 06:00:58 -06:00
|
|
|
state->flags = cx->flags;
|
|
|
|
state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
|
|
|
|
omap3_enter_idle_bm : omap3_enter_idle;
|
|
|
|
if (cx->type == OMAP3_STATE_C1)
|
|
|
|
dev->safe_state = state;
|
|
|
|
sprintf(state->name, "C%d", count+1);
|
2011-02-11 08:12:12 -07:00
|
|
|
strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
|
2008-10-08 06:00:58 -06:00
|
|
|
count++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!count)
|
|
|
|
return -EINVAL;
|
|
|
|
dev->state_count = count;
|
|
|
|
|
2010-12-20 13:05:08 -07:00
|
|
|
if (enable_off_mode)
|
|
|
|
omap3_cpuidle_update_states(PWRDM_POWER_OFF, PWRDM_POWER_OFF);
|
|
|
|
else
|
|
|
|
omap3_cpuidle_update_states(PWRDM_POWER_RET, PWRDM_POWER_RET);
|
2010-01-28 10:46:43 -07:00
|
|
|
|
2008-10-08 06:00:58 -06:00
|
|
|
if (cpuidle_register_device(dev)) {
|
|
|
|
printk(KERN_ERR "%s: CPUidle register device failed\n",
|
|
|
|
__func__);
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2008-09-26 02:04:20 -06:00
|
|
|
#else
|
|
|
|
int __init omap3_idle_init(void)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
2008-10-08 06:00:58 -06:00
|
|
|
#endif /* CONFIG_CPU_IDLE */
|