2008-10-22 23:26:29 -06:00
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#ifndef _ASM_X86_CMPXCHG_32_H
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#define _ASM_X86_CMPXCHG_32_H
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2007-05-08 01:35:02 -06:00
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#include <linux/bitops.h> /* for LOCK_PREFIX */
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2007-07-19 05:30:14 -06:00
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/*
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* Note: if you use set64_bit(), __cmpxchg64(), or their variants, you
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* you need to test for the feature in boot_cpu_data.
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*/
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2009-10-09 02:12:46 -06:00
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extern void __xchg_wrong_size(void);
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/*
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2010-07-28 16:18:35 -06:00
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* Note: no "lock" prefix even on SMP: xchg always implies lock anyway.
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* Since this is generally used to protect other memory information, we
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* use "asm volatile" and "memory" clobbers to prevent gcc from moving
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* information around.
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2009-10-09 02:12:46 -06:00
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*/
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#define __xchg(x, ptr, size) \
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({ \
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__typeof(*(ptr)) __x = (x); \
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switch (size) { \
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case 1: \
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2010-07-28 16:18:35 -06:00
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{ \
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volatile u8 *__ptr = (volatile u8 *)(ptr); \
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asm volatile("xchgb %0,%1" \
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: "=q" (__x), "+m" (*__ptr) \
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2010-07-27 18:01:49 -06:00
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: "0" (__x) \
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2009-10-09 02:12:46 -06:00
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: "memory"); \
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break; \
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2010-07-28 16:18:35 -06:00
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} \
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2009-10-09 02:12:46 -06:00
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case 2: \
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2010-07-28 16:18:35 -06:00
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{ \
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volatile u16 *__ptr = (volatile u16 *)(ptr); \
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asm volatile("xchgw %0,%1" \
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: "=r" (__x), "+m" (*__ptr) \
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2010-07-27 18:01:49 -06:00
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: "0" (__x) \
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2009-10-09 02:12:46 -06:00
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: "memory"); \
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break; \
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2010-07-28 16:18:35 -06:00
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} \
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2009-10-09 02:12:46 -06:00
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case 4: \
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2010-07-28 16:18:35 -06:00
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{ \
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volatile u32 *__ptr = (volatile u32 *)(ptr); \
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2009-10-09 02:12:46 -06:00
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asm volatile("xchgl %0,%1" \
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2010-07-28 16:18:35 -06:00
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: "=r" (__x), "+m" (*__ptr) \
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2010-07-27 18:01:49 -06:00
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: "0" (__x) \
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2009-10-09 02:12:46 -06:00
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: "memory"); \
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break; \
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2010-07-28 16:18:35 -06:00
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} \
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2009-10-09 02:12:46 -06:00
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default: \
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__xchg_wrong_size(); \
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} \
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__x; \
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})
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#define xchg(ptr, v) \
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__xchg((v), (ptr), sizeof(*ptr))
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2007-05-08 01:35:02 -06:00
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/*
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2010-07-28 00:29:52 -06:00
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* CMPXCHG8B only writes to the target if we had the previous
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* value in registers, otherwise it acts as a read and gives us the
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* "new previous" value. That is why there is a loop. Preloading
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* EDX:EAX is a performance optimization: in the common case it means
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* we need only one locked operation.
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2007-05-08 01:35:02 -06:00
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*
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2010-07-28 00:29:52 -06:00
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* A SIMD/3DNOW!/MMX/FPU 64-bit store here would require at the very
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* least an FPU save and/or %cr0.ts manipulation.
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*
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* cmpxchg8b must be used with the lock prefix here to allow the
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* instruction to be executed atomically. We need to have the reader
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* side to see the coherent 64bit value.
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2007-05-08 01:35:02 -06:00
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*/
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2010-07-28 00:29:52 -06:00
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static inline void set_64bit(volatile u64 *ptr, u64 value)
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2007-05-08 01:35:02 -06:00
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{
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2010-07-28 00:29:52 -06:00
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u32 low = value;
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u32 high = value >> 32;
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u64 prev = *ptr;
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2008-03-23 02:01:51 -06:00
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asm volatile("\n1:\t"
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2010-07-28 00:29:52 -06:00
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LOCK_PREFIX "cmpxchg8b %0\n\t"
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2008-03-23 02:01:51 -06:00
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"jnz 1b"
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2010-07-28 00:29:52 -06:00
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: "=m" (*ptr), "+A" (prev)
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: "b" (low), "c" (high)
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: "memory");
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2007-05-08 01:35:02 -06:00
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}
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2009-10-09 02:12:46 -06:00
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extern void __cmpxchg_wrong_size(void);
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2007-05-08 01:35:02 -06:00
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*/
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2009-10-09 02:12:46 -06:00
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#define __raw_cmpxchg(ptr, old, new, size, lock) \
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({ \
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__typeof__(*(ptr)) __ret; \
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__typeof__(*(ptr)) __old = (old); \
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__typeof__(*(ptr)) __new = (new); \
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switch (size) { \
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case 1: \
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2010-07-28 16:18:35 -06:00
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{ \
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volatile u8 *__ptr = (volatile u8 *)(ptr); \
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asm volatile(lock "cmpxchgb %2,%1" \
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: "=a" (__ret), "+m" (*__ptr) \
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2010-07-27 18:01:49 -06:00
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: "q" (__new), "0" (__old) \
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2009-10-09 02:12:46 -06:00
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: "memory"); \
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break; \
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2010-07-28 16:18:35 -06:00
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} \
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2009-10-09 02:12:46 -06:00
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case 2: \
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2010-07-28 16:18:35 -06:00
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{ \
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volatile u16 *__ptr = (volatile u16 *)(ptr); \
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asm volatile(lock "cmpxchgw %2,%1" \
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: "=a" (__ret), "+m" (*__ptr) \
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2010-07-27 18:01:49 -06:00
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: "r" (__new), "0" (__old) \
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2009-10-09 02:12:46 -06:00
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: "memory"); \
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break; \
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2010-07-28 16:18:35 -06:00
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} \
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2009-10-09 02:12:46 -06:00
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case 4: \
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2010-07-28 16:18:35 -06:00
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{ \
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volatile u32 *__ptr = (volatile u32 *)(ptr); \
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2010-07-27 18:01:49 -06:00
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asm volatile(lock "cmpxchgl %2,%1" \
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2010-07-28 16:18:35 -06:00
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: "=a" (__ret), "+m" (*__ptr) \
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2010-07-27 18:01:49 -06:00
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: "r" (__new), "0" (__old) \
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2009-10-09 02:12:46 -06:00
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: "memory"); \
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break; \
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2010-07-28 16:18:35 -06:00
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} \
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2009-10-09 02:12:46 -06:00
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default: \
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__cmpxchg_wrong_size(); \
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} \
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__ret; \
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})
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#define __cmpxchg(ptr, old, new, size) \
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__raw_cmpxchg((ptr), (old), (new), (size), LOCK_PREFIX)
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#define __sync_cmpxchg(ptr, old, new, size) \
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__raw_cmpxchg((ptr), (old), (new), (size), "lock; ")
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#define __cmpxchg_local(ptr, old, new, size) \
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__raw_cmpxchg((ptr), (old), (new), (size), "")
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2007-05-08 01:35:02 -06:00
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#ifdef CONFIG_X86_CMPXCHG
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#define __HAVE_ARCH_CMPXCHG 1
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2009-10-09 02:12:46 -06:00
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#define cmpxchg(ptr, old, new) \
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__cmpxchg((ptr), (old), (new), sizeof(*ptr))
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#define sync_cmpxchg(ptr, old, new) \
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__sync_cmpxchg((ptr), (old), (new), sizeof(*ptr))
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#define cmpxchg_local(ptr, old, new) \
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__cmpxchg_local((ptr), (old), (new), sizeof(*ptr))
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x86: fall back on interrupt disable in cmpxchg8b on 80386 and 80486
Actually, on 386, cmpxchg and cmpxchg_local fall back on
cmpxchg_386_u8/16/32: it disables interruptions around non atomic
updates to mimic the cmpxchg behavior.
The comment:
/* Poor man's cmpxchg for 386. Unsuitable for SMP */
already present in cmpxchg_386_u32 tells much about how this cmpxchg
implementation should not be used in a SMP context. However, the cmpxchg_local
can perfectly use this fallback, since it only needs to be atomic wrt the local
cpu.
This patch adds a cmpxchg_486_u64 and uses it as a fallback for cmpxchg64
and cmpxchg64_local on 80386 and 80486.
Q:
but why is it called cmpxchg_486 when the other functions are called
A:
Because the standard cmpxchg is missing only on 386, but cmpxchg8b is
missing both on 386 and 486.
Citing Intel's Instruction set reference:
cmpxchg:
This instruction is not supported on Intel processors earlier than the
Intel486 processors.
cmpxchg8b:
This instruction encoding is not supported on Intel processors earlier
than the Pentium processors.
Q:
What's the reason to have cmpxchg64_local on 32 bit architectures?
Without that need all this would just be a few simple defines.
A:
cmpxchg64_local on 32 bits architectures takes unsigned long long
parameters, but cmpxchg_local only takes longs. Since we have cmpxchg8b
to execute a 8 byte cmpxchg atomically on pentium and +, it makes sense
to provide a flavor of cmpxchg and cmpxchg_local using this instruction.
Also, for 32 bits architectures lacking the 64 bits atomic cmpxchg, it
makes sense _not_ to define cmpxchg64 while cmpxchg could still be
available.
Moreover, the fallback for cmpxchg8b on i386 for 386 and 486 is a
However, cmpxchg64_local will be emulated by disabling interrupts on all
architectures where it is not supported atomically.
Therefore, we *could* turn cmpxchg64_local into a cmpxchg_local, but it
would make the 386/486 fallbacks ugly, make its design different from
cmpxchg/cmpxchg64 (which really depends on atomic operations and cannot
be emulated) and require the __cmpxchg_local to be expressed as a macro
rather than an inline function so the parameters would not be fixed to
unsigned long long in every case.
So I think cmpxchg64_local makes sense there, but I am open to
suggestions.
Q:
Are there any callers?
A:
I am actually using it in LTTng in my timestamping code. I use it to
work around CPUs with asynchronous TSCs. I need to update 64 bits
values atomically on this 32 bits architecture.
Changelog:
- Ran though checkpatch.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Cc: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30 05:30:47 -07:00
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#endif
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#ifdef CONFIG_X86_CMPXCHG64
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2008-03-23 02:01:51 -06:00
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#define cmpxchg64(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg64((ptr), (unsigned long long)(o), \
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(unsigned long long)(n)))
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#define cmpxchg64_local(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg64_local((ptr), (unsigned long long)(o), \
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(unsigned long long)(n)))
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2007-05-08 01:35:02 -06:00
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#endif
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2010-07-28 16:18:35 -06:00
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static inline u64 __cmpxchg64(volatile u64 *ptr, u64 old, u64 new)
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x86: fall back on interrupt disable in cmpxchg8b on 80386 and 80486
Actually, on 386, cmpxchg and cmpxchg_local fall back on
cmpxchg_386_u8/16/32: it disables interruptions around non atomic
updates to mimic the cmpxchg behavior.
The comment:
/* Poor man's cmpxchg for 386. Unsuitable for SMP */
already present in cmpxchg_386_u32 tells much about how this cmpxchg
implementation should not be used in a SMP context. However, the cmpxchg_local
can perfectly use this fallback, since it only needs to be atomic wrt the local
cpu.
This patch adds a cmpxchg_486_u64 and uses it as a fallback for cmpxchg64
and cmpxchg64_local on 80386 and 80486.
Q:
but why is it called cmpxchg_486 when the other functions are called
A:
Because the standard cmpxchg is missing only on 386, but cmpxchg8b is
missing both on 386 and 486.
Citing Intel's Instruction set reference:
cmpxchg:
This instruction is not supported on Intel processors earlier than the
Intel486 processors.
cmpxchg8b:
This instruction encoding is not supported on Intel processors earlier
than the Pentium processors.
Q:
What's the reason to have cmpxchg64_local on 32 bit architectures?
Without that need all this would just be a few simple defines.
A:
cmpxchg64_local on 32 bits architectures takes unsigned long long
parameters, but cmpxchg_local only takes longs. Since we have cmpxchg8b
to execute a 8 byte cmpxchg atomically on pentium and +, it makes sense
to provide a flavor of cmpxchg and cmpxchg_local using this instruction.
Also, for 32 bits architectures lacking the 64 bits atomic cmpxchg, it
makes sense _not_ to define cmpxchg64 while cmpxchg could still be
available.
Moreover, the fallback for cmpxchg8b on i386 for 386 and 486 is a
However, cmpxchg64_local will be emulated by disabling interrupts on all
architectures where it is not supported atomically.
Therefore, we *could* turn cmpxchg64_local into a cmpxchg_local, but it
would make the 386/486 fallbacks ugly, make its design different from
cmpxchg/cmpxchg64 (which really depends on atomic operations and cannot
be emulated) and require the __cmpxchg_local to be expressed as a macro
rather than an inline function so the parameters would not be fixed to
unsigned long long in every case.
So I think cmpxchg64_local makes sense there, but I am open to
suggestions.
Q:
Are there any callers?
A:
I am actually using it in LTTng in my timestamping code. I use it to
work around CPUs with asynchronous TSCs. I need to update 64 bits
values atomically on this 32 bits architecture.
Changelog:
- Ran though checkpatch.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Cc: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30 05:30:47 -07:00
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{
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2010-07-28 16:18:35 -06:00
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u64 prev;
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2010-07-27 18:01:49 -06:00
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asm volatile(LOCK_PREFIX "cmpxchg8b %1"
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: "=A" (prev),
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2010-07-28 16:18:35 -06:00
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"+m" (*ptr)
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: "b" ((u32)new),
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"c" ((u32)(new >> 32)),
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2010-07-27 18:01:49 -06:00
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"0" (old)
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2008-03-23 02:01:51 -06:00
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: "memory");
|
x86: fall back on interrupt disable in cmpxchg8b on 80386 and 80486
Actually, on 386, cmpxchg and cmpxchg_local fall back on
cmpxchg_386_u8/16/32: it disables interruptions around non atomic
updates to mimic the cmpxchg behavior.
The comment:
/* Poor man's cmpxchg for 386. Unsuitable for SMP */
already present in cmpxchg_386_u32 tells much about how this cmpxchg
implementation should not be used in a SMP context. However, the cmpxchg_local
can perfectly use this fallback, since it only needs to be atomic wrt the local
cpu.
This patch adds a cmpxchg_486_u64 and uses it as a fallback for cmpxchg64
and cmpxchg64_local on 80386 and 80486.
Q:
but why is it called cmpxchg_486 when the other functions are called
A:
Because the standard cmpxchg is missing only on 386, but cmpxchg8b is
missing both on 386 and 486.
Citing Intel's Instruction set reference:
cmpxchg:
This instruction is not supported on Intel processors earlier than the
Intel486 processors.
cmpxchg8b:
This instruction encoding is not supported on Intel processors earlier
than the Pentium processors.
Q:
What's the reason to have cmpxchg64_local on 32 bit architectures?
Without that need all this would just be a few simple defines.
A:
cmpxchg64_local on 32 bits architectures takes unsigned long long
parameters, but cmpxchg_local only takes longs. Since we have cmpxchg8b
to execute a 8 byte cmpxchg atomically on pentium and +, it makes sense
to provide a flavor of cmpxchg and cmpxchg_local using this instruction.
Also, for 32 bits architectures lacking the 64 bits atomic cmpxchg, it
makes sense _not_ to define cmpxchg64 while cmpxchg could still be
available.
Moreover, the fallback for cmpxchg8b on i386 for 386 and 486 is a
However, cmpxchg64_local will be emulated by disabling interrupts on all
architectures where it is not supported atomically.
Therefore, we *could* turn cmpxchg64_local into a cmpxchg_local, but it
would make the 386/486 fallbacks ugly, make its design different from
cmpxchg/cmpxchg64 (which really depends on atomic operations and cannot
be emulated) and require the __cmpxchg_local to be expressed as a macro
rather than an inline function so the parameters would not be fixed to
unsigned long long in every case.
So I think cmpxchg64_local makes sense there, but I am open to
suggestions.
Q:
Are there any callers?
A:
I am actually using it in LTTng in my timestamping code. I use it to
work around CPUs with asynchronous TSCs. I need to update 64 bits
values atomically on this 32 bits architecture.
Changelog:
- Ran though checkpatch.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Cc: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30 05:30:47 -07:00
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return prev;
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}
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|
2010-07-28 16:18:35 -06:00
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static inline u64 __cmpxchg64_local(volatile u64 *ptr, u64 old, u64 new)
|
x86: fall back on interrupt disable in cmpxchg8b on 80386 and 80486
Actually, on 386, cmpxchg and cmpxchg_local fall back on
cmpxchg_386_u8/16/32: it disables interruptions around non atomic
updates to mimic the cmpxchg behavior.
The comment:
/* Poor man's cmpxchg for 386. Unsuitable for SMP */
already present in cmpxchg_386_u32 tells much about how this cmpxchg
implementation should not be used in a SMP context. However, the cmpxchg_local
can perfectly use this fallback, since it only needs to be atomic wrt the local
cpu.
This patch adds a cmpxchg_486_u64 and uses it as a fallback for cmpxchg64
and cmpxchg64_local on 80386 and 80486.
Q:
but why is it called cmpxchg_486 when the other functions are called
A:
Because the standard cmpxchg is missing only on 386, but cmpxchg8b is
missing both on 386 and 486.
Citing Intel's Instruction set reference:
cmpxchg:
This instruction is not supported on Intel processors earlier than the
Intel486 processors.
cmpxchg8b:
This instruction encoding is not supported on Intel processors earlier
than the Pentium processors.
Q:
What's the reason to have cmpxchg64_local on 32 bit architectures?
Without that need all this would just be a few simple defines.
A:
cmpxchg64_local on 32 bits architectures takes unsigned long long
parameters, but cmpxchg_local only takes longs. Since we have cmpxchg8b
to execute a 8 byte cmpxchg atomically on pentium and +, it makes sense
to provide a flavor of cmpxchg and cmpxchg_local using this instruction.
Also, for 32 bits architectures lacking the 64 bits atomic cmpxchg, it
makes sense _not_ to define cmpxchg64 while cmpxchg could still be
available.
Moreover, the fallback for cmpxchg8b on i386 for 386 and 486 is a
However, cmpxchg64_local will be emulated by disabling interrupts on all
architectures where it is not supported atomically.
Therefore, we *could* turn cmpxchg64_local into a cmpxchg_local, but it
would make the 386/486 fallbacks ugly, make its design different from
cmpxchg/cmpxchg64 (which really depends on atomic operations and cannot
be emulated) and require the __cmpxchg_local to be expressed as a macro
rather than an inline function so the parameters would not be fixed to
unsigned long long in every case.
So I think cmpxchg64_local makes sense there, but I am open to
suggestions.
Q:
Are there any callers?
A:
I am actually using it in LTTng in my timestamping code. I use it to
work around CPUs with asynchronous TSCs. I need to update 64 bits
values atomically on this 32 bits architecture.
Changelog:
- Ran though checkpatch.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Cc: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30 05:30:47 -07:00
|
|
|
{
|
2010-07-28 16:18:35 -06:00
|
|
|
u64 prev;
|
2010-07-27 18:01:49 -06:00
|
|
|
asm volatile("cmpxchg8b %1"
|
|
|
|
: "=A" (prev),
|
2010-07-28 16:18:35 -06:00
|
|
|
"+m" (*ptr)
|
|
|
|
: "b" ((u32)new),
|
|
|
|
"c" ((u32)(new >> 32)),
|
2010-07-27 18:01:49 -06:00
|
|
|
"0" (old)
|
2008-03-23 02:01:51 -06:00
|
|
|
: "memory");
|
x86: fall back on interrupt disable in cmpxchg8b on 80386 and 80486
Actually, on 386, cmpxchg and cmpxchg_local fall back on
cmpxchg_386_u8/16/32: it disables interruptions around non atomic
updates to mimic the cmpxchg behavior.
The comment:
/* Poor man's cmpxchg for 386. Unsuitable for SMP */
already present in cmpxchg_386_u32 tells much about how this cmpxchg
implementation should not be used in a SMP context. However, the cmpxchg_local
can perfectly use this fallback, since it only needs to be atomic wrt the local
cpu.
This patch adds a cmpxchg_486_u64 and uses it as a fallback for cmpxchg64
and cmpxchg64_local on 80386 and 80486.
Q:
but why is it called cmpxchg_486 when the other functions are called
A:
Because the standard cmpxchg is missing only on 386, but cmpxchg8b is
missing both on 386 and 486.
Citing Intel's Instruction set reference:
cmpxchg:
This instruction is not supported on Intel processors earlier than the
Intel486 processors.
cmpxchg8b:
This instruction encoding is not supported on Intel processors earlier
than the Pentium processors.
Q:
What's the reason to have cmpxchg64_local on 32 bit architectures?
Without that need all this would just be a few simple defines.
A:
cmpxchg64_local on 32 bits architectures takes unsigned long long
parameters, but cmpxchg_local only takes longs. Since we have cmpxchg8b
to execute a 8 byte cmpxchg atomically on pentium and +, it makes sense
to provide a flavor of cmpxchg and cmpxchg_local using this instruction.
Also, for 32 bits architectures lacking the 64 bits atomic cmpxchg, it
makes sense _not_ to define cmpxchg64 while cmpxchg could still be
available.
Moreover, the fallback for cmpxchg8b on i386 for 386 and 486 is a
However, cmpxchg64_local will be emulated by disabling interrupts on all
architectures where it is not supported atomically.
Therefore, we *could* turn cmpxchg64_local into a cmpxchg_local, but it
would make the 386/486 fallbacks ugly, make its design different from
cmpxchg/cmpxchg64 (which really depends on atomic operations and cannot
be emulated) and require the __cmpxchg_local to be expressed as a macro
rather than an inline function so the parameters would not be fixed to
unsigned long long in every case.
So I think cmpxchg64_local makes sense there, but I am open to
suggestions.
Q:
Are there any callers?
A:
I am actually using it in LTTng in my timestamping code. I use it to
work around CPUs with asynchronous TSCs. I need to update 64 bits
values atomically on this 32 bits architecture.
Changelog:
- Ran though checkpatch.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Cc: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30 05:30:47 -07:00
|
|
|
return prev;
|
|
|
|
}
|
|
|
|
|
2007-05-08 01:35:02 -06:00
|
|
|
#ifndef CONFIG_X86_CMPXCHG
|
|
|
|
/*
|
|
|
|
* Building a kernel capable running on 80386. It may be necessary to
|
|
|
|
* simulate the cmpxchg on the 80386 CPU. For that purpose we define
|
|
|
|
* a function for each of the sizes we support.
|
|
|
|
*/
|
|
|
|
|
|
|
|
extern unsigned long cmpxchg_386_u8(volatile void *, u8, u8);
|
|
|
|
extern unsigned long cmpxchg_386_u16(volatile void *, u16, u16);
|
|
|
|
extern unsigned long cmpxchg_386_u32(volatile void *, u32, u32);
|
|
|
|
|
|
|
|
static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
|
2008-03-23 02:01:51 -06:00
|
|
|
unsigned long new, int size)
|
2007-05-08 01:35:02 -06:00
|
|
|
{
|
|
|
|
switch (size) {
|
|
|
|
case 1:
|
|
|
|
return cmpxchg_386_u8(ptr, old, new);
|
|
|
|
case 2:
|
|
|
|
return cmpxchg_386_u16(ptr, old, new);
|
|
|
|
case 4:
|
|
|
|
return cmpxchg_386_u32(ptr, old, new);
|
|
|
|
}
|
|
|
|
return old;
|
|
|
|
}
|
|
|
|
|
x86: fall back on interrupt disable in cmpxchg8b on 80386 and 80486
Actually, on 386, cmpxchg and cmpxchg_local fall back on
cmpxchg_386_u8/16/32: it disables interruptions around non atomic
updates to mimic the cmpxchg behavior.
The comment:
/* Poor man's cmpxchg for 386. Unsuitable for SMP */
already present in cmpxchg_386_u32 tells much about how this cmpxchg
implementation should not be used in a SMP context. However, the cmpxchg_local
can perfectly use this fallback, since it only needs to be atomic wrt the local
cpu.
This patch adds a cmpxchg_486_u64 and uses it as a fallback for cmpxchg64
and cmpxchg64_local on 80386 and 80486.
Q:
but why is it called cmpxchg_486 when the other functions are called
A:
Because the standard cmpxchg is missing only on 386, but cmpxchg8b is
missing both on 386 and 486.
Citing Intel's Instruction set reference:
cmpxchg:
This instruction is not supported on Intel processors earlier than the
Intel486 processors.
cmpxchg8b:
This instruction encoding is not supported on Intel processors earlier
than the Pentium processors.
Q:
What's the reason to have cmpxchg64_local on 32 bit architectures?
Without that need all this would just be a few simple defines.
A:
cmpxchg64_local on 32 bits architectures takes unsigned long long
parameters, but cmpxchg_local only takes longs. Since we have cmpxchg8b
to execute a 8 byte cmpxchg atomically on pentium and +, it makes sense
to provide a flavor of cmpxchg and cmpxchg_local using this instruction.
Also, for 32 bits architectures lacking the 64 bits atomic cmpxchg, it
makes sense _not_ to define cmpxchg64 while cmpxchg could still be
available.
Moreover, the fallback for cmpxchg8b on i386 for 386 and 486 is a
However, cmpxchg64_local will be emulated by disabling interrupts on all
architectures where it is not supported atomically.
Therefore, we *could* turn cmpxchg64_local into a cmpxchg_local, but it
would make the 386/486 fallbacks ugly, make its design different from
cmpxchg/cmpxchg64 (which really depends on atomic operations and cannot
be emulated) and require the __cmpxchg_local to be expressed as a macro
rather than an inline function so the parameters would not be fixed to
unsigned long long in every case.
So I think cmpxchg64_local makes sense there, but I am open to
suggestions.
Q:
Are there any callers?
A:
I am actually using it in LTTng in my timestamping code. I use it to
work around CPUs with asynchronous TSCs. I need to update 64 bits
values atomically on this 32 bits architecture.
Changelog:
- Ran though checkpatch.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Cc: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30 05:30:47 -07:00
|
|
|
#define cmpxchg(ptr, o, n) \
|
2007-05-08 01:35:02 -06:00
|
|
|
({ \
|
|
|
|
__typeof__(*(ptr)) __ret; \
|
|
|
|
if (likely(boot_cpu_data.x86 > 3)) \
|
2008-03-06 05:45:46 -07:00
|
|
|
__ret = (__typeof__(*(ptr)))__cmpxchg((ptr), \
|
|
|
|
(unsigned long)(o), (unsigned long)(n), \
|
|
|
|
sizeof(*(ptr))); \
|
2007-05-08 01:35:02 -06:00
|
|
|
else \
|
2008-03-06 05:45:46 -07:00
|
|
|
__ret = (__typeof__(*(ptr)))cmpxchg_386((ptr), \
|
|
|
|
(unsigned long)(o), (unsigned long)(n), \
|
|
|
|
sizeof(*(ptr))); \
|
2007-05-08 01:35:02 -06:00
|
|
|
__ret; \
|
|
|
|
})
|
x86: fall back on interrupt disable in cmpxchg8b on 80386 and 80486
Actually, on 386, cmpxchg and cmpxchg_local fall back on
cmpxchg_386_u8/16/32: it disables interruptions around non atomic
updates to mimic the cmpxchg behavior.
The comment:
/* Poor man's cmpxchg for 386. Unsuitable for SMP */
already present in cmpxchg_386_u32 tells much about how this cmpxchg
implementation should not be used in a SMP context. However, the cmpxchg_local
can perfectly use this fallback, since it only needs to be atomic wrt the local
cpu.
This patch adds a cmpxchg_486_u64 and uses it as a fallback for cmpxchg64
and cmpxchg64_local on 80386 and 80486.
Q:
but why is it called cmpxchg_486 when the other functions are called
A:
Because the standard cmpxchg is missing only on 386, but cmpxchg8b is
missing both on 386 and 486.
Citing Intel's Instruction set reference:
cmpxchg:
This instruction is not supported on Intel processors earlier than the
Intel486 processors.
cmpxchg8b:
This instruction encoding is not supported on Intel processors earlier
than the Pentium processors.
Q:
What's the reason to have cmpxchg64_local on 32 bit architectures?
Without that need all this would just be a few simple defines.
A:
cmpxchg64_local on 32 bits architectures takes unsigned long long
parameters, but cmpxchg_local only takes longs. Since we have cmpxchg8b
to execute a 8 byte cmpxchg atomically on pentium and +, it makes sense
to provide a flavor of cmpxchg and cmpxchg_local using this instruction.
Also, for 32 bits architectures lacking the 64 bits atomic cmpxchg, it
makes sense _not_ to define cmpxchg64 while cmpxchg could still be
available.
Moreover, the fallback for cmpxchg8b on i386 for 386 and 486 is a
However, cmpxchg64_local will be emulated by disabling interrupts on all
architectures where it is not supported atomically.
Therefore, we *could* turn cmpxchg64_local into a cmpxchg_local, but it
would make the 386/486 fallbacks ugly, make its design different from
cmpxchg/cmpxchg64 (which really depends on atomic operations and cannot
be emulated) and require the __cmpxchg_local to be expressed as a macro
rather than an inline function so the parameters would not be fixed to
unsigned long long in every case.
So I think cmpxchg64_local makes sense there, but I am open to
suggestions.
Q:
Are there any callers?
A:
I am actually using it in LTTng in my timestamping code. I use it to
work around CPUs with asynchronous TSCs. I need to update 64 bits
values atomically on this 32 bits architecture.
Changelog:
- Ran though checkpatch.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Cc: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30 05:30:47 -07:00
|
|
|
#define cmpxchg_local(ptr, o, n) \
|
2007-05-08 01:35:02 -06:00
|
|
|
({ \
|
|
|
|
__typeof__(*(ptr)) __ret; \
|
|
|
|
if (likely(boot_cpu_data.x86 > 3)) \
|
2008-03-06 05:45:46 -07:00
|
|
|
__ret = (__typeof__(*(ptr)))__cmpxchg_local((ptr), \
|
|
|
|
(unsigned long)(o), (unsigned long)(n), \
|
|
|
|
sizeof(*(ptr))); \
|
2007-05-08 01:35:02 -06:00
|
|
|
else \
|
2008-03-06 05:45:46 -07:00
|
|
|
__ret = (__typeof__(*(ptr)))cmpxchg_386((ptr), \
|
|
|
|
(unsigned long)(o), (unsigned long)(n), \
|
|
|
|
sizeof(*(ptr))); \
|
2007-05-08 01:35:02 -06:00
|
|
|
__ret; \
|
|
|
|
})
|
|
|
|
#endif
|
|
|
|
|
x86: fall back on interrupt disable in cmpxchg8b on 80386 and 80486
Actually, on 386, cmpxchg and cmpxchg_local fall back on
cmpxchg_386_u8/16/32: it disables interruptions around non atomic
updates to mimic the cmpxchg behavior.
The comment:
/* Poor man's cmpxchg for 386. Unsuitable for SMP */
already present in cmpxchg_386_u32 tells much about how this cmpxchg
implementation should not be used in a SMP context. However, the cmpxchg_local
can perfectly use this fallback, since it only needs to be atomic wrt the local
cpu.
This patch adds a cmpxchg_486_u64 and uses it as a fallback for cmpxchg64
and cmpxchg64_local on 80386 and 80486.
Q:
but why is it called cmpxchg_486 when the other functions are called
A:
Because the standard cmpxchg is missing only on 386, but cmpxchg8b is
missing both on 386 and 486.
Citing Intel's Instruction set reference:
cmpxchg:
This instruction is not supported on Intel processors earlier than the
Intel486 processors.
cmpxchg8b:
This instruction encoding is not supported on Intel processors earlier
than the Pentium processors.
Q:
What's the reason to have cmpxchg64_local on 32 bit architectures?
Without that need all this would just be a few simple defines.
A:
cmpxchg64_local on 32 bits architectures takes unsigned long long
parameters, but cmpxchg_local only takes longs. Since we have cmpxchg8b
to execute a 8 byte cmpxchg atomically on pentium and +, it makes sense
to provide a flavor of cmpxchg and cmpxchg_local using this instruction.
Also, for 32 bits architectures lacking the 64 bits atomic cmpxchg, it
makes sense _not_ to define cmpxchg64 while cmpxchg could still be
available.
Moreover, the fallback for cmpxchg8b on i386 for 386 and 486 is a
However, cmpxchg64_local will be emulated by disabling interrupts on all
architectures where it is not supported atomically.
Therefore, we *could* turn cmpxchg64_local into a cmpxchg_local, but it
would make the 386/486 fallbacks ugly, make its design different from
cmpxchg/cmpxchg64 (which really depends on atomic operations and cannot
be emulated) and require the __cmpxchg_local to be expressed as a macro
rather than an inline function so the parameters would not be fixed to
unsigned long long in every case.
So I think cmpxchg64_local makes sense there, but I am open to
suggestions.
Q:
Are there any callers?
A:
I am actually using it in LTTng in my timestamping code. I use it to
work around CPUs with asynchronous TSCs. I need to update 64 bits
values atomically on this 32 bits architecture.
Changelog:
- Ran though checkpatch.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Cc: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30 05:30:47 -07:00
|
|
|
#ifndef CONFIG_X86_CMPXCHG64
|
|
|
|
/*
|
|
|
|
* Building a kernel capable running on 80386 and 80486. It may be necessary
|
|
|
|
* to simulate the cmpxchg8b on the 80386 and 80486 CPU.
|
|
|
|
*/
|
2007-05-08 01:35:02 -06:00
|
|
|
|
2009-09-30 09:07:54 -06:00
|
|
|
#define cmpxchg64(ptr, o, n) \
|
|
|
|
({ \
|
|
|
|
__typeof__(*(ptr)) __ret; \
|
|
|
|
__typeof__(*(ptr)) __old = (o); \
|
|
|
|
__typeof__(*(ptr)) __new = (n); \
|
2010-02-24 02:54:23 -07:00
|
|
|
alternative_io(LOCK_PREFIX_HERE \
|
|
|
|
"call cmpxchg8b_emu", \
|
2009-09-30 09:07:54 -06:00
|
|
|
"lock; cmpxchg8b (%%esi)" , \
|
|
|
|
X86_FEATURE_CX8, \
|
|
|
|
"=A" (__ret), \
|
|
|
|
"S" ((ptr)), "0" (__old), \
|
|
|
|
"b" ((unsigned int)__new), \
|
|
|
|
"c" ((unsigned int)(__new>>32)) \
|
|
|
|
: "memory"); \
|
|
|
|
__ret; })
|
|
|
|
|
|
|
|
|
2010-07-28 18:05:11 -06:00
|
|
|
#define cmpxchg64_local(ptr, o, n) \
|
|
|
|
({ \
|
|
|
|
__typeof__(*(ptr)) __ret; \
|
|
|
|
__typeof__(*(ptr)) __old = (o); \
|
|
|
|
__typeof__(*(ptr)) __new = (n); \
|
|
|
|
alternative_io("call cmpxchg8b_emu", \
|
|
|
|
"cmpxchg8b (%%esi)" , \
|
|
|
|
X86_FEATURE_CX8, \
|
|
|
|
"=A" (__ret), \
|
|
|
|
"S" ((ptr)), "0" (__old), \
|
|
|
|
"b" ((unsigned int)__new), \
|
|
|
|
"c" ((unsigned int)(__new>>32)) \
|
|
|
|
: "memory"); \
|
|
|
|
__ret; })
|
x86: fall back on interrupt disable in cmpxchg8b on 80386 and 80486
Actually, on 386, cmpxchg and cmpxchg_local fall back on
cmpxchg_386_u8/16/32: it disables interruptions around non atomic
updates to mimic the cmpxchg behavior.
The comment:
/* Poor man's cmpxchg for 386. Unsuitable for SMP */
already present in cmpxchg_386_u32 tells much about how this cmpxchg
implementation should not be used in a SMP context. However, the cmpxchg_local
can perfectly use this fallback, since it only needs to be atomic wrt the local
cpu.
This patch adds a cmpxchg_486_u64 and uses it as a fallback for cmpxchg64
and cmpxchg64_local on 80386 and 80486.
Q:
but why is it called cmpxchg_486 when the other functions are called
A:
Because the standard cmpxchg is missing only on 386, but cmpxchg8b is
missing both on 386 and 486.
Citing Intel's Instruction set reference:
cmpxchg:
This instruction is not supported on Intel processors earlier than the
Intel486 processors.
cmpxchg8b:
This instruction encoding is not supported on Intel processors earlier
than the Pentium processors.
Q:
What's the reason to have cmpxchg64_local on 32 bit architectures?
Without that need all this would just be a few simple defines.
A:
cmpxchg64_local on 32 bits architectures takes unsigned long long
parameters, but cmpxchg_local only takes longs. Since we have cmpxchg8b
to execute a 8 byte cmpxchg atomically on pentium and +, it makes sense
to provide a flavor of cmpxchg and cmpxchg_local using this instruction.
Also, for 32 bits architectures lacking the 64 bits atomic cmpxchg, it
makes sense _not_ to define cmpxchg64 while cmpxchg could still be
available.
Moreover, the fallback for cmpxchg8b on i386 for 386 and 486 is a
However, cmpxchg64_local will be emulated by disabling interrupts on all
architectures where it is not supported atomically.
Therefore, we *could* turn cmpxchg64_local into a cmpxchg_local, but it
would make the 386/486 fallbacks ugly, make its design different from
cmpxchg/cmpxchg64 (which really depends on atomic operations and cannot
be emulated) and require the __cmpxchg_local to be expressed as a macro
rather than an inline function so the parameters would not be fixed to
unsigned long long in every case.
So I think cmpxchg64_local makes sense there, but I am open to
suggestions.
Q:
Are there any callers?
A:
I am actually using it in LTTng in my timestamping code. I use it to
work around CPUs with asynchronous TSCs. I need to update 64 bits
values atomically on this 32 bits architecture.
Changelog:
- Ran though checkpatch.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Cc: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30 05:30:47 -07:00
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#endif
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2007-05-08 01:35:02 -06:00
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2011-06-01 11:25:47 -06:00
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#define cmpxchg8b(ptr, o1, o2, n1, n2) \
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({ \
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char __ret; \
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__typeof__(o2) __dummy; \
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__typeof__(*(ptr)) __old1 = (o1); \
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__typeof__(o2) __old2 = (o2); \
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__typeof__(*(ptr)) __new1 = (n1); \
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__typeof__(o2) __new2 = (n2); \
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asm volatile(LOCK_PREFIX "cmpxchg8b %2; setz %1" \
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: "=d"(__dummy), "=a" (__ret), "+m" (*ptr)\
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: "a" (__old1), "d"(__old2), \
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"b" (__new1), "c" (__new2) \
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: "memory"); \
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__ret; })
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#define cmpxchg8b_local(ptr, o1, o2, n1, n2) \
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({ \
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char __ret; \
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__typeof__(o2) __dummy; \
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__typeof__(*(ptr)) __old1 = (o1); \
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__typeof__(o2) __old2 = (o2); \
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__typeof__(*(ptr)) __new1 = (n1); \
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__typeof__(o2) __new2 = (n2); \
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asm volatile("cmpxchg8b %2; setz %1" \
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: "=d"(__dummy), "=a"(__ret), "+m" (*ptr)\
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: "a" (__old), "d"(__old2), \
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"b" (__new1), "c" (__new2), \
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: "memory"); \
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__ret; })
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#define cmpxchg_double(ptr, o1, o2, n1, n2) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 4); \
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VM_BUG_ON((unsigned long)(ptr) % 8); \
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cmpxchg8b((ptr), (o1), (o2), (n1), (n2)); \
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})
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#define cmpxchg_double_local(ptr, o1, o2, n1, n2) \
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({ \
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BUILD_BUG_ON(sizeof(*(ptr)) != 4); \
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VM_BUG_ON((unsigned long)(ptr) % 8); \
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cmpxchg16b_local((ptr), (o1), (o2), (n1), (n2)); \
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})
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#define system_has_cmpxchg_double() cpu_has_cx8
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2008-10-22 23:26:29 -06:00
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#endif /* _ASM_X86_CMPXCHG_32_H */
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