License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 08:07:57 -06:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2008-04-20 10:32:16 -06:00
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#ifndef _ASM_ARCH_PXA27X_UDC_H
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#define _ASM_ARCH_PXA27X_UDC_H
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#ifdef _ASM_ARCH_PXA25X_UDC_H
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2008-05-31 09:18:11 -06:00
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#error You cannot include both PXA25x and PXA27x UDC support
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2008-04-20 10:32:16 -06:00
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#endif
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#define UDCCR __REG(0x40600000) /* UDC Control Register */
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#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
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#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
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Protocol Port Support */
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#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
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Support */
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#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
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Enable */
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#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
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#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
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#define UDCCR_ACN_S 11
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#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
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#define UDCCR_AIN_S 8
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#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
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Setting Number */
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#define UDCCR_AAISN_S 5
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#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
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Configuration */
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#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
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Error */
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#define UDCCR_UDR (1 << 2) /* UDC Resume */
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#define UDCCR_UDA (1 << 1) /* UDC Active */
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#define UDCCR_UDE (1 << 0) /* UDC Enable */
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#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
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#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
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#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
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#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
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#define UDC_INT_FIFOERROR (0x2)
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#define UDC_INT_PACKETCMP (0x1)
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#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
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#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
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#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
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#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
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#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
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#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
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#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
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#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
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#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
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#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
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#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
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#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
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#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
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#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
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#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
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#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
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#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
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2011-06-23 12:39:20 -06:00
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#define UDCOTGICR_IEXR (1 << 17) /* Extra Transceiver Interrupt
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2008-04-20 10:32:16 -06:00
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Rising Edge Interrupt Enable */
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2011-06-23 12:39:20 -06:00
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#define UDCOTGICR_IEXF (1 << 16) /* Extra Transceiver Interrupt
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2008-04-20 10:32:16 -06:00
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Falling Edge Interrupt Enable */
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#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
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Interrupt Enable */
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#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
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Interrupt Enable */
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#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
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Interrupt Enable */
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#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
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Interrupt Enable */
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#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
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Interrupt Enable */
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#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
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Interrupt Enable */
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#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
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Edge Interrupt Enable */
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#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
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Edge Interrupt Enable */
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#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
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Interrupt Enable */
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#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
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Interrupt Enable */
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#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
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2008-06-10 01:57:27 -06:00
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#define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */
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2008-04-20 10:32:16 -06:00
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#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
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#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
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#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
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#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
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#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
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#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
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#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
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#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
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#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
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#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
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#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
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#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
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#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
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2008-07-09 01:07:29 -06:00
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#define UP2OCR_SEOS(x) ((x & 7) << 24) /* Single-Ended Output Select */
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2008-04-20 10:32:16 -06:00
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#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
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#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
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#define UDCCSR0_SA (1 << 7) /* Setup Active */
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#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
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#define UDCCSR0_FST (1 << 5) /* Force Stall */
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#define UDCCSR0_SST (1 << 4) /* Sent Stall */
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#define UDCCSR0_DME (1 << 3) /* DMA Enable */
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#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
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#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
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#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
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#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
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#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
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#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
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#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
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#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
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#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
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#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
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#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
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#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
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#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
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#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
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#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
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#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
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#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
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#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
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#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
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#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
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#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
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#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
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#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
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#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
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#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
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#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
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#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
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#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
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#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
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#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
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#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
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#define UDCCSR_FST (1 << 5) /* Force STALL */
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#define UDCCSR_SST (1 << 4) /* Sent STALL */
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#define UDCCSR_DME (1 << 3) /* DMA Enable */
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#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
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#define UDCCSR_PC (1 << 1) /* Packet Complete */
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#define UDCCSR_FS (1 << 0) /* FIFO needs service */
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#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
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#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
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#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
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#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
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#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
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#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
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#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
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#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
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#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
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#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
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#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
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#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
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#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
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#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
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#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
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#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
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#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
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#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
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#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
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#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
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#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
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#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
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#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
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#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
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#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
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#define UDCDN(x) __REG2(0x40600300, (x)<<2)
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#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
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#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
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#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
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#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
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#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
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#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
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#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
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#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
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#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
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#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
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#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
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#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
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#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
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#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
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#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
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#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
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#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
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#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
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#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
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#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
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#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
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#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
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#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
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#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
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#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
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#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
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#define UDCCN(x) __REG2(0x40600400, (x)<<2)
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#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
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#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
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#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
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#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
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#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
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#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
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#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
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#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
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#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
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#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
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#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
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#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
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#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
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#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
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#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
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#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
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#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
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#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
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#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
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#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
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#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
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#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
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#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
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#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
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#define UDCCONR_CN_S (25)
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#define UDCCONR_IN (0x07 << 22) /* Interface Number */
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#define UDCCONR_IN_S (22)
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#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
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#define UDCCONR_AISN_S (19)
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#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
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#define UDCCONR_EN_S (15)
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#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
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#define UDCCONR_ET_S (13)
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#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
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#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
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#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
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#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
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#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
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#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
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#define UDCCONR_MPS_S (2)
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#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
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#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
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#define UDC_INT_FIFOERROR (0x2)
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#define UDC_INT_PACKETCMP (0x1)
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#define UDC_FNR_MASK (0x7ff)
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#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
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#define UDC_BCR_MASK (0x3ff)
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#endif
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