powerpc/85xx: Add support for P5040DS board
Add support for the Freescale P5040DS Reference Board ("Superhydra"), which
is similar to the P5020DS. Features of the P5040 are listed below, but
not all of these features (e.g. DPAA networking) are currently supported.
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-26 09:08:54 -06:00
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/*
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* P5040DS Device Tree Source
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*
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2015-02-27 08:16:14 -07:00
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* Copyright 2012 - 2014 Freescale Semiconductor Inc.
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powerpc/85xx: Add support for P5040DS board
Add support for the Freescale P5040DS Reference Board ("Superhydra"), which
is similar to the P5020DS. Features of the P5040 are listed below, but
not all of these features (e.g. DPAA networking) are currently supported.
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-26 09:08:54 -06:00
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* This software is provided by Freescale Semiconductor "as is" and any
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* express or implied warranties, including, but not limited to, the implied
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* warranties of merchantability and fitness for a particular purpose are
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* disclaimed. In no event shall Freescale Semiconductor be liable for any
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* direct, indirect, incidental, special, exemplary, or consequential damages
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* (including, but not limited to, procurement of substitute goods or services;
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* loss of use, data, or profits; or business interruption) however caused and
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* on any theory of liability, whether in contract, strict liability, or tort
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* (including negligence or otherwise) arising in any way out of the use of this
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* software, even if advised of the possibility of such damage.
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*/
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/include/ "fsl/p5040si-pre.dtsi"
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/ {
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model = "fsl,P5040DS";
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compatible = "fsl,P5040DS";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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memory {
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device_type = "memory";
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|
};
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|
2015-02-27 08:16:14 -07:00
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reserved-memory {
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#address-cells = <2>;
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|
#size-cells = <2>;
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ranges;
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bman_fbpr: bman-fbpr {
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|
size = <0 0x1000000>;
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alignment = <0 0x1000000>;
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};
|
2015-04-17 16:53:07 -06:00
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qman_fqd: qman-fqd {
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size = <0 0x400000>;
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alignment = <0 0x400000>;
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};
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qman_pfdr: qman-pfdr {
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size = <0 0x2000000>;
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alignment = <0 0x2000000>;
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};
|
2015-02-27 08:16:14 -07:00
|
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|
};
|
|
|
|
|
powerpc/85xx: Add support for P5040DS board
Add support for the Freescale P5040DS Reference Board ("Superhydra"), which
is similar to the P5020DS. Features of the P5040 are listed below, but
not all of these features (e.g. DPAA networking) are currently supported.
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-26 09:08:54 -06:00
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dcsr: dcsr@f00000000 {
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ranges = <0x00000000 0xf 0x00000000 0x01008000>;
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};
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2015-02-27 08:16:14 -07:00
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bportals: bman-portals@ff4000000 {
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ranges = <0x0 0xf 0xf4000000 0x200000>;
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};
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2015-04-17 16:53:07 -06:00
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qportals: qman-portals@ff4200000 {
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ranges = <0x0 0xf 0xf4200000 0x200000>;
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};
|
|
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|
|
powerpc/85xx: Add support for P5040DS board
Add support for the Freescale P5040DS Reference Board ("Superhydra"), which
is similar to the P5020DS. Features of the P5040 are listed below, but
not all of these features (e.g. DPAA networking) are currently supported.
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-26 09:08:54 -06:00
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soc: soc@ffe000000 {
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
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reg = <0xf 0xfe000000 0 0x00001000>;
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spi@110000 {
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spansion,s25sl12801";
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reg = <0>;
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spi-max-frequency = <40000000>; /* input clock */
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partition@u-boot {
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label = "u-boot";
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reg = <0x00000000 0x00100000>;
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};
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partition@kernel {
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label = "kernel";
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reg = <0x00100000 0x00500000>;
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};
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partition@dtb {
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label = "dtb";
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reg = <0x00600000 0x00100000>;
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};
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partition@fs {
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label = "file system";
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reg = <0x00700000 0x00900000>;
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};
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};
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};
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i2c@118100 {
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eeprom@51 {
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compatible = "at24,24c256";
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reg = <0x51>;
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};
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eeprom@52 {
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compatible = "at24,24c256";
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reg = <0x52>;
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};
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};
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i2c@119100 {
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rtc@68 {
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compatible = "dallas,ds3232";
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reg = <0x68>;
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interrupts = <0x1 0x1 0 0>;
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};
|
2014-11-04 23:59:53 -07:00
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ina220@40 {
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compatible = "ti,ina220";
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reg = <0x40>;
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shunt-resistor = <1000>;
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};
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ina220@41 {
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compatible = "ti,ina220";
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reg = <0x41>;
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shunt-resistor = <1000>;
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};
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ina220@44 {
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compatible = "ti,ina220";
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|
reg = <0x44>;
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|
shunt-resistor = <1000>;
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};
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ina220@45 {
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compatible = "ti,ina220";
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reg = <0x45>;
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shunt-resistor = <1000>;
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};
|
powerpc/p5040: fix dtb build warning of p5040ds.dtb
Device node adt7461 was wrongly added in p5040ds.dts, it should be added
into i2c instead of localbus, when build p5040ds.dtb, a warning will dump:
Warning (reg_format): "reg" property in
/localbus@ffe124000/nand@2,0/adt7461@4c has invalid length (4 bytes)
(#address-cells == 1, #size-cells == 1)
This was introduced by:
commit ea6b1ba692bcb5f6e39f409a78cf8b04fdf23baa
Author: Jia Hongtao <B38951@freescale.com>
Date: Tue Aug 28 10:00:55 2012 +0800
powerpc: add adt7461 thermal monitor support to applicable boards
Add thermal monitor support to following boards:
P1022DS, MPC8536DS, P2041RDB, P3041DS, P4080DS, P5020DS, P5040DS
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-09-12 04:36:03 -06:00
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adt7461@4c {
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compatible = "adi,adt7461";
|
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reg = <0x4c>;
|
|
|
|
};
|
powerpc/85xx: Add support for P5040DS board
Add support for the Freescale P5040DS Reference Board ("Superhydra"), which
is similar to the P5020DS. Features of the P5040 are listed below, but
not all of these features (e.g. DPAA networking) are currently supported.
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-07-26 09:08:54 -06:00
|
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|
};
|
|
|
|
};
|
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|
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|
lbc: localbus@ffe124000 {
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|
|
|
reg = <0xf 0xfe124000 0 0x1000>;
|
|
|
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ranges = <0 0 0xf 0xe8000000 0x08000000
|
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|
|
2 0 0xf 0xffa00000 0x00040000
|
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|
3 0 0xf 0xffdf0000 0x00008000>;
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|
flash@0,0 {
|
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|
|
compatible = "cfi-flash";
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|
|
|
reg = <0 0 0x08000000>;
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|
|
|
bank-width = <2>;
|
|
|
|
device-width = <2>;
|
|
|
|
};
|
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|
nand@2,0 {
|
|
|
|
#address-cells = <1>;
|
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|
|
#size-cells = <1>;
|
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|
|
compatible = "fsl,elbc-fcm-nand";
|
|
|
|
reg = <0x2 0x0 0x40000>;
|
|
|
|
|
|
|
|
partition@0 {
|
|
|
|
label = "NAND U-Boot Image";
|
|
|
|
reg = <0x0 0x02000000>;
|
|
|
|
};
|
|
|
|
|
|
|
|
partition@2000000 {
|
|
|
|
label = "NAND Root File System";
|
|
|
|
reg = <0x02000000 0x10000000>;
|
|
|
|
};
|
|
|
|
|
|
|
|
partition@12000000 {
|
|
|
|
label = "NAND Compressed RFS Image";
|
|
|
|
reg = <0x12000000 0x08000000>;
|
|
|
|
};
|
|
|
|
|
|
|
|
partition@1a000000 {
|
|
|
|
label = "NAND Linux Kernel Image";
|
|
|
|
reg = <0x1a000000 0x04000000>;
|
|
|
|
};
|
|
|
|
|
|
|
|
partition@1e000000 {
|
|
|
|
label = "NAND DTB Image";
|
|
|
|
reg = <0x1e000000 0x01000000>;
|
|
|
|
};
|
|
|
|
|
|
|
|
partition@1f000000 {
|
|
|
|
label = "NAND Writable User area";
|
|
|
|
reg = <0x1f000000 0x01000000>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
board-control@3,0 {
|
|
|
|
compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
|
|
|
|
reg = <3 0 0x40>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
pci0: pcie@ffe200000 {
|
|
|
|
reg = <0xf 0xfe200000 0 0x1000>;
|
|
|
|
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
|
|
|
|
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
|
|
|
|
pcie@0 {
|
|
|
|
ranges = <0x02000000 0 0xe0000000
|
|
|
|
0x02000000 0 0xe0000000
|
|
|
|
0 0x20000000
|
|
|
|
|
|
|
|
0x01000000 0 0x00000000
|
|
|
|
0x01000000 0 0x00000000
|
|
|
|
0 0x00010000>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
pci1: pcie@ffe201000 {
|
|
|
|
reg = <0xf 0xfe201000 0 0x1000>;
|
|
|
|
ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
|
|
|
|
0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
|
|
|
|
pcie@0 {
|
|
|
|
ranges = <0x02000000 0 0xe0000000
|
|
|
|
0x02000000 0 0xe0000000
|
|
|
|
0 0x20000000
|
|
|
|
|
|
|
|
0x01000000 0 0x00000000
|
|
|
|
0x01000000 0 0x00000000
|
|
|
|
0 0x00010000>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
pci2: pcie@ffe202000 {
|
|
|
|
reg = <0xf 0xfe202000 0 0x1000>;
|
|
|
|
ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
|
|
|
|
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
|
|
|
|
pcie@0 {
|
|
|
|
ranges = <0x02000000 0 0xe0000000
|
|
|
|
0x02000000 0 0xe0000000
|
|
|
|
0 0x20000000
|
|
|
|
|
|
|
|
0x01000000 0 0x00000000
|
|
|
|
0x01000000 0 0x00000000
|
|
|
|
0 0x00010000>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
/include/ "fsl/p5040si-post.dtsi"
|