2013-08-13 03:56:54 -06:00
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/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#include <linux/firmware.h>
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#include <drm/drmP.h>
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#include "radeon.h"
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2014-06-25 17:32:36 -06:00
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#include "radeon_ucode.h"
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2013-08-13 03:56:54 -06:00
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#include "radeon_asic.h"
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2013-10-29 13:14:48 -06:00
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#include "radeon_trace.h"
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2013-08-13 03:56:54 -06:00
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#include "cikd.h"
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/* sdma */
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#define CIK_SDMA_UCODE_SIZE 1050
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#define CIK_SDMA_UCODE_VERSION 64
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u32 cik_gpu_check_soft_reset(struct radeon_device *rdev);
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/*
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* sDMA - System DMA
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* Starting with CIK, the GPU has new asynchronous
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* DMA engines. These engines are used for compute
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* and gfx. There are two DMA engines (SDMA0, SDMA1)
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* and each one supports 1 ring buffer used for gfx
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* and 2 queues used for compute.
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*
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* The programming model is very similar to the CP
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* (ring buffer, IBs, etc.), but sDMA has it's own
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* packet format that is different from the PM4 format
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* used by the CP. sDMA supports copying data, writing
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* embedded data, solid fills, and a number of other
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* things. It also has support for tiling/detiling of
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* buffers.
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*/
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2013-12-09 17:44:30 -07:00
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/**
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* cik_sdma_get_rptr - get the current read pointer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon ring pointer
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*
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* Get the current rptr from the hardware (CIK+).
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*/
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uint32_t cik_sdma_get_rptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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u32 rptr, reg;
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if (rdev->wb.enabled) {
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rptr = rdev->wb.wb[ring->rptr_offs/4];
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} else {
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if (ring->idx == R600_RING_TYPE_DMA_INDEX)
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reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET;
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else
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reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET;
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rptr = RREG32(reg);
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}
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return (rptr & 0x3fffc) >> 2;
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}
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/**
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* cik_sdma_get_wptr - get the current write pointer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon ring pointer
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*
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* Get the current wptr from the hardware (CIK+).
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*/
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uint32_t cik_sdma_get_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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u32 reg;
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if (ring->idx == R600_RING_TYPE_DMA_INDEX)
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reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
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else
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reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
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return (RREG32(reg) & 0x3fffc) >> 2;
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}
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/**
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* cik_sdma_set_wptr - commit the write pointer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon ring pointer
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*
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* Write the wptr back to the hardware (CIK+).
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*/
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void cik_sdma_set_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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u32 reg;
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if (ring->idx == R600_RING_TYPE_DMA_INDEX)
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reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
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else
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reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
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WREG32(reg, (ring->wptr << 2) & 0x3fffc);
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2014-07-29 03:47:22 -06:00
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(void)RREG32(reg);
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2013-12-09 17:44:30 -07:00
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}
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2013-08-13 03:56:54 -06:00
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/**
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* cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine
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*
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* @rdev: radeon_device pointer
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* @ib: IB object to schedule
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*
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* Schedule an IB in the DMA ring (CIK).
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*/
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void cik_sdma_ring_ib_execute(struct radeon_device *rdev,
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struct radeon_ib *ib)
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{
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struct radeon_ring *ring = &rdev->ring[ib->ring];
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2014-11-19 06:01:25 -07:00
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u32 extra_bits = (ib->vm ? ib->vm->ids[ib->ring].id : 0) & 0xf;
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2013-08-13 03:56:54 -06:00
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if (rdev->wb.enabled) {
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u32 next_rptr = ring->wptr + 5;
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while ((next_rptr & 7) != 4)
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next_rptr++;
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next_rptr += 4;
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radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
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radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
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2014-06-03 12:51:46 -06:00
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radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
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2013-08-13 03:56:54 -06:00
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radeon_ring_write(ring, 1); /* number of DWs to follow */
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radeon_ring_write(ring, next_rptr);
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}
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/* IB packet must end on a 8 DW boundary */
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while ((ring->wptr & 7) != 4)
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radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
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radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
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radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
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2014-06-03 12:51:46 -06:00
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radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
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2013-08-13 03:56:54 -06:00
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radeon_ring_write(ring, ib->length_dw);
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}
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2014-01-09 14:23:37 -07:00
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/**
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* cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
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*
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* @rdev: radeon_device pointer
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* @ridx: radeon ring index
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*
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* Emit an hdp flush packet on the requested DMA ring.
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*/
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static void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev,
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int ridx)
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{
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struct radeon_ring *ring = &rdev->ring[ridx];
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2014-01-09 14:35:39 -07:00
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u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
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SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
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u32 ref_and_mask;
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2014-01-09 14:23:37 -07:00
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2014-01-09 14:35:39 -07:00
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if (ridx == R600_RING_TYPE_DMA_INDEX)
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ref_and_mask = SDMA0;
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else
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ref_and_mask = SDMA1;
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radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
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radeon_ring_write(ring, GPU_HDP_FLUSH_DONE);
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radeon_ring_write(ring, GPU_HDP_FLUSH_REQ);
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radeon_ring_write(ring, ref_and_mask); /* reference */
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radeon_ring_write(ring, ref_and_mask); /* mask */
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radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
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2014-01-09 14:23:37 -07:00
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}
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2013-08-13 03:56:54 -06:00
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/**
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* cik_sdma_fence_ring_emit - emit a fence on the DMA ring
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*
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* @rdev: radeon_device pointer
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* @fence: radeon fence object
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*
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* Add a DMA fence packet to the ring to write
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* the fence seq number and DMA trap packet to generate
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* an interrupt if needed (CIK).
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*/
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void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
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struct radeon_fence *fence)
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{
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struct radeon_ring *ring = &rdev->ring[fence->ring];
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u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
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/* write the fence */
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radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
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2014-06-03 12:51:46 -06:00
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radeon_ring_write(ring, lower_32_bits(addr));
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radeon_ring_write(ring, upper_32_bits(addr));
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2013-08-13 03:56:54 -06:00
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radeon_ring_write(ring, fence->seq);
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/* generate an interrupt */
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radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
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/* flush HDP */
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2014-01-09 14:23:37 -07:00
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cik_sdma_hdp_flush_ring_emit(rdev, fence->ring);
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2013-08-13 03:56:54 -06:00
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}
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/**
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* cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring structure holding ring information
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* @semaphore: radeon semaphore object
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* @emit_wait: wait or signal semaphore
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*
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* Add a DMA semaphore packet to the ring wait on or signal
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* other rings (CIK).
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*/
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2013-11-12 04:58:05 -07:00
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bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
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2013-08-13 03:56:54 -06:00
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struct radeon_ring *ring,
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struct radeon_semaphore *semaphore,
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bool emit_wait)
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{
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u64 addr = semaphore->gpu_addr;
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u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;
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radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
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radeon_ring_write(ring, addr & 0xfffffff8);
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2014-06-03 12:51:46 -06:00
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radeon_ring_write(ring, upper_32_bits(addr));
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2013-11-12 04:58:05 -07:00
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return true;
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2013-08-13 03:56:54 -06:00
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}
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/**
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* cik_sdma_gfx_stop - stop the gfx async dma engines
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*
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* @rdev: radeon_device pointer
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*
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* Stop the gfx async dma ring buffers (CIK).
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*/
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static void cik_sdma_gfx_stop(struct radeon_device *rdev)
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{
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u32 rb_cntl, reg_offset;
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int i;
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2014-01-27 09:26:33 -07:00
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if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
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(rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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2013-08-13 03:56:54 -06:00
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for (i = 0; i < 2; i++) {
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if (i == 0)
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reg_offset = SDMA0_REGISTER_OFFSET;
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else
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reg_offset = SDMA1_REGISTER_OFFSET;
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rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);
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rb_cntl &= ~SDMA_RB_ENABLE;
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WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
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WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0);
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}
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2014-03-12 13:15:58 -06:00
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rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
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rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
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2015-06-19 08:32:16 -06:00
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/* FIXME use something else than big hammer but after few days can not
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* seem to find good combination so reset SDMA blocks as it seems we
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* do not shut them down properly. This fix hibernation and does not
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* affect suspend to ram.
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*/
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WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1);
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(void)RREG32(SRBM_SOFT_RESET);
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udelay(50);
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WREG32(SRBM_SOFT_RESET, 0);
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(void)RREG32(SRBM_SOFT_RESET);
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2013-08-13 03:56:54 -06:00
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}
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/**
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* cik_sdma_rlc_stop - stop the compute async dma engines
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*
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* @rdev: radeon_device pointer
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*
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* Stop the compute async dma queues (CIK).
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*/
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static void cik_sdma_rlc_stop(struct radeon_device *rdev)
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{
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/* XXX todo */
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}
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2015-01-03 13:12:35 -07:00
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/**
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* cik_sdma_ctx_switch_enable - enable/disable sdma engine preemption
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*
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* @rdev: radeon_device pointer
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* @enable: enable/disable preemption.
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*
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* Halt or unhalt the async dma engines (CIK).
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*/
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2015-01-21 05:32:11 -07:00
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static void cik_sdma_ctx_switch_enable(struct radeon_device *rdev, bool enable)
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2015-01-03 13:12:35 -07:00
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{
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uint32_t reg_offset, value;
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int i;
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for (i = 0; i < 2; i++) {
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if (i == 0)
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reg_offset = SDMA0_REGISTER_OFFSET;
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else
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reg_offset = SDMA1_REGISTER_OFFSET;
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value = RREG32(SDMA0_CNTL + reg_offset);
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if (enable)
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value |= AUTO_CTXSW_ENABLE;
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else
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value &= ~AUTO_CTXSW_ENABLE;
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|
|
WREG32(SDMA0_CNTL + reg_offset, value);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-08-13 03:56:54 -06:00
|
|
|
/**
|
|
|
|
* cik_sdma_enable - stop the async dma engines
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
* @enable: enable/disable the DMA MEs.
|
|
|
|
*
|
|
|
|
* Halt or unhalt the async dma engines (CIK).
|
|
|
|
*/
|
|
|
|
void cik_sdma_enable(struct radeon_device *rdev, bool enable)
|
|
|
|
{
|
|
|
|
u32 me_cntl, reg_offset;
|
|
|
|
int i;
|
|
|
|
|
2014-03-12 13:26:34 -06:00
|
|
|
if (enable == false) {
|
|
|
|
cik_sdma_gfx_stop(rdev);
|
|
|
|
cik_sdma_rlc_stop(rdev);
|
|
|
|
}
|
|
|
|
|
2013-08-13 03:56:54 -06:00
|
|
|
for (i = 0; i < 2; i++) {
|
|
|
|
if (i == 0)
|
|
|
|
reg_offset = SDMA0_REGISTER_OFFSET;
|
|
|
|
else
|
|
|
|
reg_offset = SDMA1_REGISTER_OFFSET;
|
|
|
|
me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset);
|
|
|
|
if (enable)
|
|
|
|
me_cntl &= ~SDMA_HALT;
|
|
|
|
else
|
|
|
|
me_cntl |= SDMA_HALT;
|
|
|
|
WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl);
|
|
|
|
}
|
2015-01-03 13:12:35 -07:00
|
|
|
|
|
|
|
cik_sdma_ctx_switch_enable(rdev, enable);
|
2013-08-13 03:56:54 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* cik_sdma_gfx_resume - setup and start the async dma engines
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Set up the gfx DMA ring buffers and enable them (CIK).
|
|
|
|
* Returns 0 for success, error for failure.
|
|
|
|
*/
|
|
|
|
static int cik_sdma_gfx_resume(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
struct radeon_ring *ring;
|
|
|
|
u32 rb_cntl, ib_cntl;
|
|
|
|
u32 rb_bufsz;
|
|
|
|
u32 reg_offset, wb_offset;
|
|
|
|
int i, r;
|
|
|
|
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
|
|
if (i == 0) {
|
|
|
|
ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
|
|
|
|
reg_offset = SDMA0_REGISTER_OFFSET;
|
|
|
|
wb_offset = R600_WB_DMA_RPTR_OFFSET;
|
|
|
|
} else {
|
|
|
|
ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
|
|
|
|
reg_offset = SDMA1_REGISTER_OFFSET;
|
|
|
|
wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET;
|
|
|
|
}
|
|
|
|
|
|
|
|
WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
|
|
|
|
WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
|
|
|
|
|
|
|
|
/* Set ring buffer size in dwords */
|
2013-09-01 17:31:40 -06:00
|
|
|
rb_bufsz = order_base_2(ring->ring_size / 4);
|
2013-08-13 03:56:54 -06:00
|
|
|
rb_cntl = rb_bufsz << 1;
|
|
|
|
#ifdef __BIG_ENDIAN
|
|
|
|
rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE;
|
|
|
|
#endif
|
|
|
|
WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
|
|
|
|
|
|
|
|
/* Initialize the ring buffer's read and write pointers */
|
|
|
|
WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0);
|
|
|
|
WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0);
|
|
|
|
|
|
|
|
/* set the wb address whether it's enabled or not */
|
|
|
|
WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset,
|
|
|
|
upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
|
|
|
|
WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset,
|
|
|
|
((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
|
|
|
|
|
|
|
|
if (rdev->wb.enabled)
|
|
|
|
rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE;
|
|
|
|
|
|
|
|
WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8);
|
|
|
|
WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40);
|
|
|
|
|
|
|
|
ring->wptr = 0;
|
|
|
|
WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);
|
|
|
|
|
|
|
|
/* enable DMA RB */
|
|
|
|
WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE);
|
|
|
|
|
|
|
|
ib_cntl = SDMA_IB_ENABLE;
|
|
|
|
#ifdef __BIG_ENDIAN
|
|
|
|
ib_cntl |= SDMA_IB_SWAP_ENABLE;
|
|
|
|
#endif
|
|
|
|
/* enable DMA IBs */
|
|
|
|
WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl);
|
|
|
|
|
|
|
|
ring->ready = true;
|
|
|
|
|
|
|
|
r = radeon_ring_test(rdev, ring->idx, ring);
|
|
|
|
if (r) {
|
|
|
|
ring->ready = false;
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-01-27 09:26:33 -07:00
|
|
|
if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
|
|
|
|
(rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
|
|
|
|
radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
|
2013-08-13 03:56:54 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* cik_sdma_rlc_resume - setup and start the async dma engines
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Set up the compute DMA queues and enable them (CIK).
|
|
|
|
* Returns 0 for success, error for failure.
|
|
|
|
*/
|
|
|
|
static int cik_sdma_rlc_resume(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
/* XXX todo */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* cik_sdma_load_microcode - load the sDMA ME ucode
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Loads the sDMA0/1 ucode.
|
|
|
|
* Returns 0 for success, -EINVAL if the ucode is not available.
|
|
|
|
*/
|
|
|
|
static int cik_sdma_load_microcode(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (!rdev->sdma_fw)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/* halt the MEs */
|
|
|
|
cik_sdma_enable(rdev, false);
|
|
|
|
|
2014-06-25 17:32:36 -06:00
|
|
|
if (rdev->new_fw) {
|
|
|
|
const struct sdma_firmware_header_v1_0 *hdr =
|
|
|
|
(const struct sdma_firmware_header_v1_0 *)rdev->sdma_fw->data;
|
|
|
|
const __le32 *fw_data;
|
|
|
|
u32 fw_size;
|
|
|
|
|
|
|
|
radeon_ucode_print_sdma_hdr(&hdr->header);
|
|
|
|
|
|
|
|
/* sdma0 */
|
|
|
|
fw_data = (const __le32 *)
|
|
|
|
(rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
|
|
|
|
fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
|
|
|
|
WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
|
|
|
|
for (i = 0; i < fw_size; i++)
|
|
|
|
WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++));
|
|
|
|
WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
|
|
|
|
|
|
|
|
/* sdma1 */
|
|
|
|
fw_data = (const __le32 *)
|
|
|
|
(rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
|
|
|
|
fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
|
|
|
|
WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
|
|
|
|
for (i = 0; i < fw_size; i++)
|
|
|
|
WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++));
|
|
|
|
WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
|
|
|
|
} else {
|
|
|
|
const __be32 *fw_data;
|
|
|
|
|
|
|
|
/* sdma0 */
|
|
|
|
fw_data = (const __be32 *)rdev->sdma_fw->data;
|
|
|
|
WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
|
|
|
|
for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
|
|
|
|
WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++));
|
|
|
|
WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
|
|
|
|
|
|
|
|
/* sdma1 */
|
|
|
|
fw_data = (const __be32 *)rdev->sdma_fw->data;
|
|
|
|
WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
|
|
|
|
for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
|
|
|
|
WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++));
|
|
|
|
WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
|
|
|
|
}
|
2013-08-13 03:56:54 -06:00
|
|
|
|
|
|
|
WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
|
|
|
|
WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* cik_sdma_resume - setup and start the async dma engines
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Set up the DMA engines and enable them (CIK).
|
|
|
|
* Returns 0 for success, error for failure.
|
|
|
|
*/
|
|
|
|
int cik_sdma_resume(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
int r;
|
|
|
|
|
|
|
|
r = cik_sdma_load_microcode(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
|
|
|
/* unhalt the MEs */
|
|
|
|
cik_sdma_enable(rdev, true);
|
|
|
|
|
|
|
|
/* start the gfx rings and rlc compute queues */
|
|
|
|
r = cik_sdma_gfx_resume(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
r = cik_sdma_rlc_resume(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* cik_sdma_fini - tear down the async dma engines
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Stop the async dma engines and free the rings (CIK).
|
|
|
|
*/
|
|
|
|
void cik_sdma_fini(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
/* halt the MEs */
|
|
|
|
cik_sdma_enable(rdev, false);
|
|
|
|
radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
|
|
|
|
radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
|
|
|
|
/* XXX - compute dma queue tear down */
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* cik_copy_dma - copy pages using the DMA engine
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
* @src_offset: src GPU address
|
|
|
|
* @dst_offset: dst GPU address
|
|
|
|
* @num_gpu_pages: number of GPU pages to xfer
|
2014-09-04 12:01:53 -06:00
|
|
|
* @resv: reservation object to sync to
|
2013-08-13 03:56:54 -06:00
|
|
|
*
|
|
|
|
* Copy GPU paging using the DMA engine (CIK).
|
|
|
|
* Used by the radeon ttm implementation to move pages if
|
|
|
|
* registered as the asic copy callback.
|
|
|
|
*/
|
2014-09-04 12:01:53 -06:00
|
|
|
struct radeon_fence *cik_copy_dma(struct radeon_device *rdev,
|
|
|
|
uint64_t src_offset, uint64_t dst_offset,
|
|
|
|
unsigned num_gpu_pages,
|
|
|
|
struct reservation_object *resv)
|
2013-08-13 03:56:54 -06:00
|
|
|
{
|
2014-09-04 12:01:53 -06:00
|
|
|
struct radeon_fence *fence;
|
2014-11-19 06:01:22 -07:00
|
|
|
struct radeon_sync sync;
|
2013-08-13 03:56:54 -06:00
|
|
|
int ring_index = rdev->asic->copy.dma_ring_index;
|
|
|
|
struct radeon_ring *ring = &rdev->ring[ring_index];
|
|
|
|
u32 size_in_bytes, cur_size_in_bytes;
|
|
|
|
int i, num_loops;
|
|
|
|
int r = 0;
|
|
|
|
|
2014-11-19 06:01:22 -07:00
|
|
|
radeon_sync_create(&sync);
|
2013-08-13 03:56:54 -06:00
|
|
|
|
|
|
|
size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
|
|
|
|
num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
|
|
|
|
r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("radeon: moving bo (%d).\n", r);
|
2014-11-19 06:01:22 -07:00
|
|
|
radeon_sync_free(rdev, &sync, NULL);
|
2014-09-04 12:01:53 -06:00
|
|
|
return ERR_PTR(r);
|
2013-08-13 03:56:54 -06:00
|
|
|
}
|
|
|
|
|
2014-11-19 06:01:22 -07:00
|
|
|
radeon_sync_resv(rdev, &sync, resv, false);
|
|
|
|
radeon_sync_rings(rdev, &sync, ring->idx);
|
2013-08-13 03:56:54 -06:00
|
|
|
|
|
|
|
for (i = 0; i < num_loops; i++) {
|
|
|
|
cur_size_in_bytes = size_in_bytes;
|
|
|
|
if (cur_size_in_bytes > 0x1fffff)
|
|
|
|
cur_size_in_bytes = 0x1fffff;
|
|
|
|
size_in_bytes -= cur_size_in_bytes;
|
|
|
|
radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0));
|
|
|
|
radeon_ring_write(ring, cur_size_in_bytes);
|
|
|
|
radeon_ring_write(ring, 0); /* src/dst endian swap */
|
2014-06-03 12:51:46 -06:00
|
|
|
radeon_ring_write(ring, lower_32_bits(src_offset));
|
|
|
|
radeon_ring_write(ring, upper_32_bits(src_offset));
|
|
|
|
radeon_ring_write(ring, lower_32_bits(dst_offset));
|
|
|
|
radeon_ring_write(ring, upper_32_bits(dst_offset));
|
2013-08-13 03:56:54 -06:00
|
|
|
src_offset += cur_size_in_bytes;
|
|
|
|
dst_offset += cur_size_in_bytes;
|
|
|
|
}
|
|
|
|
|
2014-09-04 12:01:53 -06:00
|
|
|
r = radeon_fence_emit(rdev, &fence, ring->idx);
|
2013-08-13 03:56:54 -06:00
|
|
|
if (r) {
|
|
|
|
radeon_ring_unlock_undo(rdev, ring);
|
2014-11-19 06:01:22 -07:00
|
|
|
radeon_sync_free(rdev, &sync, NULL);
|
2014-09-04 12:01:53 -06:00
|
|
|
return ERR_PTR(r);
|
2013-08-13 03:56:54 -06:00
|
|
|
}
|
|
|
|
|
2014-08-18 02:34:55 -06:00
|
|
|
radeon_ring_unlock_commit(rdev, ring, false);
|
2014-11-19 06:01:22 -07:00
|
|
|
radeon_sync_free(rdev, &sync, fence);
|
2013-08-13 03:56:54 -06:00
|
|
|
|
2014-09-04 12:01:53 -06:00
|
|
|
return fence;
|
2013-08-13 03:56:54 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* cik_sdma_ring_test - simple async dma engine test
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
* @ring: radeon_ring structure holding ring information
|
|
|
|
*
|
|
|
|
* Test the DMA engine by writing using it to write an
|
|
|
|
* value to memory. (CIK).
|
|
|
|
* Returns 0 for success, error for failure.
|
|
|
|
*/
|
|
|
|
int cik_sdma_ring_test(struct radeon_device *rdev,
|
|
|
|
struct radeon_ring *ring)
|
|
|
|
{
|
|
|
|
unsigned i;
|
|
|
|
int r;
|
2014-10-13 11:20:02 -06:00
|
|
|
unsigned index;
|
2013-08-13 03:56:54 -06:00
|
|
|
u32 tmp;
|
2014-10-13 11:20:02 -06:00
|
|
|
u64 gpu_addr;
|
2013-08-13 03:56:54 -06:00
|
|
|
|
2014-10-13 11:20:02 -06:00
|
|
|
if (ring->idx == R600_RING_TYPE_DMA_INDEX)
|
|
|
|
index = R600_WB_DMA_RING_TEST_OFFSET;
|
|
|
|
else
|
|
|
|
index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
|
|
|
|
|
|
|
|
gpu_addr = rdev->wb.gpu_addr + index;
|
2013-08-13 03:56:54 -06:00
|
|
|
|
|
|
|
tmp = 0xCAFEDEAD;
|
2014-10-13 11:20:02 -06:00
|
|
|
rdev->wb.wb[index/4] = cpu_to_le32(tmp);
|
2013-08-13 03:56:54 -06:00
|
|
|
|
2014-04-22 06:17:18 -06:00
|
|
|
r = radeon_ring_lock(rdev, ring, 5);
|
2013-08-13 03:56:54 -06:00
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
|
2014-10-13 11:20:02 -06:00
|
|
|
radeon_ring_write(ring, lower_32_bits(gpu_addr));
|
|
|
|
radeon_ring_write(ring, upper_32_bits(gpu_addr));
|
2013-08-13 03:56:54 -06:00
|
|
|
radeon_ring_write(ring, 1); /* number of DWs to follow */
|
|
|
|
radeon_ring_write(ring, 0xDEADBEEF);
|
2014-08-18 02:34:55 -06:00
|
|
|
radeon_ring_unlock_commit(rdev, ring, false);
|
2013-08-13 03:56:54 -06:00
|
|
|
|
|
|
|
for (i = 0; i < rdev->usec_timeout; i++) {
|
2014-10-13 11:20:02 -06:00
|
|
|
tmp = le32_to_cpu(rdev->wb.wb[index/4]);
|
2013-08-13 03:56:54 -06:00
|
|
|
if (tmp == 0xDEADBEEF)
|
|
|
|
break;
|
|
|
|
DRM_UDELAY(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i < rdev->usec_timeout) {
|
|
|
|
DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
|
|
|
|
} else {
|
|
|
|
DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
|
|
|
|
ring->idx, tmp);
|
|
|
|
r = -EINVAL;
|
|
|
|
}
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* cik_sdma_ib_test - test an IB on the DMA engine
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
* @ring: radeon_ring structure holding ring information
|
|
|
|
*
|
|
|
|
* Test a simple IB in the DMA ring (CIK).
|
|
|
|
* Returns 0 on success, error on failure.
|
|
|
|
*/
|
|
|
|
int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
|
|
|
|
{
|
|
|
|
struct radeon_ib ib;
|
|
|
|
unsigned i;
|
2014-11-03 09:27:17 -07:00
|
|
|
unsigned index;
|
2013-08-13 03:56:54 -06:00
|
|
|
int r;
|
|
|
|
u32 tmp = 0;
|
2014-11-03 09:27:17 -07:00
|
|
|
u64 gpu_addr;
|
2013-08-13 03:56:54 -06:00
|
|
|
|
2014-11-03 09:27:17 -07:00
|
|
|
if (ring->idx == R600_RING_TYPE_DMA_INDEX)
|
|
|
|
index = R600_WB_DMA_RING_TEST_OFFSET;
|
|
|
|
else
|
|
|
|
index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
|
|
|
|
|
|
|
|
gpu_addr = rdev->wb.gpu_addr + index;
|
2013-08-13 03:56:54 -06:00
|
|
|
|
|
|
|
tmp = 0xCAFEDEAD;
|
2014-11-03 09:27:17 -07:00
|
|
|
rdev->wb.wb[index/4] = cpu_to_le32(tmp);
|
2013-08-13 03:56:54 -06:00
|
|
|
|
|
|
|
r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("radeon: failed to get ib (%d).\n", r);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
|
2014-11-03 09:27:17 -07:00
|
|
|
ib.ptr[1] = lower_32_bits(gpu_addr);
|
|
|
|
ib.ptr[2] = upper_32_bits(gpu_addr);
|
2013-08-13 03:56:54 -06:00
|
|
|
ib.ptr[3] = 1;
|
|
|
|
ib.ptr[4] = 0xDEADBEEF;
|
|
|
|
ib.length_dw = 5;
|
|
|
|
|
2014-08-18 02:34:55 -06:00
|
|
|
r = radeon_ib_schedule(rdev, &ib, NULL, false);
|
2013-08-13 03:56:54 -06:00
|
|
|
if (r) {
|
|
|
|
radeon_ib_free(rdev, &ib);
|
|
|
|
DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
|
|
|
|
return r;
|
|
|
|
}
|
2016-02-07 14:51:12 -07:00
|
|
|
r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
|
|
|
|
RADEON_USEC_IB_TEST_TIMEOUT));
|
|
|
|
if (r < 0) {
|
2013-08-13 03:56:54 -06:00
|
|
|
DRM_ERROR("radeon: fence wait failed (%d).\n", r);
|
|
|
|
return r;
|
2016-02-07 14:51:12 -07:00
|
|
|
} else if (r == 0) {
|
|
|
|
DRM_ERROR("radeon: fence wait timed out.\n");
|
|
|
|
return -ETIMEDOUT;
|
2013-08-13 03:56:54 -06:00
|
|
|
}
|
2016-02-07 14:51:12 -07:00
|
|
|
r = 0;
|
2013-08-13 03:56:54 -06:00
|
|
|
for (i = 0; i < rdev->usec_timeout; i++) {
|
2014-11-03 09:27:17 -07:00
|
|
|
tmp = le32_to_cpu(rdev->wb.wb[index/4]);
|
2013-08-13 03:56:54 -06:00
|
|
|
if (tmp == 0xDEADBEEF)
|
|
|
|
break;
|
|
|
|
DRM_UDELAY(1);
|
|
|
|
}
|
|
|
|
if (i < rdev->usec_timeout) {
|
|
|
|
DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
|
|
|
|
} else {
|
|
|
|
DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
|
|
|
|
r = -EINVAL;
|
|
|
|
}
|
|
|
|
radeon_ib_free(rdev, &ib);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* cik_sdma_is_lockup - Check if the DMA engine is locked up
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
* @ring: radeon_ring structure holding ring information
|
|
|
|
*
|
|
|
|
* Check if the async DMA engine is locked up (CIK).
|
|
|
|
* Returns true if the engine appears to be locked up, false if not.
|
|
|
|
*/
|
|
|
|
bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
|
|
|
|
{
|
|
|
|
u32 reset_mask = cik_gpu_check_soft_reset(rdev);
|
|
|
|
u32 mask;
|
|
|
|
|
|
|
|
if (ring->idx == R600_RING_TYPE_DMA_INDEX)
|
|
|
|
mask = RADEON_RESET_DMA;
|
|
|
|
else
|
|
|
|
mask = RADEON_RESET_DMA1;
|
|
|
|
|
|
|
|
if (!(reset_mask & mask)) {
|
2014-02-18 06:52:33 -07:00
|
|
|
radeon_ring_lockup_update(rdev, ring);
|
2013-08-13 03:56:54 -06:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return radeon_ring_test_lockup(rdev, ring);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2014-07-30 13:05:17 -06:00
|
|
|
* cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
* @ib: indirect buffer to fill with commands
|
|
|
|
* @pe: addr of the page entry
|
|
|
|
* @src: src addr to copy from
|
|
|
|
* @count: number of page entries to update
|
|
|
|
*
|
|
|
|
* Update PTEs by copying them from the GART using sDMA (CIK).
|
|
|
|
*/
|
|
|
|
void cik_sdma_vm_copy_pages(struct radeon_device *rdev,
|
|
|
|
struct radeon_ib *ib,
|
|
|
|
uint64_t pe, uint64_t src,
|
|
|
|
unsigned count)
|
|
|
|
{
|
|
|
|
while (count) {
|
|
|
|
unsigned bytes = count * 8;
|
|
|
|
if (bytes > 0x1FFFF8)
|
|
|
|
bytes = 0x1FFFF8;
|
|
|
|
|
|
|
|
ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
|
|
|
|
SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
|
|
|
|
ib->ptr[ib->length_dw++] = bytes;
|
|
|
|
ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
|
|
|
|
ib->ptr[ib->length_dw++] = lower_32_bits(src);
|
|
|
|
ib->ptr[ib->length_dw++] = upper_32_bits(src);
|
|
|
|
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
|
|
|
|
ib->ptr[ib->length_dw++] = upper_32_bits(pe);
|
|
|
|
|
|
|
|
pe += bytes;
|
|
|
|
src += bytes;
|
|
|
|
count -= bytes / 8;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* cik_sdma_vm_write_pages - update PTEs by writing them manually
|
2013-08-13 03:56:54 -06:00
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
* @ib: indirect buffer to fill with commands
|
|
|
|
* @pe: addr of the page entry
|
|
|
|
* @addr: dst addr to write into pe
|
|
|
|
* @count: number of page entries to update
|
|
|
|
* @incr: increase next addr by incr bytes
|
|
|
|
* @flags: access flags
|
|
|
|
*
|
2014-07-30 13:05:17 -06:00
|
|
|
* Update PTEs by writing them manually using sDMA (CIK).
|
2013-08-13 03:56:54 -06:00
|
|
|
*/
|
2014-07-30 13:05:17 -06:00
|
|
|
void cik_sdma_vm_write_pages(struct radeon_device *rdev,
|
|
|
|
struct radeon_ib *ib,
|
|
|
|
uint64_t pe,
|
|
|
|
uint64_t addr, unsigned count,
|
|
|
|
uint32_t incr, uint32_t flags)
|
2013-08-13 03:56:54 -06:00
|
|
|
{
|
|
|
|
uint64_t value;
|
|
|
|
unsigned ndw;
|
|
|
|
|
2014-07-30 13:05:17 -06:00
|
|
|
while (count) {
|
|
|
|
ndw = count * 2;
|
|
|
|
if (ndw > 0xFFFFE)
|
|
|
|
ndw = 0xFFFFE;
|
|
|
|
|
|
|
|
/* for non-physically contiguous pages (system) */
|
|
|
|
ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
|
|
|
|
SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
|
|
|
|
ib->ptr[ib->length_dw++] = pe;
|
|
|
|
ib->ptr[ib->length_dw++] = upper_32_bits(pe);
|
|
|
|
ib->ptr[ib->length_dw++] = ndw;
|
|
|
|
for (; ndw > 0; ndw -= 2, --count, pe += 8) {
|
|
|
|
if (flags & R600_PTE_SYSTEM) {
|
2013-10-30 09:51:09 -06:00
|
|
|
value = radeon_vm_map_gart(rdev, addr);
|
2014-07-30 13:05:17 -06:00
|
|
|
} else if (flags & R600_PTE_VALID) {
|
2013-08-13 03:56:54 -06:00
|
|
|
value = addr;
|
2014-07-30 13:05:17 -06:00
|
|
|
} else {
|
2013-08-13 03:56:54 -06:00
|
|
|
value = 0;
|
2014-07-30 13:05:17 -06:00
|
|
|
}
|
|
|
|
addr += incr;
|
|
|
|
value |= flags;
|
|
|
|
ib->ptr[ib->length_dw++] = value;
|
2013-08-13 03:56:54 -06:00
|
|
|
ib->ptr[ib->length_dw++] = upper_32_bits(value);
|
|
|
|
}
|
|
|
|
}
|
2014-07-30 13:05:17 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* cik_sdma_vm_set_pages - update the page tables using sDMA
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
* @ib: indirect buffer to fill with commands
|
|
|
|
* @pe: addr of the page entry
|
|
|
|
* @addr: dst addr to write into pe
|
|
|
|
* @count: number of page entries to update
|
|
|
|
* @incr: increase next addr by incr bytes
|
|
|
|
* @flags: access flags
|
|
|
|
*
|
|
|
|
* Update the page tables using sDMA (CIK).
|
|
|
|
*/
|
|
|
|
void cik_sdma_vm_set_pages(struct radeon_device *rdev,
|
|
|
|
struct radeon_ib *ib,
|
|
|
|
uint64_t pe,
|
|
|
|
uint64_t addr, unsigned count,
|
|
|
|
uint32_t incr, uint32_t flags)
|
|
|
|
{
|
|
|
|
uint64_t value;
|
|
|
|
unsigned ndw;
|
|
|
|
|
|
|
|
while (count) {
|
|
|
|
ndw = count;
|
|
|
|
if (ndw > 0x7FFFF)
|
|
|
|
ndw = 0x7FFFF;
|
|
|
|
|
|
|
|
if (flags & R600_PTE_VALID)
|
|
|
|
value = addr;
|
|
|
|
else
|
|
|
|
value = 0;
|
|
|
|
|
|
|
|
/* for physically contiguous pages (vram) */
|
|
|
|
ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
|
|
|
|
ib->ptr[ib->length_dw++] = pe; /* dst addr */
|
|
|
|
ib->ptr[ib->length_dw++] = upper_32_bits(pe);
|
|
|
|
ib->ptr[ib->length_dw++] = flags; /* mask */
|
|
|
|
ib->ptr[ib->length_dw++] = 0;
|
|
|
|
ib->ptr[ib->length_dw++] = value; /* value */
|
|
|
|
ib->ptr[ib->length_dw++] = upper_32_bits(value);
|
|
|
|
ib->ptr[ib->length_dw++] = incr; /* increment size */
|
|
|
|
ib->ptr[ib->length_dw++] = 0;
|
|
|
|
ib->ptr[ib->length_dw++] = ndw; /* number of entries */
|
|
|
|
|
|
|
|
pe += ndw * 8;
|
|
|
|
addr += ndw * incr;
|
|
|
|
count -= ndw;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* cik_sdma_vm_pad_ib - pad the IB to the required number of dw
|
|
|
|
*
|
|
|
|
* @ib: indirect buffer to fill with padding
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
void cik_sdma_vm_pad_ib(struct radeon_ib *ib)
|
|
|
|
{
|
2013-08-13 03:56:54 -06:00
|
|
|
while (ib->length_dw & 0x7)
|
|
|
|
ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* cik_dma_vm_flush - cik vm flush using sDMA
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Update the page table base and flush the VM TLB
|
|
|
|
* using sDMA (CIK).
|
|
|
|
*/
|
2014-11-19 06:01:19 -07:00
|
|
|
void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
|
|
|
|
unsigned vm_id, uint64_t pd_addr)
|
2013-08-13 03:56:54 -06:00
|
|
|
{
|
2015-01-05 17:59:47 -07:00
|
|
|
u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
|
|
|
|
SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
|
|
|
|
|
2013-08-13 03:56:54 -06:00
|
|
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radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
|
2014-11-19 06:01:19 -07:00
|
|
|
if (vm_id < 8) {
|
|
|
|
radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);
|
2013-08-13 03:56:54 -06:00
|
|
|
} else {
|
2014-11-19 06:01:19 -07:00
|
|
|
radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);
|
2013-08-13 03:56:54 -06:00
|
|
|
}
|
2014-11-19 06:01:19 -07:00
|
|
|
radeon_ring_write(ring, pd_addr >> 12);
|
2013-08-13 03:56:54 -06:00
|
|
|
|
|
|
|
/* update SH_MEM_* regs */
|
|
|
|
radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
|
|
|
|
radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
|
2014-11-19 06:01:19 -07:00
|
|
|
radeon_ring_write(ring, VMID(vm_id));
|
2013-08-13 03:56:54 -06:00
|
|
|
|
|
|
|
radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
|
|
|
|
radeon_ring_write(ring, SH_MEM_BASES >> 2);
|
|
|
|
radeon_ring_write(ring, 0);
|
|
|
|
|
|
|
|
radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
|
|
|
|
radeon_ring_write(ring, SH_MEM_CONFIG >> 2);
|
|
|
|
radeon_ring_write(ring, 0);
|
|
|
|
|
|
|
|
radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
|
|
|
|
radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2);
|
|
|
|
radeon_ring_write(ring, 1);
|
|
|
|
|
|
|
|
radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
|
|
|
|
radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2);
|
|
|
|
radeon_ring_write(ring, 0);
|
|
|
|
|
|
|
|
radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
|
|
|
|
radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
|
|
|
|
radeon_ring_write(ring, VMID(0));
|
|
|
|
|
|
|
|
/* flush HDP */
|
2014-11-19 06:01:19 -07:00
|
|
|
cik_sdma_hdp_flush_ring_emit(rdev, ring->idx);
|
2013-08-13 03:56:54 -06:00
|
|
|
|
|
|
|
/* flush TLB */
|
|
|
|
radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
|
|
|
|
radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
|
2014-11-19 06:01:19 -07:00
|
|
|
radeon_ring_write(ring, 1 << vm_id);
|
2015-01-05 17:59:47 -07:00
|
|
|
|
|
|
|
radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
|
|
|
|
radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
|
|
|
|
radeon_ring_write(ring, 0);
|
|
|
|
radeon_ring_write(ring, 0); /* reference */
|
|
|
|
radeon_ring_write(ring, 0); /* mask */
|
|
|
|
radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
|
2013-08-13 03:56:54 -06:00
|
|
|
}
|
|
|
|
|