2006-03-29 01:21:00 -07:00
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/*
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2007-07-11 12:04:50 -06:00
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* linux/drivers/mmc/host/omap.c
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2006-03-29 01:21:00 -07:00
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*
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* Copyright (C) 2004 Nokia Corporation
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2011-12-29 15:09:01 -07:00
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* Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
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2006-03-29 01:21:00 -07:00
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* Misc hacks here and there by Tony Lindgren <tony@atomide.com>
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* Other hacks (DMA, SD, etc) by David Brownell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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2012-04-21 15:35:42 -06:00
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#include <linux/dmaengine.h>
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2006-03-29 01:21:00 -07:00
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/timer.h>
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2012-04-21 15:35:42 -06:00
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#include <linux/omap-dma.h>
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2006-03-29 01:21:00 -07:00
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#include <linux/mmc/host.h>
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#include <linux/mmc/card.h>
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#include <linux/clk.h>
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2007-10-22 13:19:53 -06:00
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#include <linux/scatterlist.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2006-03-29 01:21:00 -07:00
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2009-10-20 10:40:47 -06:00
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#include <plat/mmc.h>
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#include <plat/dma.h>
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2006-03-29 01:21:00 -07:00
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2006-11-11 15:38:36 -07:00
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#define OMAP_MMC_REG_CMD 0x00
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2010-05-26 15:41:49 -06:00
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#define OMAP_MMC_REG_ARGL 0x01
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#define OMAP_MMC_REG_ARGH 0x02
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#define OMAP_MMC_REG_CON 0x03
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#define OMAP_MMC_REG_STAT 0x04
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#define OMAP_MMC_REG_IE 0x05
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#define OMAP_MMC_REG_CTO 0x06
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#define OMAP_MMC_REG_DTO 0x07
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#define OMAP_MMC_REG_DATA 0x08
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#define OMAP_MMC_REG_BLEN 0x09
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#define OMAP_MMC_REG_NBLK 0x0a
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#define OMAP_MMC_REG_BUF 0x0b
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#define OMAP_MMC_REG_SDIO 0x0d
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#define OMAP_MMC_REG_REV 0x0f
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#define OMAP_MMC_REG_RSP0 0x10
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#define OMAP_MMC_REG_RSP1 0x11
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#define OMAP_MMC_REG_RSP2 0x12
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#define OMAP_MMC_REG_RSP3 0x13
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#define OMAP_MMC_REG_RSP4 0x14
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#define OMAP_MMC_REG_RSP5 0x15
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#define OMAP_MMC_REG_RSP6 0x16
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#define OMAP_MMC_REG_RSP7 0x17
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#define OMAP_MMC_REG_IOSR 0x18
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#define OMAP_MMC_REG_SYSC 0x19
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#define OMAP_MMC_REG_SYSS 0x1a
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2006-11-11 15:38:36 -07:00
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#define OMAP_MMC_STAT_CARD_ERR (1 << 14)
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#define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
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#define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
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#define OMAP_MMC_STAT_A_EMPTY (1 << 11)
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#define OMAP_MMC_STAT_A_FULL (1 << 10)
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#define OMAP_MMC_STAT_CMD_CRC (1 << 8)
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#define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
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#define OMAP_MMC_STAT_DATA_CRC (1 << 6)
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#define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
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#define OMAP_MMC_STAT_END_BUSY (1 << 4)
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#define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
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#define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
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#define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
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2010-05-26 15:41:49 -06:00
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#define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
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#define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
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#define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
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2006-11-11 15:38:36 -07:00
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/*
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* Command types
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*/
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#define OMAP_MMC_CMDTYPE_BC 0
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#define OMAP_MMC_CMDTYPE_BCR 1
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#define OMAP_MMC_CMDTYPE_AC 2
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#define OMAP_MMC_CMDTYPE_ADTC 3
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2006-03-29 01:21:00 -07:00
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#define DRIVER_NAME "mmci-omap"
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/* Specifies how often in millisecs to poll for card status changes
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* when the cover switch is open */
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2008-03-26 14:09:42 -06:00
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#define OMAP_MMC_COVER_POLL_DELAY 500
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2006-03-29 01:21:00 -07:00
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2008-03-26 14:08:57 -06:00
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struct mmc_omap_host;
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struct mmc_omap_slot {
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int id;
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unsigned int vdd;
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u16 saved_con;
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u16 bus_mode;
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unsigned int fclk_freq;
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2008-03-26 14:09:42 -06:00
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struct tasklet_struct cover_tasklet;
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struct timer_list cover_timer;
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2008-03-26 14:09:08 -06:00
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unsigned cover_open;
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2008-03-26 14:08:57 -06:00
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struct mmc_request *mrq;
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struct mmc_omap_host *host;
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struct mmc_host *mmc;
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struct omap_mmc_slot_data *pdata;
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};
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2006-03-29 01:21:00 -07:00
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struct mmc_omap_host {
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int initialized;
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int suspended;
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struct mmc_request * mrq;
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struct mmc_command * cmd;
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struct mmc_data * data;
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struct mmc_host * mmc;
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struct device * dev;
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unsigned char id; /* 16xx chips have 2 MMC blocks */
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struct clk * iclk;
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struct clk * fclk;
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2012-04-21 15:35:42 -06:00
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struct dma_chan *dma_rx;
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u32 dma_rx_burst;
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struct dma_chan *dma_tx;
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u32 dma_tx_burst;
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2006-11-11 15:36:01 -07:00
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struct resource *mem_res;
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void __iomem *virt_base;
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unsigned int phys_base;
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2006-03-29 01:21:00 -07:00
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int irq;
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unsigned char bus_mode;
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2010-05-26 15:41:49 -06:00
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unsigned int reg_shift;
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2006-03-29 01:21:00 -07:00
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2008-03-26 14:09:48 -06:00
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struct work_struct cmd_abort_work;
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unsigned abort:1;
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struct timer_list cmd_abort_timer;
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2008-03-26 14:09:29 -06:00
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2008-03-26 14:09:58 -06:00
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struct work_struct slot_release_work;
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struct mmc_omap_slot *next_slot;
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struct work_struct send_stop_work;
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struct mmc_data *stop_data;
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2006-03-29 01:21:00 -07:00
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unsigned int sg_len;
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int sg_idx;
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u16 * buffer;
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u32 buffer_bytes_left;
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u32 total_bytes_left;
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unsigned use_dma:1;
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unsigned brs_received:1, dma_done:1;
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unsigned dma_in_use:1;
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2012-04-21 15:35:42 -06:00
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spinlock_t dma_lock;
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2006-03-29 01:21:00 -07:00
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2008-03-26 14:08:57 -06:00
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struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
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struct mmc_omap_slot *current_slot;
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spinlock_t slot_lock;
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wait_queue_head_t slot_wq;
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int nr_slots;
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2008-03-26 14:09:52 -06:00
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struct timer_list clk_timer;
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spinlock_t clk_lock; /* for changing enabled state */
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unsigned int fclk_enabled:1;
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2012-05-08 05:35:33 -06:00
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struct workqueue_struct *mmc_omap_wq;
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2008-03-26 14:09:52 -06:00
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2008-03-26 14:08:57 -06:00
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struct omap_mmc_platform_data *pdata;
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2006-03-29 01:21:00 -07:00
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};
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2010-12-24 08:00:17 -07:00
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2008-09-05 08:13:24 -06:00
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static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
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2008-03-26 14:09:52 -06:00
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{
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unsigned long tick_ns;
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if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
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tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq;
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ndelay(8 * tick_ns);
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}
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}
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2008-09-05 08:13:24 -06:00
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static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
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2008-03-26 14:09:52 -06:00
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{
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unsigned long flags;
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spin_lock_irqsave(&host->clk_lock, flags);
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if (host->fclk_enabled != enable) {
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host->fclk_enabled = enable;
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if (enable)
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clk_enable(host->fclk);
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else
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clk_disable(host->fclk);
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}
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spin_unlock_irqrestore(&host->clk_lock, flags);
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}
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2008-03-26 14:08:57 -06:00
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static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
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{
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struct mmc_omap_host *host = slot->host;
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unsigned long flags;
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if (claimed)
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goto no_claim;
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spin_lock_irqsave(&host->slot_lock, flags);
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while (host->mmc != NULL) {
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spin_unlock_irqrestore(&host->slot_lock, flags);
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wait_event(host->slot_wq, host->mmc == NULL);
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spin_lock_irqsave(&host->slot_lock, flags);
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}
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host->mmc = slot->mmc;
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spin_unlock_irqrestore(&host->slot_lock, flags);
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no_claim:
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2008-03-26 14:09:52 -06:00
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del_timer(&host->clk_timer);
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if (host->current_slot != slot || !claimed)
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mmc_omap_fclk_offdelay(host->current_slot);
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2008-03-26 14:08:57 -06:00
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if (host->current_slot != slot) {
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2008-03-26 14:09:52 -06:00
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OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
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2008-03-26 14:08:57 -06:00
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if (host->pdata->switch_slot != NULL)
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host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
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host->current_slot = slot;
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}
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2008-03-26 14:09:52 -06:00
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if (claimed) {
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mmc_omap_fclk_enable(host, 1);
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/* Doing the dummy read here seems to work around some bug
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* at least in OMAP24xx silicon where the command would not
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* start after writing the CMD register. Sigh. */
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OMAP_MMC_READ(host, CON);
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2008-03-26 14:08:57 -06:00
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2008-03-26 14:09:52 -06:00
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OMAP_MMC_WRITE(host, CON, slot->saved_con);
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} else
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mmc_omap_fclk_enable(host, 0);
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2008-03-26 14:08:57 -06:00
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}
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static void mmc_omap_start_request(struct mmc_omap_host *host,
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struct mmc_request *req);
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2008-03-26 14:09:58 -06:00
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static void mmc_omap_slot_release_work(struct work_struct *work)
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{
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struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
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slot_release_work);
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struct mmc_omap_slot *next_slot = host->next_slot;
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struct mmc_request *rq;
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host->next_slot = NULL;
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mmc_omap_select_slot(next_slot, 1);
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rq = next_slot->mrq;
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next_slot->mrq = NULL;
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mmc_omap_start_request(host, rq);
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}
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2008-03-26 14:09:52 -06:00
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static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
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2008-03-26 14:08:57 -06:00
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{
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struct mmc_omap_host *host = slot->host;
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unsigned long flags;
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int i;
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BUG_ON(slot == NULL || host->mmc == NULL);
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2008-03-26 14:09:52 -06:00
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if (clk_enabled)
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|
|
|
/* Keeps clock running for at least 8 cycles on valid freq */
|
|
|
|
mod_timer(&host->clk_timer, jiffies + HZ/10);
|
|
|
|
else {
|
|
|
|
del_timer(&host->clk_timer);
|
|
|
|
mmc_omap_fclk_offdelay(slot);
|
|
|
|
mmc_omap_fclk_enable(host, 0);
|
|
|
|
}
|
2008-03-26 14:08:57 -06:00
|
|
|
|
|
|
|
spin_lock_irqsave(&host->slot_lock, flags);
|
|
|
|
/* Check for any pending requests */
|
|
|
|
for (i = 0; i < host->nr_slots; i++) {
|
|
|
|
struct mmc_omap_slot *new_slot;
|
|
|
|
|
|
|
|
if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
|
|
|
|
continue;
|
|
|
|
|
2008-03-26 14:09:58 -06:00
|
|
|
BUG_ON(host->next_slot != NULL);
|
2008-03-26 14:08:57 -06:00
|
|
|
new_slot = host->slots[i];
|
|
|
|
/* The current slot should not have a request in queue */
|
|
|
|
BUG_ON(new_slot == host->current_slot);
|
|
|
|
|
2008-03-26 14:09:58 -06:00
|
|
|
host->next_slot = new_slot;
|
2008-03-26 14:08:57 -06:00
|
|
|
host->mmc = new_slot->mmc;
|
|
|
|
spin_unlock_irqrestore(&host->slot_lock, flags);
|
2012-05-08 05:35:33 -06:00
|
|
|
queue_work(host->mmc_omap_wq, &host->slot_release_work);
|
2008-03-26 14:08:57 -06:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
host->mmc = NULL;
|
|
|
|
wake_up(&host->slot_wq);
|
|
|
|
spin_unlock_irqrestore(&host->slot_lock, flags);
|
|
|
|
}
|
|
|
|
|
2008-03-26 14:09:08 -06:00
|
|
|
static inline
|
|
|
|
int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
|
|
|
|
{
|
2008-03-26 14:09:38 -06:00
|
|
|
if (slot->pdata->get_cover_state)
|
|
|
|
return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
|
|
|
|
slot->id);
|
|
|
|
return 0;
|
2008-03-26 14:09:08 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static ssize_t
|
|
|
|
mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
|
|
|
|
char *buf)
|
|
|
|
{
|
|
|
|
struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
|
|
|
|
struct mmc_omap_slot *slot = mmc_priv(mmc);
|
|
|
|
|
|
|
|
return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
|
|
|
|
"closed");
|
|
|
|
}
|
|
|
|
|
|
|
|
static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
|
|
|
|
|
2008-03-26 14:08:57 -06:00
|
|
|
static ssize_t
|
|
|
|
mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
|
|
|
|
char *buf)
|
|
|
|
{
|
|
|
|
struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
|
|
|
|
struct mmc_omap_slot *slot = mmc_priv(mmc);
|
|
|
|
|
|
|
|
return sprintf(buf, "%s\n", slot->pdata->name);
|
|
|
|
}
|
|
|
|
|
|
|
|
static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
|
|
|
|
|
2006-03-29 01:21:00 -07:00
|
|
|
static void
|
|
|
|
mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
|
|
|
|
{
|
|
|
|
u32 cmdreg;
|
|
|
|
u32 resptype;
|
|
|
|
u32 cmdtype;
|
|
|
|
|
|
|
|
host->cmd = cmd;
|
|
|
|
|
|
|
|
resptype = 0;
|
|
|
|
cmdtype = 0;
|
|
|
|
|
|
|
|
/* Our hardware needs to know exact type */
|
2007-01-14 22:38:15 -07:00
|
|
|
switch (mmc_resp_type(cmd)) {
|
|
|
|
case MMC_RSP_NONE:
|
|
|
|
break;
|
|
|
|
case MMC_RSP_R1:
|
|
|
|
case MMC_RSP_R1B:
|
2007-01-04 08:04:47 -07:00
|
|
|
/* resp 1, 1b, 6, 7 */
|
2006-03-29 01:21:00 -07:00
|
|
|
resptype = 1;
|
|
|
|
break;
|
2007-01-14 22:38:15 -07:00
|
|
|
case MMC_RSP_R2:
|
2006-03-29 01:21:00 -07:00
|
|
|
resptype = 2;
|
|
|
|
break;
|
2007-01-14 22:38:15 -07:00
|
|
|
case MMC_RSP_R3:
|
2006-03-29 01:21:00 -07:00
|
|
|
resptype = 3;
|
|
|
|
break;
|
|
|
|
default:
|
2007-01-14 22:38:15 -07:00
|
|
|
dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
|
2006-03-29 01:21:00 -07:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
|
|
|
|
cmdtype = OMAP_MMC_CMDTYPE_ADTC;
|
|
|
|
} else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
|
|
|
|
cmdtype = OMAP_MMC_CMDTYPE_BC;
|
|
|
|
} else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
|
|
|
|
cmdtype = OMAP_MMC_CMDTYPE_BCR;
|
|
|
|
} else {
|
|
|
|
cmdtype = OMAP_MMC_CMDTYPE_AC;
|
|
|
|
}
|
|
|
|
|
|
|
|
cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
|
|
|
|
|
2008-03-26 14:08:57 -06:00
|
|
|
if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
|
2006-03-29 01:21:00 -07:00
|
|
|
cmdreg |= 1 << 6;
|
|
|
|
|
|
|
|
if (cmd->flags & MMC_RSP_BUSY)
|
|
|
|
cmdreg |= 1 << 11;
|
|
|
|
|
|
|
|
if (host->data && !(host->data->flags & MMC_DATA_WRITE))
|
|
|
|
cmdreg |= 1 << 15;
|
|
|
|
|
2008-03-26 14:09:48 -06:00
|
|
|
mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
|
2008-03-26 14:09:29 -06:00
|
|
|
|
2006-11-11 15:36:52 -07:00
|
|
|
OMAP_MMC_WRITE(host, CTO, 200);
|
|
|
|
OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
|
|
|
|
OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
|
|
|
|
OMAP_MMC_WRITE(host, IE,
|
2006-03-29 01:21:00 -07:00
|
|
|
OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
|
|
|
|
OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
|
|
|
|
OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
|
|
|
|
OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
|
|
|
|
OMAP_MMC_STAT_END_OF_DATA);
|
2006-11-11 15:36:52 -07:00
|
|
|
OMAP_MMC_WRITE(host, CMD, cmdreg);
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
|
2008-03-26 14:09:12 -06:00
|
|
|
static void
|
|
|
|
mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
|
|
|
|
int abort)
|
|
|
|
{
|
|
|
|
enum dma_data_direction dma_data_dir;
|
2012-04-21 15:35:42 -06:00
|
|
|
struct device *dev = mmc_dev(host->mmc);
|
|
|
|
struct dma_chan *c;
|
2008-03-26 14:09:12 -06:00
|
|
|
|
2012-04-21 15:35:42 -06:00
|
|
|
if (data->flags & MMC_DATA_WRITE) {
|
2008-03-26 14:09:12 -06:00
|
|
|
dma_data_dir = DMA_TO_DEVICE;
|
2012-04-21 15:35:42 -06:00
|
|
|
c = host->dma_tx;
|
|
|
|
} else {
|
2008-03-26 14:09:12 -06:00
|
|
|
dma_data_dir = DMA_FROM_DEVICE;
|
2012-04-21 15:35:42 -06:00
|
|
|
c = host->dma_rx;
|
|
|
|
}
|
|
|
|
if (c) {
|
|
|
|
if (data->error) {
|
|
|
|
dmaengine_terminate_all(c);
|
|
|
|
/* Claim nothing transferred on error... */
|
|
|
|
data->bytes_xfered = 0;
|
|
|
|
}
|
|
|
|
dev = c->device->dev;
|
|
|
|
}
|
|
|
|
dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
|
2008-03-26 14:09:12 -06:00
|
|
|
}
|
|
|
|
|
2008-03-26 14:09:58 -06:00
|
|
|
static void mmc_omap_send_stop_work(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
|
|
|
|
send_stop_work);
|
|
|
|
struct mmc_omap_slot *slot = host->current_slot;
|
|
|
|
struct mmc_data *data = host->stop_data;
|
|
|
|
unsigned long tick_ns;
|
|
|
|
|
|
|
|
tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq;
|
|
|
|
ndelay(8*tick_ns);
|
|
|
|
|
|
|
|
mmc_omap_start_command(host, data->stop);
|
|
|
|
}
|
|
|
|
|
2006-03-29 01:21:00 -07:00
|
|
|
static void
|
|
|
|
mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
|
|
|
|
{
|
2008-03-26 14:09:12 -06:00
|
|
|
if (host->dma_in_use)
|
|
|
|
mmc_omap_release_dma(host, data, data->error);
|
|
|
|
|
2006-03-29 01:21:00 -07:00
|
|
|
host->data = NULL;
|
|
|
|
host->sg_len = 0;
|
|
|
|
|
|
|
|
/* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
|
|
|
|
* dozens of requests until the card finishes writing data.
|
|
|
|
* It'd be cheaper to just wait till an EOFB interrupt arrives...
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (!data->stop) {
|
2008-03-26 14:09:12 -06:00
|
|
|
struct mmc_host *mmc;
|
|
|
|
|
2006-03-29 01:21:00 -07:00
|
|
|
host->mrq = NULL;
|
2008-03-26 14:09:12 -06:00
|
|
|
mmc = host->mmc;
|
2008-03-26 14:09:52 -06:00
|
|
|
mmc_omap_release_slot(host->current_slot, 1);
|
2008-03-26 14:09:12 -06:00
|
|
|
mmc_request_done(mmc, data->mrq);
|
2006-03-29 01:21:00 -07:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2008-03-26 14:09:58 -06:00
|
|
|
host->stop_data = data;
|
2012-05-08 05:35:33 -06:00
|
|
|
queue_work(host->mmc_omap_wq, &host->send_stop_work);
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
|
2008-03-26 14:09:29 -06:00
|
|
|
static void
|
2008-03-26 14:09:48 -06:00
|
|
|
mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
|
2008-03-26 14:09:29 -06:00
|
|
|
{
|
|
|
|
struct mmc_omap_slot *slot = host->current_slot;
|
|
|
|
unsigned int restarts, passes, timeout;
|
|
|
|
u16 stat = 0;
|
|
|
|
|
|
|
|
/* Sending abort takes 80 clocks. Have some extra and round up */
|
|
|
|
timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
|
|
|
|
restarts = 0;
|
2008-03-26 14:09:48 -06:00
|
|
|
while (restarts < maxloops) {
|
2008-03-26 14:09:29 -06:00
|
|
|
OMAP_MMC_WRITE(host, STAT, 0xFFFF);
|
|
|
|
OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
|
|
|
|
|
|
|
|
passes = 0;
|
|
|
|
while (passes < timeout) {
|
|
|
|
stat = OMAP_MMC_READ(host, STAT);
|
|
|
|
if (stat & OMAP_MMC_STAT_END_OF_CMD)
|
|
|
|
goto out;
|
|
|
|
udelay(1);
|
|
|
|
passes++;
|
|
|
|
}
|
|
|
|
|
|
|
|
restarts++;
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
OMAP_MMC_WRITE(host, STAT, stat);
|
|
|
|
}
|
|
|
|
|
2008-03-26 14:09:12 -06:00
|
|
|
static void
|
|
|
|
mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
|
|
|
|
{
|
|
|
|
if (host->dma_in_use)
|
|
|
|
mmc_omap_release_dma(host, data, 1);
|
|
|
|
|
|
|
|
host->data = NULL;
|
|
|
|
host->sg_len = 0;
|
|
|
|
|
2008-03-26 14:09:48 -06:00
|
|
|
mmc_omap_send_abort(host, 10000);
|
2008-03-26 14:09:12 -06:00
|
|
|
}
|
|
|
|
|
2006-03-29 01:21:00 -07:00
|
|
|
static void
|
|
|
|
mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
int done;
|
|
|
|
|
|
|
|
if (!host->dma_in_use) {
|
|
|
|
mmc_omap_xfer_done(host, data);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
done = 0;
|
|
|
|
spin_lock_irqsave(&host->dma_lock, flags);
|
|
|
|
if (host->dma_done)
|
|
|
|
done = 1;
|
|
|
|
else
|
|
|
|
host->brs_received = 1;
|
|
|
|
spin_unlock_irqrestore(&host->dma_lock, flags);
|
|
|
|
if (done)
|
|
|
|
mmc_omap_xfer_done(host, data);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
int done;
|
|
|
|
|
|
|
|
done = 0;
|
|
|
|
spin_lock_irqsave(&host->dma_lock, flags);
|
|
|
|
if (host->brs_received)
|
|
|
|
done = 1;
|
|
|
|
else
|
|
|
|
host->dma_done = 1;
|
|
|
|
spin_unlock_irqrestore(&host->dma_lock, flags);
|
|
|
|
if (done)
|
|
|
|
mmc_omap_xfer_done(host, data);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
|
|
|
|
{
|
|
|
|
host->cmd = NULL;
|
|
|
|
|
2008-03-26 14:09:48 -06:00
|
|
|
del_timer(&host->cmd_abort_timer);
|
2008-03-26 14:09:29 -06:00
|
|
|
|
2006-03-29 01:21:00 -07:00
|
|
|
if (cmd->flags & MMC_RSP_PRESENT) {
|
|
|
|
if (cmd->flags & MMC_RSP_136) {
|
|
|
|
/* response type 2 */
|
|
|
|
cmd->resp[3] =
|
2006-11-11 15:36:52 -07:00
|
|
|
OMAP_MMC_READ(host, RSP0) |
|
|
|
|
(OMAP_MMC_READ(host, RSP1) << 16);
|
2006-03-29 01:21:00 -07:00
|
|
|
cmd->resp[2] =
|
2006-11-11 15:36:52 -07:00
|
|
|
OMAP_MMC_READ(host, RSP2) |
|
|
|
|
(OMAP_MMC_READ(host, RSP3) << 16);
|
2006-03-29 01:21:00 -07:00
|
|
|
cmd->resp[1] =
|
2006-11-11 15:36:52 -07:00
|
|
|
OMAP_MMC_READ(host, RSP4) |
|
|
|
|
(OMAP_MMC_READ(host, RSP5) << 16);
|
2006-03-29 01:21:00 -07:00
|
|
|
cmd->resp[0] =
|
2006-11-11 15:36:52 -07:00
|
|
|
OMAP_MMC_READ(host, RSP6) |
|
|
|
|
(OMAP_MMC_READ(host, RSP7) << 16);
|
2006-03-29 01:21:00 -07:00
|
|
|
} else {
|
|
|
|
/* response types 1, 1b, 3, 4, 5, 6 */
|
|
|
|
cmd->resp[0] =
|
2006-11-11 15:36:52 -07:00
|
|
|
OMAP_MMC_READ(host, RSP6) |
|
|
|
|
(OMAP_MMC_READ(host, RSP7) << 16);
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-07-22 14:18:46 -06:00
|
|
|
if (host->data == NULL || cmd->error) {
|
2008-03-26 14:09:12 -06:00
|
|
|
struct mmc_host *mmc;
|
|
|
|
|
|
|
|
if (host->data != NULL)
|
|
|
|
mmc_omap_abort_xfer(host, host->data);
|
2006-03-29 01:21:00 -07:00
|
|
|
host->mrq = NULL;
|
2008-03-26 14:09:12 -06:00
|
|
|
mmc = host->mmc;
|
2008-03-26 14:09:52 -06:00
|
|
|
mmc_omap_release_slot(host->current_slot, 1);
|
2008-03-26 14:09:12 -06:00
|
|
|
mmc_request_done(mmc, cmd->mrq);
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-03-26 14:09:29 -06:00
|
|
|
/*
|
|
|
|
* Abort stuck command. Can occur when card is removed while it is being
|
|
|
|
* read.
|
|
|
|
*/
|
|
|
|
static void mmc_omap_abort_command(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
|
2008-03-26 14:09:48 -06:00
|
|
|
cmd_abort_work);
|
|
|
|
BUG_ON(!host->cmd);
|
2008-03-26 14:09:29 -06:00
|
|
|
|
|
|
|
dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
|
|
|
|
host->cmd->opcode);
|
|
|
|
|
2008-03-26 14:09:48 -06:00
|
|
|
if (host->cmd->error == 0)
|
|
|
|
host->cmd->error = -ETIMEDOUT;
|
2008-03-26 14:09:29 -06:00
|
|
|
|
2008-03-26 14:09:48 -06:00
|
|
|
if (host->data == NULL) {
|
|
|
|
struct mmc_command *cmd;
|
|
|
|
struct mmc_host *mmc;
|
|
|
|
|
|
|
|
cmd = host->cmd;
|
|
|
|
host->cmd = NULL;
|
|
|
|
mmc_omap_send_abort(host, 10000);
|
|
|
|
|
|
|
|
host->mrq = NULL;
|
|
|
|
mmc = host->mmc;
|
2008-03-26 14:09:52 -06:00
|
|
|
mmc_omap_release_slot(host->current_slot, 1);
|
2008-03-26 14:09:48 -06:00
|
|
|
mmc_request_done(mmc, cmd->mrq);
|
|
|
|
} else
|
|
|
|
mmc_omap_cmd_done(host, host->cmd);
|
2008-03-26 14:09:29 -06:00
|
|
|
|
2008-03-26 14:09:48 -06:00
|
|
|
host->abort = 0;
|
|
|
|
enable_irq(host->irq);
|
2008-03-26 14:09:29 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
mmc_omap_cmd_timer(unsigned long data)
|
|
|
|
{
|
|
|
|
struct mmc_omap_host *host = (struct mmc_omap_host *) data;
|
2008-03-26 14:09:48 -06:00
|
|
|
unsigned long flags;
|
2008-03-26 14:09:29 -06:00
|
|
|
|
2008-03-26 14:09:48 -06:00
|
|
|
spin_lock_irqsave(&host->slot_lock, flags);
|
|
|
|
if (host->cmd != NULL && !host->abort) {
|
|
|
|
OMAP_MMC_WRITE(host, IE, 0);
|
|
|
|
disable_irq(host->irq);
|
|
|
|
host->abort = 1;
|
2012-05-08 05:35:33 -06:00
|
|
|
queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
|
2008-03-26 14:09:48 -06:00
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&host->slot_lock, flags);
|
2008-03-26 14:09:29 -06:00
|
|
|
}
|
|
|
|
|
2006-03-29 01:21:00 -07:00
|
|
|
/* PIO only */
|
|
|
|
static void
|
|
|
|
mmc_omap_sg_to_buf(struct mmc_omap_host *host)
|
|
|
|
{
|
|
|
|
struct scatterlist *sg;
|
|
|
|
|
|
|
|
sg = host->data->sg + host->sg_idx;
|
|
|
|
host->buffer_bytes_left = sg->length;
|
2007-10-22 13:19:53 -06:00
|
|
|
host->buffer = sg_virt(sg);
|
2006-03-29 01:21:00 -07:00
|
|
|
if (host->buffer_bytes_left > host->total_bytes_left)
|
|
|
|
host->buffer_bytes_left = host->total_bytes_left;
|
|
|
|
}
|
|
|
|
|
2008-03-26 14:09:52 -06:00
|
|
|
static void
|
|
|
|
mmc_omap_clk_timer(unsigned long data)
|
|
|
|
{
|
|
|
|
struct mmc_omap_host *host = (struct mmc_omap_host *) data;
|
|
|
|
|
|
|
|
mmc_omap_fclk_enable(host, 0);
|
|
|
|
}
|
|
|
|
|
2006-03-29 01:21:00 -07:00
|
|
|
/* PIO only */
|
|
|
|
static void
|
|
|
|
mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
|
|
|
|
{
|
2012-08-24 00:00:18 -06:00
|
|
|
int n, nwords;
|
2006-03-29 01:21:00 -07:00
|
|
|
|
|
|
|
if (host->buffer_bytes_left == 0) {
|
|
|
|
host->sg_idx++;
|
|
|
|
BUG_ON(host->sg_idx == host->sg_len);
|
|
|
|
mmc_omap_sg_to_buf(host);
|
|
|
|
}
|
|
|
|
n = 64;
|
|
|
|
if (n > host->buffer_bytes_left)
|
|
|
|
n = host->buffer_bytes_left;
|
2012-08-24 00:00:18 -06:00
|
|
|
|
|
|
|
nwords = n / 2;
|
|
|
|
nwords += n & 1; /* handle odd number of bytes to transfer */
|
|
|
|
|
2006-03-29 01:21:00 -07:00
|
|
|
host->buffer_bytes_left -= n;
|
|
|
|
host->total_bytes_left -= n;
|
|
|
|
host->data->bytes_xfered += n;
|
|
|
|
|
|
|
|
if (write) {
|
2012-08-24 00:00:18 -06:00
|
|
|
__raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
|
|
|
|
host->buffer, nwords);
|
2006-03-29 01:21:00 -07:00
|
|
|
} else {
|
2012-08-24 00:00:18 -06:00
|
|
|
__raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
|
|
|
|
host->buffer, nwords);
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
2012-08-24 00:00:18 -06:00
|
|
|
|
|
|
|
host->buffer += nwords;
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
|
2012-08-07 07:33:01 -06:00
|
|
|
#ifdef CONFIG_MMC_DEBUG
|
|
|
|
static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
|
2006-03-29 01:21:00 -07:00
|
|
|
{
|
|
|
|
static const char *mmc_omap_status_bits[] = {
|
|
|
|
"EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
|
|
|
|
"CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
|
|
|
|
};
|
2012-08-07 07:33:01 -06:00
|
|
|
int i;
|
|
|
|
char res[64], *buf = res;
|
|
|
|
|
|
|
|
buf += sprintf(buf, "MMC IRQ 0x%x:", status);
|
2006-03-29 01:21:00 -07:00
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
|
2012-08-07 07:33:01 -06:00
|
|
|
if (status & (1 << i))
|
|
|
|
buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
|
|
|
|
dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
|
|
|
|
{
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
2012-08-07 07:33:01 -06:00
|
|
|
#endif
|
|
|
|
|
2006-03-29 01:21:00 -07:00
|
|
|
|
IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 07:55:46 -06:00
|
|
|
static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
|
2006-03-29 01:21:00 -07:00
|
|
|
{
|
|
|
|
struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
|
|
|
|
u16 status;
|
|
|
|
int end_command;
|
|
|
|
int end_transfer;
|
2008-03-26 14:09:26 -06:00
|
|
|
int transfer_error, cmd_error;
|
2006-03-29 01:21:00 -07:00
|
|
|
|
|
|
|
if (host->cmd == NULL && host->data == NULL) {
|
2006-11-11 15:36:52 -07:00
|
|
|
status = OMAP_MMC_READ(host, STAT);
|
2008-03-26 14:09:26 -06:00
|
|
|
dev_info(mmc_dev(host->slots[0]->mmc),
|
|
|
|
"Spurious IRQ 0x%04x\n", status);
|
2006-03-29 01:21:00 -07:00
|
|
|
if (status != 0) {
|
2006-11-11 15:36:52 -07:00
|
|
|
OMAP_MMC_WRITE(host, STAT, status);
|
|
|
|
OMAP_MMC_WRITE(host, IE, 0);
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
end_command = 0;
|
|
|
|
end_transfer = 0;
|
|
|
|
transfer_error = 0;
|
2008-03-26 14:09:26 -06:00
|
|
|
cmd_error = 0;
|
2006-03-29 01:21:00 -07:00
|
|
|
|
2006-11-11 15:36:52 -07:00
|
|
|
while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
|
2008-03-26 14:09:26 -06:00
|
|
|
int cmd;
|
|
|
|
|
2006-11-11 15:36:52 -07:00
|
|
|
OMAP_MMC_WRITE(host, STAT, status);
|
2008-03-26 14:09:26 -06:00
|
|
|
if (host->cmd != NULL)
|
|
|
|
cmd = host->cmd->opcode;
|
|
|
|
else
|
|
|
|
cmd = -1;
|
2006-03-29 01:21:00 -07:00
|
|
|
dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
|
2008-03-26 14:09:26 -06:00
|
|
|
status, cmd);
|
2012-08-07 07:33:01 -06:00
|
|
|
mmc_omap_report_irq(host, status);
|
|
|
|
|
2006-03-29 01:21:00 -07:00
|
|
|
if (host->total_bytes_left) {
|
|
|
|
if ((status & OMAP_MMC_STAT_A_FULL) ||
|
|
|
|
(status & OMAP_MMC_STAT_END_OF_DATA))
|
|
|
|
mmc_omap_xfer_data(host, 0);
|
|
|
|
if (status & OMAP_MMC_STAT_A_EMPTY)
|
|
|
|
mmc_omap_xfer_data(host, 1);
|
|
|
|
}
|
|
|
|
|
2008-03-26 14:09:26 -06:00
|
|
|
if (status & OMAP_MMC_STAT_END_OF_DATA)
|
2006-03-29 01:21:00 -07:00
|
|
|
end_transfer = 1;
|
|
|
|
|
|
|
|
if (status & OMAP_MMC_STAT_DATA_TOUT) {
|
2008-03-26 14:09:26 -06:00
|
|
|
dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
|
|
|
|
cmd);
|
2006-03-29 01:21:00 -07:00
|
|
|
if (host->data) {
|
2007-07-22 14:18:46 -06:00
|
|
|
host->data->error = -ETIMEDOUT;
|
2006-03-29 01:21:00 -07:00
|
|
|
transfer_error = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status & OMAP_MMC_STAT_DATA_CRC) {
|
|
|
|
if (host->data) {
|
2007-07-22 14:18:46 -06:00
|
|
|
host->data->error = -EILSEQ;
|
2006-03-29 01:21:00 -07:00
|
|
|
dev_dbg(mmc_dev(host->mmc),
|
|
|
|
"data CRC error, bytes left %d\n",
|
|
|
|
host->total_bytes_left);
|
|
|
|
transfer_error = 1;
|
|
|
|
} else {
|
|
|
|
dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status & OMAP_MMC_STAT_CMD_TOUT) {
|
|
|
|
/* Timeouts are routine with some commands */
|
|
|
|
if (host->cmd) {
|
2008-03-26 14:08:57 -06:00
|
|
|
struct mmc_omap_slot *slot =
|
|
|
|
host->current_slot;
|
2008-03-26 14:09:26 -06:00
|
|
|
if (slot == NULL ||
|
|
|
|
!mmc_omap_cover_is_open(slot))
|
2008-03-26 14:09:08 -06:00
|
|
|
dev_err(mmc_dev(host->mmc),
|
2008-03-26 14:09:26 -06:00
|
|
|
"command timeout (CMD%d)\n",
|
|
|
|
cmd);
|
2007-07-22 14:18:46 -06:00
|
|
|
host->cmd->error = -ETIMEDOUT;
|
2006-03-29 01:21:00 -07:00
|
|
|
end_command = 1;
|
2008-03-26 14:09:26 -06:00
|
|
|
cmd_error = 1;
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status & OMAP_MMC_STAT_CMD_CRC) {
|
|
|
|
if (host->cmd) {
|
|
|
|
dev_err(mmc_dev(host->mmc),
|
|
|
|
"command CRC error (CMD%d, arg 0x%08x)\n",
|
2008-03-26 14:09:26 -06:00
|
|
|
cmd, host->cmd->arg);
|
2007-07-22 14:18:46 -06:00
|
|
|
host->cmd->error = -EILSEQ;
|
2006-03-29 01:21:00 -07:00
|
|
|
end_command = 1;
|
2008-03-26 14:09:26 -06:00
|
|
|
cmd_error = 1;
|
2006-03-29 01:21:00 -07:00
|
|
|
} else
|
|
|
|
dev_err(mmc_dev(host->mmc),
|
|
|
|
"command CRC error without cmd?\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status & OMAP_MMC_STAT_CARD_ERR) {
|
2007-06-13 11:09:28 -06:00
|
|
|
dev_dbg(mmc_dev(host->mmc),
|
|
|
|
"ignoring card status error (CMD%d)\n",
|
2008-03-26 14:09:26 -06:00
|
|
|
cmd);
|
2007-06-13 11:09:28 -06:00
|
|
|
end_command = 1;
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* NOTE: On 1610 the END_OF_CMD may come too early when
|
2008-03-26 14:09:26 -06:00
|
|
|
* starting a write
|
2006-03-29 01:21:00 -07:00
|
|
|
*/
|
|
|
|
if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
|
|
|
|
(!(status & OMAP_MMC_STAT_A_EMPTY))) {
|
|
|
|
end_command = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-03-26 14:09:48 -06:00
|
|
|
if (cmd_error && host->data) {
|
|
|
|
del_timer(&host->cmd_abort_timer);
|
|
|
|
host->abort = 1;
|
|
|
|
OMAP_MMC_WRITE(host, IE, 0);
|
2009-04-15 23:55:21 -06:00
|
|
|
disable_irq_nosync(host->irq);
|
2012-05-08 05:35:33 -06:00
|
|
|
queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
|
2008-03-26 14:09:48 -06:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2011-04-11 15:00:44 -06:00
|
|
|
if (end_command && host->cmd)
|
2006-03-29 01:21:00 -07:00
|
|
|
mmc_omap_cmd_done(host, host->cmd);
|
2008-03-26 14:09:26 -06:00
|
|
|
if (host->data != NULL) {
|
|
|
|
if (transfer_error)
|
|
|
|
mmc_omap_xfer_done(host, host->data);
|
|
|
|
else if (end_transfer)
|
|
|
|
mmc_omap_end_of_data(host, host->data);
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2008-03-26 14:09:42 -06:00
|
|
|
void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
|
2008-03-26 14:09:08 -06:00
|
|
|
{
|
2008-03-26 14:09:42 -06:00
|
|
|
int cover_open;
|
2008-03-26 14:09:08 -06:00
|
|
|
struct mmc_omap_host *host = dev_get_drvdata(dev);
|
2008-03-26 14:09:42 -06:00
|
|
|
struct mmc_omap_slot *slot = host->slots[num];
|
2008-03-26 14:09:08 -06:00
|
|
|
|
2008-03-26 14:09:42 -06:00
|
|
|
BUG_ON(num >= host->nr_slots);
|
2008-03-26 14:09:08 -06:00
|
|
|
|
|
|
|
/* Other subsystems can call in here before we're initialised. */
|
2008-03-26 14:09:42 -06:00
|
|
|
if (host->nr_slots == 0 || !host->slots[num])
|
2008-03-26 14:09:08 -06:00
|
|
|
return;
|
|
|
|
|
2008-03-26 14:09:42 -06:00
|
|
|
cover_open = mmc_omap_cover_is_open(slot);
|
|
|
|
if (cover_open != slot->cover_open) {
|
|
|
|
slot->cover_open = cover_open;
|
|
|
|
sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
|
|
|
|
}
|
|
|
|
|
|
|
|
tasklet_hi_schedule(&slot->cover_tasklet);
|
2008-03-26 14:09:08 -06:00
|
|
|
}
|
|
|
|
|
2008-03-26 14:09:42 -06:00
|
|
|
static void mmc_omap_cover_timer(unsigned long arg)
|
2008-03-26 14:09:08 -06:00
|
|
|
{
|
|
|
|
struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
|
2008-03-26 14:09:42 -06:00
|
|
|
tasklet_schedule(&slot->cover_tasklet);
|
2008-03-26 14:09:08 -06:00
|
|
|
}
|
|
|
|
|
2008-03-26 14:09:42 -06:00
|
|
|
static void mmc_omap_cover_handler(unsigned long param)
|
2008-03-26 14:09:08 -06:00
|
|
|
{
|
2008-03-26 14:09:42 -06:00
|
|
|
struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
|
|
|
|
int cover_open = mmc_omap_cover_is_open(slot);
|
2008-03-26 14:09:08 -06:00
|
|
|
|
2008-03-26 14:09:42 -06:00
|
|
|
mmc_detect_change(slot->mmc, 0);
|
|
|
|
if (!cover_open)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If no card is inserted, we postpone polling until
|
|
|
|
* the cover has been closed.
|
|
|
|
*/
|
|
|
|
if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
|
|
|
|
return;
|
|
|
|
|
|
|
|
mod_timer(&slot->cover_timer,
|
|
|
|
jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
|
2008-03-26 14:09:08 -06:00
|
|
|
}
|
|
|
|
|
2012-04-21 15:35:42 -06:00
|
|
|
static void mmc_omap_dma_callback(void *priv)
|
|
|
|
{
|
|
|
|
struct mmc_omap_host *host = priv;
|
|
|
|
struct mmc_data *data = host->data;
|
|
|
|
|
|
|
|
/* If we got to the end of DMA, assume everything went well */
|
|
|
|
data->bytes_xfered += data->blocks * data->blksz;
|
|
|
|
|
|
|
|
mmc_omap_dma_done(host, data);
|
|
|
|
}
|
|
|
|
|
2006-03-29 01:21:00 -07:00
|
|
|
static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
|
|
|
|
{
|
|
|
|
u16 reg;
|
|
|
|
|
2006-11-11 15:36:52 -07:00
|
|
|
reg = OMAP_MMC_READ(host, SDIO);
|
2006-03-29 01:21:00 -07:00
|
|
|
reg &= ~(1 << 5);
|
2006-11-11 15:36:52 -07:00
|
|
|
OMAP_MMC_WRITE(host, SDIO, reg);
|
2006-03-29 01:21:00 -07:00
|
|
|
/* Set maximum timeout */
|
2006-11-11 15:36:52 -07:00
|
|
|
OMAP_MMC_WRITE(host, CTO, 0xff);
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
|
|
|
|
{
|
2008-03-26 14:09:16 -06:00
|
|
|
unsigned int timeout, cycle_ns;
|
2006-03-29 01:21:00 -07:00
|
|
|
u16 reg;
|
|
|
|
|
2008-03-26 14:09:16 -06:00
|
|
|
cycle_ns = 1000000000 / host->current_slot->fclk_freq;
|
|
|
|
timeout = req->data->timeout_ns / cycle_ns;
|
|
|
|
timeout += req->data->timeout_clks;
|
2006-03-29 01:21:00 -07:00
|
|
|
|
|
|
|
/* Check if we need to use timeout multiplier register */
|
2006-11-11 15:36:52 -07:00
|
|
|
reg = OMAP_MMC_READ(host, SDIO);
|
2006-03-29 01:21:00 -07:00
|
|
|
if (timeout > 0xffff) {
|
|
|
|
reg |= (1 << 5);
|
|
|
|
timeout /= 1024;
|
|
|
|
} else
|
|
|
|
reg &= ~(1 << 5);
|
2006-11-11 15:36:52 -07:00
|
|
|
OMAP_MMC_WRITE(host, SDIO, reg);
|
|
|
|
OMAP_MMC_WRITE(host, DTO, timeout);
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
|
|
|
|
{
|
|
|
|
struct mmc_data *data = req->data;
|
|
|
|
int i, use_dma, block_size;
|
|
|
|
unsigned sg_len;
|
|
|
|
|
|
|
|
host->data = data;
|
|
|
|
if (data == NULL) {
|
2006-11-11 15:36:52 -07:00
|
|
|
OMAP_MMC_WRITE(host, BLEN, 0);
|
|
|
|
OMAP_MMC_WRITE(host, NBLK, 0);
|
|
|
|
OMAP_MMC_WRITE(host, BUF, 0);
|
2006-03-29 01:21:00 -07:00
|
|
|
host->dma_in_use = 0;
|
|
|
|
set_cmd_timeout(host, req);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2006-06-04 10:51:15 -06:00
|
|
|
block_size = data->blksz;
|
2006-03-29 01:21:00 -07:00
|
|
|
|
2006-11-11 15:36:52 -07:00
|
|
|
OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
|
|
|
|
OMAP_MMC_WRITE(host, BLEN, block_size - 1);
|
2006-03-29 01:21:00 -07:00
|
|
|
set_data_timeout(host, req);
|
|
|
|
|
|
|
|
/* cope with calling layer confusion; it issues "single
|
|
|
|
* block" writes using multi-block scatterlists.
|
|
|
|
*/
|
|
|
|
sg_len = (data->blocks == 1) ? 1 : data->sg_len;
|
|
|
|
|
|
|
|
/* Only do DMA for entire blocks */
|
|
|
|
use_dma = host->use_dma;
|
|
|
|
if (use_dma) {
|
|
|
|
for (i = 0; i < sg_len; i++) {
|
|
|
|
if ((data->sg[i].length % block_size) != 0) {
|
|
|
|
use_dma = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
host->sg_idx = 0;
|
2012-04-21 15:35:42 -06:00
|
|
|
if (use_dma) {
|
|
|
|
enum dma_data_direction dma_data_dir;
|
|
|
|
struct dma_async_tx_descriptor *tx;
|
|
|
|
struct dma_chan *c;
|
|
|
|
u32 burst, *bp;
|
|
|
|
u16 buf;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
|
|
|
|
* and 24xx. Use 16 or 32 word frames when the
|
|
|
|
* blocksize is at least that large. Blocksize is
|
|
|
|
* usually 512 bytes; but not for some SD reads.
|
|
|
|
*/
|
|
|
|
burst = cpu_is_omap15xx() ? 32 : 64;
|
|
|
|
if (burst > data->blksz)
|
|
|
|
burst = data->blksz;
|
|
|
|
|
|
|
|
burst >>= 1;
|
|
|
|
|
|
|
|
if (data->flags & MMC_DATA_WRITE) {
|
|
|
|
c = host->dma_tx;
|
|
|
|
bp = &host->dma_tx_burst;
|
|
|
|
buf = 0x0f80 | (burst - 1) << 0;
|
|
|
|
dma_data_dir = DMA_TO_DEVICE;
|
|
|
|
} else {
|
|
|
|
c = host->dma_rx;
|
|
|
|
bp = &host->dma_rx_burst;
|
|
|
|
buf = 0x800f | (burst - 1) << 8;
|
|
|
|
dma_data_dir = DMA_FROM_DEVICE;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!c)
|
|
|
|
goto use_pio;
|
|
|
|
|
|
|
|
/* Only reconfigure if we have a different burst size */
|
|
|
|
if (*bp != burst) {
|
|
|
|
struct dma_slave_config cfg;
|
|
|
|
|
|
|
|
cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
|
|
|
|
cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
|
|
|
|
cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
|
|
|
|
cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
|
|
|
|
cfg.src_maxburst = burst;
|
|
|
|
cfg.dst_maxburst = burst;
|
|
|
|
|
|
|
|
if (dmaengine_slave_config(c, &cfg))
|
|
|
|
goto use_pio;
|
|
|
|
|
|
|
|
*bp = burst;
|
|
|
|
}
|
|
|
|
|
|
|
|
host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
|
|
|
|
dma_data_dir);
|
|
|
|
if (host->sg_len == 0)
|
|
|
|
goto use_pio;
|
|
|
|
|
|
|
|
tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
|
|
|
|
data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
|
|
|
|
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
|
|
if (!tx)
|
|
|
|
goto use_pio;
|
|
|
|
|
|
|
|
OMAP_MMC_WRITE(host, BUF, buf);
|
|
|
|
|
|
|
|
tx->callback = mmc_omap_dma_callback;
|
|
|
|
tx->callback_param = host;
|
|
|
|
dmaengine_submit(tx);
|
|
|
|
host->brs_received = 0;
|
|
|
|
host->dma_done = 0;
|
|
|
|
host->dma_in_use = 1;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
use_pio:
|
2006-03-29 01:21:00 -07:00
|
|
|
|
|
|
|
/* Revert to PIO? */
|
2012-04-21 15:41:10 -06:00
|
|
|
OMAP_MMC_WRITE(host, BUF, 0x1f1f);
|
|
|
|
host->total_bytes_left = data->blocks * block_size;
|
|
|
|
host->sg_len = sg_len;
|
|
|
|
mmc_omap_sg_to_buf(host);
|
|
|
|
host->dma_in_use = 0;
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
|
2008-03-26 14:08:57 -06:00
|
|
|
static void mmc_omap_start_request(struct mmc_omap_host *host,
|
|
|
|
struct mmc_request *req)
|
2006-03-29 01:21:00 -07:00
|
|
|
{
|
2008-03-26 14:08:57 -06:00
|
|
|
BUG_ON(host->mrq != NULL);
|
2006-03-29 01:21:00 -07:00
|
|
|
|
|
|
|
host->mrq = req;
|
|
|
|
|
|
|
|
/* only touch fifo AFTER the controller readies it */
|
|
|
|
mmc_omap_prepare_data(host, req);
|
|
|
|
mmc_omap_start_command(host, req->cmd);
|
2012-04-21 15:35:42 -06:00
|
|
|
if (host->dma_in_use) {
|
|
|
|
struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
|
|
|
|
host->dma_tx : host->dma_rx;
|
|
|
|
|
2012-04-21 15:41:10 -06:00
|
|
|
dma_async_issue_pending(c);
|
2012-04-21 15:35:42 -06:00
|
|
|
}
|
2008-03-26 14:08:57 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
|
|
|
|
{
|
|
|
|
struct mmc_omap_slot *slot = mmc_priv(mmc);
|
|
|
|
struct mmc_omap_host *host = slot->host;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&host->slot_lock, flags);
|
|
|
|
if (host->mmc != NULL) {
|
|
|
|
BUG_ON(slot->mrq != NULL);
|
|
|
|
slot->mrq = req;
|
|
|
|
spin_unlock_irqrestore(&host->slot_lock, flags);
|
|
|
|
return;
|
|
|
|
} else
|
|
|
|
host->mmc = mmc;
|
|
|
|
spin_unlock_irqrestore(&host->slot_lock, flags);
|
|
|
|
mmc_omap_select_slot(slot, 1);
|
|
|
|
mmc_omap_start_request(host, req);
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
|
2008-03-26 14:09:22 -06:00
|
|
|
static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
|
|
|
|
int vdd)
|
2006-03-29 01:21:00 -07:00
|
|
|
{
|
2008-03-26 14:09:22 -06:00
|
|
|
struct mmc_omap_host *host;
|
2006-03-29 01:21:00 -07:00
|
|
|
|
2008-03-26 14:09:22 -06:00
|
|
|
host = slot->host;
|
|
|
|
|
|
|
|
if (slot->pdata->set_power != NULL)
|
|
|
|
slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
|
|
|
|
vdd);
|
|
|
|
|
|
|
|
if (cpu_is_omap24xx()) {
|
|
|
|
u16 w;
|
|
|
|
|
|
|
|
if (power_on) {
|
|
|
|
w = OMAP_MMC_READ(host, CON);
|
|
|
|
OMAP_MMC_WRITE(host, CON, w | (1 << 11));
|
|
|
|
} else {
|
|
|
|
w = OMAP_MMC_READ(host, CON);
|
|
|
|
OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
|
|
|
|
}
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-05-01 08:36:00 -06:00
|
|
|
static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
|
2006-03-29 01:21:00 -07:00
|
|
|
{
|
2008-03-26 14:08:57 -06:00
|
|
|
struct mmc_omap_slot *slot = mmc_priv(mmc);
|
|
|
|
struct mmc_omap_host *host = slot->host;
|
2007-05-01 08:36:00 -06:00
|
|
|
int func_clk_rate = clk_get_rate(host->fclk);
|
2006-03-29 01:21:00 -07:00
|
|
|
int dsor;
|
|
|
|
|
|
|
|
if (ios->clock == 0)
|
2007-05-01 08:36:00 -06:00
|
|
|
return 0;
|
2006-03-29 01:21:00 -07:00
|
|
|
|
2007-05-01 08:36:00 -06:00
|
|
|
dsor = func_clk_rate / ios->clock;
|
|
|
|
if (dsor < 1)
|
|
|
|
dsor = 1;
|
2006-03-29 01:21:00 -07:00
|
|
|
|
2007-05-01 08:36:00 -06:00
|
|
|
if (func_clk_rate / dsor > ios->clock)
|
2006-03-29 01:21:00 -07:00
|
|
|
dsor++;
|
|
|
|
|
2007-05-01 08:36:00 -06:00
|
|
|
if (dsor > 250)
|
|
|
|
dsor = 250;
|
|
|
|
|
2008-03-26 14:08:57 -06:00
|
|
|
slot->fclk_freq = func_clk_rate / dsor;
|
|
|
|
|
2007-05-01 08:36:00 -06:00
|
|
|
if (ios->bus_width == MMC_BUS_WIDTH_4)
|
|
|
|
dsor |= 1 << 15;
|
|
|
|
|
|
|
|
return dsor;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
|
|
{
|
2008-03-26 14:08:57 -06:00
|
|
|
struct mmc_omap_slot *slot = mmc_priv(mmc);
|
|
|
|
struct mmc_omap_host *host = slot->host;
|
|
|
|
int i, dsor;
|
2008-03-26 14:09:52 -06:00
|
|
|
int clk_enabled;
|
2008-03-26 14:09:22 -06:00
|
|
|
|
|
|
|
mmc_omap_select_slot(slot, 0);
|
|
|
|
|
2008-03-26 14:09:52 -06:00
|
|
|
dsor = mmc_omap_calc_divisor(mmc, ios);
|
|
|
|
|
2008-03-26 14:09:22 -06:00
|
|
|
if (ios->vdd != slot->vdd)
|
|
|
|
slot->vdd = ios->vdd;
|
2006-03-29 01:21:00 -07:00
|
|
|
|
2008-03-26 14:09:52 -06:00
|
|
|
clk_enabled = 0;
|
2006-03-29 01:21:00 -07:00
|
|
|
switch (ios->power_mode) {
|
|
|
|
case MMC_POWER_OFF:
|
2008-03-26 14:09:22 -06:00
|
|
|
mmc_omap_set_power(slot, 0, ios->vdd);
|
2006-03-29 01:21:00 -07:00
|
|
|
break;
|
|
|
|
case MMC_POWER_UP:
|
2007-05-01 08:34:16 -06:00
|
|
|
/* Cannot touch dsor yet, just power up MMC */
|
2008-03-26 14:09:22 -06:00
|
|
|
mmc_omap_set_power(slot, 1, ios->vdd);
|
|
|
|
goto exit;
|
2007-05-01 08:34:16 -06:00
|
|
|
case MMC_POWER_ON:
|
2008-03-26 14:09:52 -06:00
|
|
|
mmc_omap_fclk_enable(host, 1);
|
|
|
|
clk_enabled = 1;
|
2006-11-11 15:42:39 -07:00
|
|
|
dsor |= 1 << 11;
|
2006-03-29 01:21:00 -07:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2008-03-26 14:09:22 -06:00
|
|
|
if (slot->bus_mode != ios->bus_mode) {
|
|
|
|
if (slot->pdata->set_bus_mode != NULL)
|
|
|
|
slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
|
|
|
|
ios->bus_mode);
|
|
|
|
slot->bus_mode = ios->bus_mode;
|
|
|
|
}
|
2006-03-29 01:21:00 -07:00
|
|
|
|
|
|
|
/* On insanely high arm_per frequencies something sometimes
|
|
|
|
* goes somehow out of sync, and the POW bit is not being set,
|
|
|
|
* which results in the while loop below getting stuck.
|
|
|
|
* Writing to the CON register twice seems to do the trick. */
|
|
|
|
for (i = 0; i < 2; i++)
|
2006-11-11 15:36:52 -07:00
|
|
|
OMAP_MMC_WRITE(host, CON, dsor);
|
2008-03-26 14:09:22 -06:00
|
|
|
slot->saved_con = dsor;
|
2007-05-01 08:34:16 -06:00
|
|
|
if (ios->power_mode == MMC_POWER_ON) {
|
2008-03-26 14:10:02 -06:00
|
|
|
/* worst case at 400kHz, 80 cycles makes 200 microsecs */
|
|
|
|
int usecs = 250;
|
|
|
|
|
2006-03-29 01:21:00 -07:00
|
|
|
/* Send clock cycles, poll completion */
|
2006-11-11 15:36:52 -07:00
|
|
|
OMAP_MMC_WRITE(host, IE, 0);
|
|
|
|
OMAP_MMC_WRITE(host, STAT, 0xffff);
|
2006-11-11 15:42:39 -07:00
|
|
|
OMAP_MMC_WRITE(host, CMD, 1 << 7);
|
2008-03-26 14:10:02 -06:00
|
|
|
while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
|
|
|
|
udelay(1);
|
|
|
|
usecs--;
|
|
|
|
}
|
2006-11-11 15:36:52 -07:00
|
|
|
OMAP_MMC_WRITE(host, STAT, 1);
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
2008-03-26 14:09:22 -06:00
|
|
|
|
|
|
|
exit:
|
2008-03-26 14:09:52 -06:00
|
|
|
mmc_omap_release_slot(slot, clk_enabled);
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
|
2006-11-12 18:55:30 -07:00
|
|
|
static const struct mmc_host_ops mmc_omap_ops = {
|
2006-03-29 01:21:00 -07:00
|
|
|
.request = mmc_omap_request,
|
|
|
|
.set_ios = mmc_omap_set_ios,
|
|
|
|
};
|
|
|
|
|
2012-11-19 11:23:06 -07:00
|
|
|
static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
|
2006-03-29 01:21:00 -07:00
|
|
|
{
|
2008-03-26 14:08:57 -06:00
|
|
|
struct mmc_omap_slot *slot = NULL;
|
2006-03-29 01:21:00 -07:00
|
|
|
struct mmc_host *mmc;
|
2008-03-26 14:08:57 -06:00
|
|
|
int r;
|
|
|
|
|
|
|
|
mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
|
|
|
|
if (mmc == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
slot = mmc_priv(mmc);
|
|
|
|
slot->host = host;
|
|
|
|
slot->mmc = mmc;
|
|
|
|
slot->id = id;
|
|
|
|
slot->pdata = &host->pdata->slots[id];
|
|
|
|
|
|
|
|
host->slots[id] = slot;
|
|
|
|
|
2008-07-05 17:10:27 -06:00
|
|
|
mmc->caps = 0;
|
2008-12-10 18:37:17 -07:00
|
|
|
if (host->pdata->slots[id].wires >= 4)
|
2008-03-26 14:08:57 -06:00
|
|
|
mmc->caps |= MMC_CAP_4_BIT_DATA;
|
|
|
|
|
|
|
|
mmc->ops = &mmc_omap_ops;
|
|
|
|
mmc->f_min = 400000;
|
|
|
|
|
|
|
|
if (cpu_class_is_omap2())
|
|
|
|
mmc->f_max = 48000000;
|
|
|
|
else
|
|
|
|
mmc->f_max = 24000000;
|
|
|
|
if (host->pdata->max_freq)
|
|
|
|
mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
|
|
|
|
mmc->ocr_avail = slot->pdata->ocr_mask;
|
|
|
|
|
|
|
|
/* Use scatterlist DMA to reduce per-transfer costs.
|
|
|
|
* NOTE max_seg_size assumption that small blocks aren't
|
|
|
|
* normally used (except e.g. for reading SD registers).
|
|
|
|
*/
|
2010-09-09 23:33:59 -06:00
|
|
|
mmc->max_segs = 32;
|
2008-03-26 14:08:57 -06:00
|
|
|
mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
|
|
|
|
mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
|
|
|
|
mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
|
|
|
|
mmc->max_seg_size = mmc->max_req_size;
|
|
|
|
|
|
|
|
r = mmc_add_host(mmc);
|
|
|
|
if (r < 0)
|
|
|
|
goto err_remove_host;
|
|
|
|
|
|
|
|
if (slot->pdata->name != NULL) {
|
|
|
|
r = device_create_file(&mmc->class_dev,
|
|
|
|
&dev_attr_slot_name);
|
|
|
|
if (r < 0)
|
|
|
|
goto err_remove_host;
|
|
|
|
}
|
|
|
|
|
2008-03-26 14:09:08 -06:00
|
|
|
if (slot->pdata->get_cover_state != NULL) {
|
|
|
|
r = device_create_file(&mmc->class_dev,
|
|
|
|
&dev_attr_cover_switch);
|
|
|
|
if (r < 0)
|
|
|
|
goto err_remove_slot_name;
|
|
|
|
|
2008-03-26 14:09:42 -06:00
|
|
|
setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
|
|
|
|
(unsigned long)slot);
|
|
|
|
tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
|
|
|
|
(unsigned long)slot);
|
|
|
|
tasklet_schedule(&slot->cover_tasklet);
|
2008-03-26 14:09:08 -06:00
|
|
|
}
|
|
|
|
|
2008-03-26 14:08:57 -06:00
|
|
|
return 0;
|
|
|
|
|
2008-03-26 14:09:08 -06:00
|
|
|
err_remove_slot_name:
|
|
|
|
if (slot->pdata->name != NULL)
|
|
|
|
device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
|
2008-03-26 14:08:57 -06:00
|
|
|
err_remove_host:
|
|
|
|
mmc_remove_host(mmc);
|
|
|
|
mmc_free_host(mmc);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
|
|
|
|
{
|
|
|
|
struct mmc_host *mmc = slot->mmc;
|
|
|
|
|
|
|
|
if (slot->pdata->name != NULL)
|
|
|
|
device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
|
2008-03-26 14:09:08 -06:00
|
|
|
if (slot->pdata->get_cover_state != NULL)
|
|
|
|
device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
|
|
|
|
|
2008-03-26 14:09:42 -06:00
|
|
|
tasklet_kill(&slot->cover_tasklet);
|
|
|
|
del_timer_sync(&slot->cover_timer);
|
2012-05-08 05:35:33 -06:00
|
|
|
flush_workqueue(slot->host->mmc_omap_wq);
|
2008-03-26 14:08:57 -06:00
|
|
|
|
|
|
|
mmc_remove_host(mmc);
|
|
|
|
mmc_free_host(mmc);
|
|
|
|
}
|
|
|
|
|
2012-11-19 11:23:06 -07:00
|
|
|
static int mmc_omap_probe(struct platform_device *pdev)
|
2008-03-26 14:08:57 -06:00
|
|
|
{
|
|
|
|
struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
|
2006-03-29 01:21:00 -07:00
|
|
|
struct mmc_omap_host *host = NULL;
|
2006-11-11 15:39:20 -07:00
|
|
|
struct resource *res;
|
2012-04-21 15:35:42 -06:00
|
|
|
dma_cap_mask_t mask;
|
|
|
|
unsigned sig;
|
2008-03-26 14:08:57 -06:00
|
|
|
int i, ret = 0;
|
2006-07-01 12:56:44 -06:00
|
|
|
int irq;
|
2006-11-11 15:39:20 -07:00
|
|
|
|
2008-03-26 14:08:57 -06:00
|
|
|
if (pdata == NULL) {
|
2006-11-11 15:39:20 -07:00
|
|
|
dev_err(&pdev->dev, "platform data missing\n");
|
|
|
|
return -ENXIO;
|
|
|
|
}
|
2008-03-26 14:08:57 -06:00
|
|
|
if (pdata->nr_slots == 0) {
|
|
|
|
dev_err(&pdev->dev, "no slots\n");
|
|
|
|
return -ENXIO;
|
|
|
|
}
|
2006-11-11 15:39:20 -07:00
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2006-07-01 12:56:44 -06:00
|
|
|
irq = platform_get_irq(pdev, 0);
|
2006-11-11 15:39:20 -07:00
|
|
|
if (res == NULL || irq < 0)
|
2006-07-01 12:56:44 -06:00
|
|
|
return -ENXIO;
|
2006-03-29 01:21:00 -07:00
|
|
|
|
2011-03-22 17:34:41 -06:00
|
|
|
res = request_mem_region(res->start, resource_size(res),
|
2008-03-26 14:08:57 -06:00
|
|
|
pdev->name);
|
2006-11-11 15:39:20 -07:00
|
|
|
if (res == NULL)
|
2006-03-29 01:21:00 -07:00
|
|
|
return -EBUSY;
|
|
|
|
|
2008-03-26 14:08:57 -06:00
|
|
|
host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
|
|
|
|
if (host == NULL) {
|
2006-03-29 01:21:00 -07:00
|
|
|
ret = -ENOMEM;
|
2006-11-11 15:39:20 -07:00
|
|
|
goto err_free_mem_region;
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
|
2008-03-26 14:09:58 -06:00
|
|
|
INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
|
|
|
|
INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
|
|
|
|
|
2008-03-26 14:09:48 -06:00
|
|
|
INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
|
|
|
|
setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
|
|
|
|
(unsigned long) host);
|
2008-03-26 14:09:29 -06:00
|
|
|
|
2008-03-26 14:09:52 -06:00
|
|
|
spin_lock_init(&host->clk_lock);
|
|
|
|
setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
|
|
|
|
|
2006-03-29 01:21:00 -07:00
|
|
|
spin_lock_init(&host->dma_lock);
|
2008-03-26 14:08:57 -06:00
|
|
|
spin_lock_init(&host->slot_lock);
|
|
|
|
init_waitqueue_head(&host->slot_wq);
|
|
|
|
|
|
|
|
host->pdata = pdata;
|
|
|
|
host->dev = &pdev->dev;
|
|
|
|
platform_set_drvdata(pdev, host);
|
|
|
|
|
2006-03-29 01:21:00 -07:00
|
|
|
host->id = pdev->id;
|
2006-11-11 15:39:20 -07:00
|
|
|
host->mem_res = res;
|
2006-07-01 12:56:44 -06:00
|
|
|
host->irq = irq;
|
2008-03-26 14:08:57 -06:00
|
|
|
host->use_dma = 1;
|
|
|
|
host->irq = irq;
|
|
|
|
host->phys_base = host->mem_res->start;
|
2011-03-22 17:34:41 -06:00
|
|
|
host->virt_base = ioremap(res->start, resource_size(res));
|
2008-09-04 07:07:22 -06:00
|
|
|
if (!host->virt_base)
|
|
|
|
goto err_ioremap;
|
2008-03-26 14:08:57 -06:00
|
|
|
|
2009-01-23 12:03:37 -07:00
|
|
|
host->iclk = clk_get(&pdev->dev, "ick");
|
2009-12-14 19:01:24 -07:00
|
|
|
if (IS_ERR(host->iclk)) {
|
|
|
|
ret = PTR_ERR(host->iclk);
|
2009-01-23 12:03:37 -07:00
|
|
|
goto err_free_mmc_host;
|
2009-12-14 19:01:24 -07:00
|
|
|
}
|
2009-01-23 12:03:37 -07:00
|
|
|
clk_enable(host->iclk);
|
2006-03-29 01:21:00 -07:00
|
|
|
|
2009-01-19 13:53:30 -07:00
|
|
|
host->fclk = clk_get(&pdev->dev, "fck");
|
2006-03-29 01:21:00 -07:00
|
|
|
if (IS_ERR(host->fclk)) {
|
|
|
|
ret = PTR_ERR(host->fclk);
|
2006-11-11 15:39:20 -07:00
|
|
|
goto err_free_iclk;
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
|
2012-04-21 15:35:42 -06:00
|
|
|
dma_cap_zero(mask);
|
|
|
|
dma_cap_set(DMA_SLAVE, mask);
|
|
|
|
|
|
|
|
host->dma_tx_burst = -1;
|
|
|
|
host->dma_rx_burst = -1;
|
|
|
|
|
|
|
|
if (cpu_is_omap24xx())
|
|
|
|
sig = host->id == 0 ? OMAP24XX_DMA_MMC1_TX : OMAP24XX_DMA_MMC2_TX;
|
|
|
|
else
|
|
|
|
sig = host->id == 0 ? OMAP_DMA_MMC_TX : OMAP_DMA_MMC2_TX;
|
|
|
|
host->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
|
|
|
|
#if 0
|
|
|
|
if (!host->dma_tx) {
|
|
|
|
dev_err(host->dev, "unable to obtain TX DMA engine channel %u\n",
|
|
|
|
sig);
|
|
|
|
goto err_dma;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
if (!host->dma_tx)
|
|
|
|
dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n",
|
|
|
|
sig);
|
|
|
|
#endif
|
|
|
|
if (cpu_is_omap24xx())
|
|
|
|
sig = host->id == 0 ? OMAP24XX_DMA_MMC1_RX : OMAP24XX_DMA_MMC2_RX;
|
|
|
|
else
|
|
|
|
sig = host->id == 0 ? OMAP_DMA_MMC_RX : OMAP_DMA_MMC2_RX;
|
|
|
|
host->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
|
|
|
|
#if 0
|
|
|
|
if (!host->dma_rx) {
|
|
|
|
dev_err(host->dev, "unable to obtain RX DMA engine channel %u\n",
|
|
|
|
sig);
|
|
|
|
goto err_dma;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
if (!host->dma_rx)
|
|
|
|
dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n",
|
|
|
|
sig);
|
|
|
|
#endif
|
|
|
|
|
2008-03-26 14:08:57 -06:00
|
|
|
ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
|
|
|
|
if (ret)
|
2012-04-21 15:35:42 -06:00
|
|
|
goto err_free_dma;
|
2006-09-24 03:44:09 -06:00
|
|
|
|
2008-03-26 14:08:57 -06:00
|
|
|
if (pdata->init != NULL) {
|
|
|
|
ret = pdata->init(&pdev->dev);
|
|
|
|
if (ret < 0)
|
|
|
|
goto err_free_irq;
|
|
|
|
}
|
2006-03-29 01:21:00 -07:00
|
|
|
|
2008-03-26 14:08:57 -06:00
|
|
|
host->nr_slots = pdata->nr_slots;
|
2012-06-06 07:47:49 -06:00
|
|
|
host->reg_shift = (cpu_is_omap7xx() ? 1 : 2);
|
2012-06-06 07:45:50 -06:00
|
|
|
|
|
|
|
host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
|
|
|
|
if (!host->mmc_omap_wq)
|
|
|
|
goto err_plat_cleanup;
|
|
|
|
|
2008-03-26 14:08:57 -06:00
|
|
|
for (i = 0; i < pdata->nr_slots; i++) {
|
|
|
|
ret = mmc_omap_new_slot(host, i);
|
|
|
|
if (ret < 0) {
|
|
|
|
while (--i >= 0)
|
|
|
|
mmc_omap_remove_slot(host->slots[i]);
|
2006-03-29 01:21:00 -07:00
|
|
|
|
2012-06-06 07:45:50 -06:00
|
|
|
goto err_destroy_wq;
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2012-06-06 07:45:50 -06:00
|
|
|
err_destroy_wq:
|
|
|
|
destroy_workqueue(host->mmc_omap_wq);
|
2008-03-26 14:08:57 -06:00
|
|
|
err_plat_cleanup:
|
|
|
|
if (pdata->cleanup)
|
|
|
|
pdata->cleanup(&pdev->dev);
|
|
|
|
err_free_irq:
|
|
|
|
free_irq(host->irq, host);
|
2012-04-21 15:35:42 -06:00
|
|
|
err_free_dma:
|
|
|
|
if (host->dma_tx)
|
|
|
|
dma_release_channel(host->dma_tx);
|
|
|
|
if (host->dma_rx)
|
|
|
|
dma_release_channel(host->dma_rx);
|
2006-11-11 15:39:20 -07:00
|
|
|
clk_put(host->fclk);
|
|
|
|
err_free_iclk:
|
2009-12-14 19:01:24 -07:00
|
|
|
clk_disable(host->iclk);
|
|
|
|
clk_put(host->iclk);
|
2006-11-11 15:39:20 -07:00
|
|
|
err_free_mmc_host:
|
2008-09-04 07:07:22 -06:00
|
|
|
iounmap(host->virt_base);
|
|
|
|
err_ioremap:
|
2008-03-26 14:08:57 -06:00
|
|
|
kfree(host);
|
2006-11-11 15:39:20 -07:00
|
|
|
err_free_mem_region:
|
2011-03-22 17:34:41 -06:00
|
|
|
release_mem_region(res->start, resource_size(res));
|
2006-03-29 01:21:00 -07:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-05-08 05:35:34 -06:00
|
|
|
static int __devexit mmc_omap_remove(struct platform_device *pdev)
|
2006-03-29 01:21:00 -07:00
|
|
|
{
|
|
|
|
struct mmc_omap_host *host = platform_get_drvdata(pdev);
|
2008-03-26 14:08:57 -06:00
|
|
|
int i;
|
2006-03-29 01:21:00 -07:00
|
|
|
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
|
2006-11-11 15:39:20 -07:00
|
|
|
BUG_ON(host == NULL);
|
|
|
|
|
2008-03-26 14:08:57 -06:00
|
|
|
for (i = 0; i < host->nr_slots; i++)
|
|
|
|
mmc_omap_remove_slot(host->slots[i]);
|
|
|
|
|
|
|
|
if (host->pdata->cleanup)
|
|
|
|
host->pdata->cleanup(&pdev->dev);
|
2006-11-11 15:39:20 -07:00
|
|
|
|
2009-01-23 12:03:37 -07:00
|
|
|
mmc_omap_fclk_enable(host, 0);
|
2009-11-11 15:26:43 -07:00
|
|
|
free_irq(host->irq, host);
|
2009-01-23 12:03:37 -07:00
|
|
|
clk_put(host->fclk);
|
|
|
|
clk_disable(host->iclk);
|
|
|
|
clk_put(host->iclk);
|
2006-03-29 01:21:00 -07:00
|
|
|
|
2012-04-21 15:35:42 -06:00
|
|
|
if (host->dma_tx)
|
|
|
|
dma_release_channel(host->dma_tx);
|
|
|
|
if (host->dma_rx)
|
|
|
|
dma_release_channel(host->dma_rx);
|
|
|
|
|
2008-09-04 07:07:22 -06:00
|
|
|
iounmap(host->virt_base);
|
2006-03-29 01:21:00 -07:00
|
|
|
release_mem_region(pdev->resource[0].start,
|
2006-11-11 15:39:20 -07:00
|
|
|
pdev->resource[0].end - pdev->resource[0].start + 1);
|
2012-05-08 05:35:33 -06:00
|
|
|
destroy_workqueue(host->mmc_omap_wq);
|
2006-11-11 15:39:20 -07:00
|
|
|
|
2008-03-26 14:08:57 -06:00
|
|
|
kfree(host);
|
2006-03-29 01:21:00 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
|
|
|
|
{
|
2008-03-26 14:08:57 -06:00
|
|
|
int i, ret = 0;
|
2006-03-29 01:21:00 -07:00
|
|
|
struct mmc_omap_host *host = platform_get_drvdata(pdev);
|
|
|
|
|
2008-03-26 14:08:57 -06:00
|
|
|
if (host == NULL || host->suspended)
|
2006-03-29 01:21:00 -07:00
|
|
|
return 0;
|
|
|
|
|
2008-03-26 14:08:57 -06:00
|
|
|
for (i = 0; i < host->nr_slots; i++) {
|
|
|
|
struct mmc_omap_slot *slot;
|
|
|
|
|
|
|
|
slot = host->slots[i];
|
2010-05-26 15:42:08 -06:00
|
|
|
ret = mmc_suspend_host(slot->mmc);
|
2008-03-26 14:08:57 -06:00
|
|
|
if (ret < 0) {
|
|
|
|
while (--i >= 0) {
|
|
|
|
slot = host->slots[i];
|
|
|
|
mmc_resume_host(slot->mmc);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
2008-03-26 14:08:57 -06:00
|
|
|
host->suspended = 1;
|
|
|
|
return 0;
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int mmc_omap_resume(struct platform_device *pdev)
|
|
|
|
{
|
2008-03-26 14:08:57 -06:00
|
|
|
int i, ret = 0;
|
2006-03-29 01:21:00 -07:00
|
|
|
struct mmc_omap_host *host = platform_get_drvdata(pdev);
|
|
|
|
|
2008-03-26 14:08:57 -06:00
|
|
|
if (host == NULL || !host->suspended)
|
2006-03-29 01:21:00 -07:00
|
|
|
return 0;
|
|
|
|
|
2008-03-26 14:08:57 -06:00
|
|
|
for (i = 0; i < host->nr_slots; i++) {
|
|
|
|
struct mmc_omap_slot *slot;
|
|
|
|
slot = host->slots[i];
|
|
|
|
ret = mmc_resume_host(slot->mmc);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2006-03-29 01:21:00 -07:00
|
|
|
|
2008-03-26 14:08:57 -06:00
|
|
|
host->suspended = 0;
|
|
|
|
}
|
|
|
|
return 0;
|
2006-03-29 01:21:00 -07:00
|
|
|
}
|
|
|
|
#else
|
|
|
|
#define mmc_omap_suspend NULL
|
|
|
|
#define mmc_omap_resume NULL
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static struct platform_driver mmc_omap_driver = {
|
2012-05-08 05:35:34 -06:00
|
|
|
.probe = mmc_omap_probe,
|
2012-11-19 11:20:26 -07:00
|
|
|
.remove = mmc_omap_remove,
|
2006-03-29 01:21:00 -07:00
|
|
|
.suspend = mmc_omap_suspend,
|
|
|
|
.resume = mmc_omap_resume,
|
|
|
|
.driver = {
|
|
|
|
.name = DRIVER_NAME,
|
2008-04-15 15:34:28 -06:00
|
|
|
.owner = THIS_MODULE,
|
2006-03-29 01:21:00 -07:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-05-08 05:35:35 -06:00
|
|
|
module_platform_driver(mmc_omap_driver);
|
2006-03-29 01:21:00 -07:00
|
|
|
MODULE_DESCRIPTION("OMAP Multimedia Card driver");
|
|
|
|
MODULE_LICENSE("GPL");
|
2008-04-15 15:34:28 -06:00
|
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|
2011-12-29 15:09:01 -07:00
|
|
|
MODULE_AUTHOR("Juha Yrjölä");
|