2005-04-16 16:20:36 -06:00
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/*
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* $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
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*
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* PCI Bus Services, see include/linux/pci.h for further explanation.
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*
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* Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
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* David Mosberger-Tang
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*
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* Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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2007-04-26 01:12:06 -06:00
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#include <linux/pm.h>
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2005-04-16 16:20:36 -06:00
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#include <linux/module.h>
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#include <linux/spinlock.h>
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2005-10-30 16:03:48 -07:00
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#include <linux/string.h>
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2007-08-13 06:53:14 -06:00
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#include <linux/log2.h>
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2005-04-16 16:20:36 -06:00
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#include <asm/dma.h> /* isa_dma_bridge_buggy */
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2005-04-07 23:53:31 -06:00
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#include "pci.h"
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2005-04-16 16:20:36 -06:00
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2006-07-12 09:59:00 -06:00
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unsigned int pci_pm_d3_delay = 10;
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2005-04-16 16:20:36 -06:00
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2007-10-11 14:57:27 -06:00
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#ifdef CONFIG_PCI_DOMAINS
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int pci_domains_supported = 1;
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#endif
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2007-02-05 17:36:06 -07:00
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#define DEFAULT_CARDBUS_IO_SIZE (256)
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#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
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/* pci=cbmemsize=nnM,cbiosize=nn can override this */
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unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
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unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
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2005-04-16 16:20:36 -06:00
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/**
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* pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
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* @bus: pointer to PCI bus structure to search
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*
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* Given a PCI bus, returns the highest PCI bus number present in the set
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* including the given PCI bus and its list of child PCI buses.
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*/
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2007-03-26 23:53:30 -06:00
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unsigned char pci_bus_max_busnr(struct pci_bus* bus)
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2005-04-16 16:20:36 -06:00
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{
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struct list_head *tmp;
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unsigned char max, n;
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2006-01-17 17:56:56 -07:00
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max = bus->subordinate;
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2005-04-16 16:20:36 -06:00
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list_for_each(tmp, &bus->children) {
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n = pci_bus_max_busnr(pci_bus_b(tmp));
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if(n > max)
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max = n;
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}
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return max;
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}
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2006-01-17 17:56:56 -07:00
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EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
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2005-04-16 16:20:36 -06:00
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2006-01-17 17:56:56 -07:00
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#if 0
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2005-04-16 16:20:36 -06:00
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/**
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* pci_max_busnr - returns maximum PCI bus number
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*
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* Returns the highest PCI bus number present in the system global list of
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* PCI buses.
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*/
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unsigned char __devinit
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pci_max_busnr(void)
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{
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struct pci_bus *bus = NULL;
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unsigned char max, n;
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max = 0;
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while ((bus = pci_find_next_bus(bus)) != NULL) {
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n = pci_bus_max_busnr(bus);
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if(n > max)
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max = n;
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}
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return max;
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}
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2005-12-21 17:08:52 -07:00
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#endif /* 0 */
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2006-11-22 00:26:18 -07:00
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#define PCI_FIND_CAP_TTL 48
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static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
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u8 pos, int cap, int *ttl)
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[PATCH] PCI: add pci_find_next_capability()
Some devices have more than one capability of the same type. For
example, the PCI header for the PathScale InfiniPath looks like:
04:01.0 InfiniBand: Unknown device 1fc1:000d (rev 02)
Subsystem: Unknown device 1fc1:000d
Flags: bus master, fast devsel, latency 0, IRQ 193
Memory at fea00000 (64-bit, non-prefetchable) [size=2M]
Capabilities: [c0] HyperTransport: Slave or Primary Interface
Capabilities: [f8] HyperTransport: Interrupt Discovery and Configuration
There are _two_ HyperTransport capabilities, and the PathScale driver
wants to look at both of them.
The current pci_find_capability() API doesn't work for this, since it
only allows us to get to the first capability of a given type. The
patch below introduces a new pci_find_next_capability(), which can be
used in a loop like
for (pos = pci_find_capability(pdev, <ID>);
pos;
pos = pci_find_next_capability(pdev, pos, <ID>)) {
/* ... */
}
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Signed-off-by: Matthew Wilcox <matthew@wil.cx>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2005-10-28 18:35:34 -06:00
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{
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u8 id;
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2006-11-22 00:26:18 -07:00
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while ((*ttl)--) {
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[PATCH] PCI: add pci_find_next_capability()
Some devices have more than one capability of the same type. For
example, the PCI header for the PathScale InfiniPath looks like:
04:01.0 InfiniBand: Unknown device 1fc1:000d (rev 02)
Subsystem: Unknown device 1fc1:000d
Flags: bus master, fast devsel, latency 0, IRQ 193
Memory at fea00000 (64-bit, non-prefetchable) [size=2M]
Capabilities: [c0] HyperTransport: Slave or Primary Interface
Capabilities: [f8] HyperTransport: Interrupt Discovery and Configuration
There are _two_ HyperTransport capabilities, and the PathScale driver
wants to look at both of them.
The current pci_find_capability() API doesn't work for this, since it
only allows us to get to the first capability of a given type. The
patch below introduces a new pci_find_next_capability(), which can be
used in a loop like
for (pos = pci_find_capability(pdev, <ID>);
pos;
pos = pci_find_next_capability(pdev, pos, <ID>)) {
/* ... */
}
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Signed-off-by: Matthew Wilcox <matthew@wil.cx>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2005-10-28 18:35:34 -06:00
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pci_bus_read_config_byte(bus, devfn, pos, &pos);
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if (pos < 0x40)
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break;
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pos &= ~3;
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pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
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&id);
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if (id == 0xff)
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break;
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if (id == cap)
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return pos;
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pos += PCI_CAP_LIST_NEXT;
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}
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return 0;
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}
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2006-11-22 00:26:18 -07:00
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static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
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u8 pos, int cap)
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{
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int ttl = PCI_FIND_CAP_TTL;
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return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
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}
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[PATCH] PCI: add pci_find_next_capability()
Some devices have more than one capability of the same type. For
example, the PCI header for the PathScale InfiniPath looks like:
04:01.0 InfiniBand: Unknown device 1fc1:000d (rev 02)
Subsystem: Unknown device 1fc1:000d
Flags: bus master, fast devsel, latency 0, IRQ 193
Memory at fea00000 (64-bit, non-prefetchable) [size=2M]
Capabilities: [c0] HyperTransport: Slave or Primary Interface
Capabilities: [f8] HyperTransport: Interrupt Discovery and Configuration
There are _two_ HyperTransport capabilities, and the PathScale driver
wants to look at both of them.
The current pci_find_capability() API doesn't work for this, since it
only allows us to get to the first capability of a given type. The
patch below introduces a new pci_find_next_capability(), which can be
used in a loop like
for (pos = pci_find_capability(pdev, <ID>);
pos;
pos = pci_find_next_capability(pdev, pos, <ID>)) {
/* ... */
}
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Signed-off-by: Matthew Wilcox <matthew@wil.cx>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2005-10-28 18:35:34 -06:00
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int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
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{
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return __pci_find_next_cap(dev->bus, dev->devfn,
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pos + PCI_CAP_LIST_NEXT, cap);
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}
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EXPORT_SYMBOL_GPL(pci_find_next_capability);
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2006-11-22 00:26:16 -07:00
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static int __pci_bus_find_cap_start(struct pci_bus *bus,
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unsigned int devfn, u8 hdr_type)
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2005-04-16 16:20:36 -06:00
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{
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u16 status;
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pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
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if (!(status & PCI_STATUS_CAP_LIST))
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return 0;
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switch (hdr_type) {
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case PCI_HEADER_TYPE_NORMAL:
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case PCI_HEADER_TYPE_BRIDGE:
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2006-11-22 00:26:16 -07:00
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return PCI_CAPABILITY_LIST;
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2005-04-16 16:20:36 -06:00
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case PCI_HEADER_TYPE_CARDBUS:
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2006-11-22 00:26:16 -07:00
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return PCI_CB_CAPABILITY_LIST;
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2005-04-16 16:20:36 -06:00
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default:
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return 0;
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}
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2006-11-22 00:26:16 -07:00
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return 0;
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2005-04-16 16:20:36 -06:00
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}
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/**
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* pci_find_capability - query for devices' capabilities
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* @dev: PCI device to query
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* @cap: capability code
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*
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* Tell if a device supports a given PCI capability.
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* Returns the address of the requested capability structure within the
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* device's PCI configuration space or 0 in case the device does not
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* support it. Possible values for @cap:
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*
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* %PCI_CAP_ID_PM Power Management
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* %PCI_CAP_ID_AGP Accelerated Graphics Port
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* %PCI_CAP_ID_VPD Vital Product Data
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* %PCI_CAP_ID_SLOTID Slot Identification
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* %PCI_CAP_ID_MSI Message Signalled Interrupts
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* %PCI_CAP_ID_CHSWP CompactPCI HotSwap
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* %PCI_CAP_ID_PCIX PCI-X
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* %PCI_CAP_ID_EXP PCI Express
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*/
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int pci_find_capability(struct pci_dev *dev, int cap)
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{
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2006-11-22 00:26:16 -07:00
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int pos;
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pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
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if (pos)
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pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
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return pos;
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2005-04-16 16:20:36 -06:00
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}
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/**
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* pci_bus_find_capability - query for devices' capabilities
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* @bus: the PCI bus to query
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* @devfn: PCI device to query
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* @cap: capability code
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*
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* Like pci_find_capability() but works for pci devices that do not have a
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* pci_dev structure set up yet.
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*
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* Returns the address of the requested capability structure within the
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* device's PCI configuration space or 0 in case the device does not
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* support it.
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*/
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int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
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{
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2006-11-22 00:26:16 -07:00
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int pos;
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2005-04-16 16:20:36 -06:00
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u8 hdr_type;
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pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
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2006-11-22 00:26:16 -07:00
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pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
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if (pos)
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pos = __pci_find_next_cap(bus, devfn, pos, cap);
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return pos;
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2005-04-16 16:20:36 -06:00
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}
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/**
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* pci_find_ext_capability - Find an extended capability
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* @dev: PCI device to query
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* @cap: capability code
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*
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* Returns the address of the requested extended capability structure
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* within the device's PCI configuration space or 0 if the device does
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* not support it. Possible values for @cap:
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*
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* %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
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* %PCI_EXT_CAP_ID_VC Virtual Channel
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* %PCI_EXT_CAP_ID_DSN Device Serial Number
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* %PCI_EXT_CAP_ID_PWR Power Budgeting
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*/
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int pci_find_ext_capability(struct pci_dev *dev, int cap)
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{
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u32 header;
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int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
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int pos = 0x100;
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if (dev->cfg_size <= 256)
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return 0;
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if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
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return 0;
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/*
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* If we have no capabilities, this is indicated by cap ID,
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* cap version and next pointer all being 0.
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*/
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if (header == 0)
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return 0;
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while (ttl-- > 0) {
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if (PCI_EXT_CAP_ID(header) == cap)
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return pos;
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pos = PCI_EXT_CAP_NEXT(header);
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if (pos < 0x100)
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break;
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if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
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break;
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}
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return 0;
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}
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2006-05-23 04:10:01 -06:00
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EXPORT_SYMBOL_GPL(pci_find_ext_capability);
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2005-04-16 16:20:36 -06:00
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2006-11-22 00:26:18 -07:00
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static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
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{
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int rc, ttl = PCI_FIND_CAP_TTL;
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u8 cap, mask;
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if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
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mask = HT_3BIT_CAP_MASK;
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else
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mask = HT_5BIT_CAP_MASK;
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pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
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PCI_CAP_ID_HT, &ttl);
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while (pos) {
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rc = pci_read_config_byte(dev, pos + 3, &cap);
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if (rc != PCIBIOS_SUCCESSFUL)
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return 0;
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if ((cap & mask) == ht_cap)
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return pos;
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2007-01-11 00:15:29 -07:00
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pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
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pos + PCI_CAP_LIST_NEXT,
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2006-11-22 00:26:18 -07:00
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PCI_CAP_ID_HT, &ttl);
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}
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return 0;
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}
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/**
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* pci_find_next_ht_capability - query a device's Hypertransport capabilities
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* @dev: PCI device to query
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* @pos: Position from which to continue searching
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* @ht_cap: Hypertransport capability code
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*
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* To be used in conjunction with pci_find_ht_capability() to search for
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* all capabilities matching @ht_cap. @pos should always be a value returned
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* from pci_find_ht_capability().
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*
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* NB. To be 100% safe against broken PCI devices, the caller should take
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* steps to avoid an infinite loop.
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*/
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int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
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{
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|
|
return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_find_ht_capability - query a device's Hypertransport capabilities
|
|
|
|
* @dev: PCI device to query
|
|
|
|
* @ht_cap: Hypertransport capability code
|
|
|
|
*
|
|
|
|
* Tell if a device supports a given Hypertransport capability.
|
|
|
|
* Returns an address within the device's PCI configuration space
|
|
|
|
* or 0 in case the device does not support the request capability.
|
|
|
|
* The address points to the PCI capability, of type PCI_CAP_ID_HT,
|
|
|
|
* which has a Hypertransport capability matching @ht_cap.
|
|
|
|
*/
|
|
|
|
int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
|
|
|
|
{
|
|
|
|
int pos;
|
|
|
|
|
|
|
|
pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
|
|
|
|
if (pos)
|
|
|
|
pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
|
|
|
|
|
|
|
|
return pos;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(pci_find_ht_capability);
|
|
|
|
|
2007-10-23 20:45:08 -06:00
|
|
|
void pcie_wait_pending_transaction(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int pos;
|
|
|
|
u16 reg16;
|
|
|
|
|
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
|
|
|
|
if (!pos)
|
|
|
|
return;
|
|
|
|
while (1) {
|
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, ®16);
|
|
|
|
if (!(reg16 & PCI_EXP_DEVSTA_TRPND))
|
|
|
|
break;
|
|
|
|
cpu_relax();
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(pcie_wait_pending_transaction);
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/**
|
|
|
|
* pci_find_parent_resource - return resource region of parent bus of given region
|
|
|
|
* @dev: PCI device structure contains resources to be searched
|
|
|
|
* @res: child resource record for which parent is sought
|
|
|
|
*
|
|
|
|
* For given resource region of given device, return the resource
|
|
|
|
* region of parent bus the given region is contained in or where
|
|
|
|
* it should be allocated from.
|
|
|
|
*/
|
|
|
|
struct resource *
|
|
|
|
pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
|
|
|
|
{
|
|
|
|
const struct pci_bus *bus = dev->bus;
|
|
|
|
int i;
|
|
|
|
struct resource *best = NULL;
|
|
|
|
|
|
|
|
for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
|
|
|
|
struct resource *r = bus->resource[i];
|
|
|
|
if (!r)
|
|
|
|
continue;
|
|
|
|
if (res->start && !(res->start >= r->start && res->end <= r->end))
|
|
|
|
continue; /* Not contained */
|
|
|
|
if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
|
|
|
|
continue; /* Wrong type */
|
|
|
|
if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
|
|
|
|
return r; /* Exact match */
|
|
|
|
if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
|
|
|
|
best = r; /* Approximating prefetchable by non-prefetchable */
|
|
|
|
}
|
|
|
|
return best;
|
|
|
|
}
|
|
|
|
|
2005-07-27 08:19:44 -06:00
|
|
|
/**
|
|
|
|
* pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
|
|
|
|
* @dev: PCI device to have its BARs restored
|
|
|
|
*
|
|
|
|
* Restore the BAR values for a given device, so as to make it
|
|
|
|
* accessible by its driver.
|
|
|
|
*/
|
2007-10-26 19:06:22 -06:00
|
|
|
static void
|
2005-07-27 08:19:44 -06:00
|
|
|
pci_restore_bars(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int i, numres;
|
|
|
|
|
|
|
|
switch (dev->hdr_type) {
|
|
|
|
case PCI_HEADER_TYPE_NORMAL:
|
|
|
|
numres = 6;
|
|
|
|
break;
|
|
|
|
case PCI_HEADER_TYPE_BRIDGE:
|
|
|
|
numres = 2;
|
|
|
|
break;
|
|
|
|
case PCI_HEADER_TYPE_CARDBUS:
|
|
|
|
numres = 1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* Should never get here, but just in case... */
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < numres; i ++)
|
|
|
|
pci_update_resource(dev, &dev->resource[i], i);
|
|
|
|
}
|
|
|
|
|
2005-10-23 12:57:38 -06:00
|
|
|
int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/**
|
|
|
|
* pci_set_power_state - Set the power state of a PCI device
|
|
|
|
* @dev: PCI device to be suspended
|
|
|
|
* @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
|
|
|
|
*
|
|
|
|
* Transition a device to a new power state, using the Power Management
|
|
|
|
* Capabilities in the device's config space.
|
|
|
|
*
|
|
|
|
* RETURN VALUE:
|
|
|
|
* -EINVAL if trying to enter a lower state than we're already in.
|
|
|
|
* 0 if we're already in the requested state.
|
|
|
|
* -EIO if device does not support PCI PM.
|
|
|
|
* 0 if we can successfully change the power state.
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
pci_set_power_state(struct pci_dev *dev, pci_power_t state)
|
|
|
|
{
|
2005-07-27 08:19:44 -06:00
|
|
|
int pm, need_restore = 0;
|
2005-04-16 16:20:36 -06:00
|
|
|
u16 pmcsr, pmc;
|
|
|
|
|
|
|
|
/* bound the state we're entering */
|
|
|
|
if (state > PCI_D3hot)
|
|
|
|
state = PCI_D3hot;
|
|
|
|
|
2007-01-16 04:17:13 -07:00
|
|
|
/*
|
|
|
|
* If the device or the parent bridge can't support PCI PM, ignore
|
|
|
|
* the request if we're doing anything besides putting it into D0
|
|
|
|
* (which would only happen on boot).
|
|
|
|
*/
|
|
|
|
if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
|
|
|
|
return 0;
|
|
|
|
|
2007-07-09 12:55:58 -06:00
|
|
|
/* find PCI PM capability in list */
|
|
|
|
pm = pci_find_capability(dev, PCI_CAP_ID_PM);
|
|
|
|
|
|
|
|
/* abort if the device doesn't support PM capabilities */
|
|
|
|
if (!pm)
|
|
|
|
return -EIO;
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/* Validate current state:
|
|
|
|
* Can enter D0 from any state, but if we can only go deeper
|
|
|
|
* to sleep if we're already in a low power state
|
|
|
|
*/
|
2006-03-23 02:38:34 -07:00
|
|
|
if (state != PCI_D0 && dev->current_state > state) {
|
|
|
|
printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
|
|
|
|
__FUNCTION__, pci_name(dev), state, dev->current_state);
|
2005-04-16 16:20:36 -06:00
|
|
|
return -EINVAL;
|
2006-03-23 02:38:34 -07:00
|
|
|
} else if (dev->current_state == state)
|
2005-04-16 16:20:36 -06:00
|
|
|
return 0; /* we're already there */
|
|
|
|
|
2006-07-12 09:59:00 -06:00
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
|
2005-08-17 16:32:19 -06:00
|
|
|
if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
|
2005-04-16 16:20:36 -06:00
|
|
|
printk(KERN_DEBUG
|
|
|
|
"PCI: %s has unsupported PM cap regs version (%u)\n",
|
|
|
|
pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* check if this device supports the desired state */
|
2005-08-17 16:32:19 -06:00
|
|
|
if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
|
|
|
|
return -EIO;
|
|
|
|
else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
|
|
|
|
return -EIO;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2005-07-27 08:19:44 -06:00
|
|
|
pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
|
|
|
|
|
2005-09-14 07:52:42 -06:00
|
|
|
/* If we're (effectively) in D3, force entire word to 0.
|
2005-04-16 16:20:36 -06:00
|
|
|
* This doesn't affect PME_Status, disables PME_En, and
|
|
|
|
* sets PowerState to 0.
|
|
|
|
*/
|
2005-09-14 07:52:42 -06:00
|
|
|
switch (dev->current_state) {
|
2005-09-28 15:50:51 -06:00
|
|
|
case PCI_D0:
|
|
|
|
case PCI_D1:
|
|
|
|
case PCI_D2:
|
|
|
|
pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
|
|
|
|
pmcsr |= state;
|
|
|
|
break;
|
2005-09-14 07:52:42 -06:00
|
|
|
case PCI_UNKNOWN: /* Boot-up */
|
|
|
|
if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
|
|
|
|
&& !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
|
2005-07-27 08:19:44 -06:00
|
|
|
need_restore = 1;
|
2005-09-14 07:52:42 -06:00
|
|
|
/* Fall-through: force to D0 */
|
|
|
|
default:
|
2005-09-28 15:50:51 -06:00
|
|
|
pmcsr = 0;
|
2005-09-14 07:52:42 -06:00
|
|
|
break;
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/* enter specified state */
|
|
|
|
pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
|
|
|
|
|
|
|
|
/* Mandatory power management transition delays */
|
|
|
|
/* see PCI PM 1.1 5.6.1 table 18 */
|
|
|
|
if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
|
2006-07-12 09:59:00 -06:00
|
|
|
msleep(pci_pm_d3_delay);
|
2005-04-16 16:20:36 -06:00
|
|
|
else if (state == PCI_D2 || dev->current_state == PCI_D2)
|
|
|
|
udelay(200);
|
|
|
|
|
2005-03-18 22:16:18 -07:00
|
|
|
/*
|
|
|
|
* Give firmware a chance to be called, such as ACPI _PRx, _PSx
|
2006-06-26 10:35:02 -06:00
|
|
|
* Firmware method after native method ?
|
2005-03-18 22:16:18 -07:00
|
|
|
*/
|
|
|
|
if (platform_pci_set_power_state)
|
|
|
|
platform_pci_set_power_state(dev, state);
|
|
|
|
|
|
|
|
dev->current_state = state;
|
2005-07-27 08:19:44 -06:00
|
|
|
|
|
|
|
/* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
|
|
|
|
* INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
|
|
|
|
* from D3hot to D0 _may_ perform an internal reset, thereby
|
|
|
|
* going to "D0 Uninitialized" rather than "D0 Initialized".
|
|
|
|
* For example, at least some versions of the 3c905B and the
|
|
|
|
* 3c556B exhibit this behaviour.
|
|
|
|
*
|
|
|
|
* At least some laptop BIOSen (e.g. the Thinkpad T21) leave
|
|
|
|
* devices in a D3hot state at boot. Consequently, we need to
|
|
|
|
* restore at least the BARs so that the device will be
|
|
|
|
* accessible to its driver.
|
|
|
|
*/
|
|
|
|
if (need_restore)
|
|
|
|
pci_restore_bars(dev);
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-07-19 20:03:22 -06:00
|
|
|
pci_power_t (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
|
2005-03-18 22:15:48 -07:00
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/**
|
|
|
|
* pci_choose_state - Choose the power state of a PCI device
|
|
|
|
* @dev: PCI device to be suspended
|
|
|
|
* @state: target sleep state for the whole system. This is the value
|
|
|
|
* that is passed to suspend() function.
|
|
|
|
*
|
|
|
|
* Returns PCI power state suitable for given device and given system
|
|
|
|
* message.
|
|
|
|
*/
|
|
|
|
|
|
|
|
pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
|
|
|
|
{
|
2007-07-19 20:03:22 -06:00
|
|
|
pci_power_t ret;
|
2005-03-18 22:15:48 -07:00
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
if (!pci_find_capability(dev, PCI_CAP_ID_PM))
|
|
|
|
return PCI_D0;
|
|
|
|
|
2005-03-18 22:15:48 -07:00
|
|
|
if (platform_pci_choose_state) {
|
|
|
|
ret = platform_pci_choose_state(dev, state);
|
2007-07-19 20:03:22 -06:00
|
|
|
if (ret != PCI_POWER_ERROR)
|
|
|
|
return ret;
|
2005-03-18 22:15:48 -07:00
|
|
|
}
|
2005-09-03 16:56:57 -06:00
|
|
|
|
|
|
|
switch (state.event) {
|
|
|
|
case PM_EVENT_ON:
|
|
|
|
return PCI_D0;
|
|
|
|
case PM_EVENT_FREEZE:
|
2006-08-15 00:11:05 -06:00
|
|
|
case PM_EVENT_PRETHAW:
|
|
|
|
/* REVISIT both freeze and pre-thaw "should" use D0 */
|
2005-09-03 16:56:57 -06:00
|
|
|
case PM_EVENT_SUSPEND:
|
2008-02-23 11:13:25 -07:00
|
|
|
case PM_EVENT_HIBERNATE:
|
2005-09-03 16:56:57 -06:00
|
|
|
return PCI_D3hot;
|
2005-04-16 16:20:36 -06:00
|
|
|
default:
|
2006-08-15 00:11:05 -06:00
|
|
|
printk("Unrecognized suspend event %d\n", state.event);
|
2005-04-16 16:20:36 -06:00
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
return PCI_D0;
|
|
|
|
}
|
|
|
|
|
|
|
|
EXPORT_SYMBOL(pci_choose_state);
|
|
|
|
|
2006-08-21 07:22:22 -06:00
|
|
|
static int pci_save_pcie_state(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int pos, i = 0;
|
|
|
|
struct pci_cap_saved_state *save_state;
|
|
|
|
u16 *cap;
|
2007-12-17 18:57:09 -07:00
|
|
|
int found = 0;
|
2006-08-21 07:22:22 -06:00
|
|
|
|
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
|
|
|
|
if (pos <= 0)
|
|
|
|
return 0;
|
|
|
|
|
2007-03-08 13:06:13 -07:00
|
|
|
save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
|
|
|
|
if (!save_state)
|
|
|
|
save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
|
2007-12-17 18:57:09 -07:00
|
|
|
else
|
|
|
|
found = 1;
|
2006-08-21 07:22:22 -06:00
|
|
|
if (!save_state) {
|
|
|
|
dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
cap = (u16 *)&save_state->data[0];
|
|
|
|
|
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
|
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
|
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
|
|
|
|
pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
|
2007-12-17 18:56:56 -07:00
|
|
|
save_state->cap_nr = PCI_CAP_ID_EXP;
|
2007-12-17 18:57:09 -07:00
|
|
|
if (!found)
|
|
|
|
pci_add_saved_cap(dev, save_state);
|
2006-08-21 07:22:22 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pci_restore_pcie_state(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int i = 0, pos;
|
|
|
|
struct pci_cap_saved_state *save_state;
|
|
|
|
u16 *cap;
|
|
|
|
|
|
|
|
save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
|
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
|
|
|
|
if (!save_state || pos <= 0)
|
|
|
|
return;
|
|
|
|
cap = (u16 *)&save_state->data[0];
|
|
|
|
|
|
|
|
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
|
|
|
|
pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
|
|
|
|
pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
|
|
|
|
pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
|
|
|
|
}
|
|
|
|
|
2006-11-08 17:17:15 -07:00
|
|
|
|
|
|
|
static int pci_save_pcix_state(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int pos, i = 0;
|
|
|
|
struct pci_cap_saved_state *save_state;
|
|
|
|
u16 *cap;
|
2007-12-17 18:57:09 -07:00
|
|
|
int found = 0;
|
2006-11-08 17:17:15 -07:00
|
|
|
|
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
|
|
|
|
if (pos <= 0)
|
|
|
|
return 0;
|
|
|
|
|
2007-12-17 18:56:47 -07:00
|
|
|
save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
|
2007-03-08 13:06:13 -07:00
|
|
|
if (!save_state)
|
|
|
|
save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
|
2007-12-17 18:57:09 -07:00
|
|
|
else
|
|
|
|
found = 1;
|
2006-11-08 17:17:15 -07:00
|
|
|
if (!save_state) {
|
|
|
|
dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
cap = (u16 *)&save_state->data[0];
|
|
|
|
|
|
|
|
pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
|
2007-12-17 18:56:56 -07:00
|
|
|
save_state->cap_nr = PCI_CAP_ID_PCIX;
|
2007-12-17 18:57:09 -07:00
|
|
|
if (!found)
|
|
|
|
pci_add_saved_cap(dev, save_state);
|
2006-11-08 17:17:15 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pci_restore_pcix_state(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int i = 0, pos;
|
|
|
|
struct pci_cap_saved_state *save_state;
|
|
|
|
u16 *cap;
|
|
|
|
|
|
|
|
save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
|
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
|
|
|
|
if (!save_state || pos <= 0)
|
|
|
|
return;
|
|
|
|
cap = (u16 *)&save_state->data[0];
|
|
|
|
|
|
|
|
pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/**
|
|
|
|
* pci_save_state - save the PCI configuration space of a device before suspending
|
|
|
|
* @dev: - PCI device that we're dealing with
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
pci_save_state(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
/* XXX: 100% dword access ok here? */
|
|
|
|
for (i = 0; i < 16; i++)
|
|
|
|
pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
|
2006-08-21 07:22:22 -06:00
|
|
|
if ((i = pci_save_pcie_state(dev)) != 0)
|
|
|
|
return i;
|
2006-11-08 17:17:15 -07:00
|
|
|
if ((i = pci_save_pcix_state(dev)) != 0)
|
|
|
|
return i;
|
2005-04-16 16:20:36 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_restore_state - Restore the saved state of a PCI device
|
|
|
|
* @dev: - PCI device that we're dealing with
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
pci_restore_state(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int i;
|
2007-10-14 12:35:40 -06:00
|
|
|
u32 val;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2006-08-21 07:22:22 -06:00
|
|
|
/* PCI Express register must be restored first */
|
|
|
|
pci_restore_pcie_state(dev);
|
|
|
|
|
2006-04-25 01:00:34 -06:00
|
|
|
/*
|
|
|
|
* The Base Address register should be programmed before the command
|
|
|
|
* register(s)
|
|
|
|
*/
|
|
|
|
for (i = 15; i >= 0; i--) {
|
2006-04-18 22:06:51 -06:00
|
|
|
pci_read_config_dword(dev, i * 4, &val);
|
|
|
|
if (val != dev->saved_config_space[i]) {
|
|
|
|
printk(KERN_DEBUG "PM: Writing back config space on "
|
|
|
|
"device %s at offset %x (was %x, writing %x)\n",
|
|
|
|
pci_name(dev), i,
|
|
|
|
val, (int)dev->saved_config_space[i]);
|
|
|
|
pci_write_config_dword(dev,i * 4,
|
|
|
|
dev->saved_config_space[i]);
|
|
|
|
}
|
|
|
|
}
|
2006-11-08 17:17:15 -07:00
|
|
|
pci_restore_pcix_state(dev);
|
2006-02-08 02:11:38 -07:00
|
|
|
pci_restore_msi_state(dev);
|
2007-01-25 01:34:08 -07:00
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2006-12-17 18:30:00 -07:00
|
|
|
static int do_pci_enable_device(struct pci_dev *dev, int bars)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
|
|
|
err = pci_set_power_state(dev, PCI_D0);
|
|
|
|
if (err < 0 && err != -EIO)
|
|
|
|
return err;
|
|
|
|
err = pcibios_enable_device(dev, bars);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
pci_fixup_device(pci_fixup_enable, dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2007-07-26 23:43:35 -06:00
|
|
|
* pci_reenable_device - Resume abandoned device
|
2006-12-17 18:30:00 -07:00
|
|
|
* @dev: PCI device to be resumed
|
|
|
|
*
|
|
|
|
* Note this function is a backend of pci_default_resume and is not supposed
|
|
|
|
* to be called by normal code, write proper resume handler and use it instead.
|
|
|
|
*/
|
2007-07-26 23:43:35 -06:00
|
|
|
int pci_reenable_device(struct pci_dev *dev)
|
2006-12-17 18:30:00 -07:00
|
|
|
{
|
|
|
|
if (atomic_read(&dev->enable_cnt))
|
|
|
|
return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-12-19 21:28:08 -07:00
|
|
|
static int __pci_enable_device_flags(struct pci_dev *dev,
|
|
|
|
resource_size_t flags)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
|
|
|
int err;
|
2007-12-19 21:28:08 -07:00
|
|
|
int i, bars = 0;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2006-12-17 18:28:43 -07:00
|
|
|
if (atomic_add_return(1, &dev->enable_cnt) > 1)
|
|
|
|
return 0; /* already enabled */
|
|
|
|
|
2007-12-19 21:28:08 -07:00
|
|
|
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
|
|
|
|
if (dev->resource[i].flags & flags)
|
|
|
|
bars |= (1 << i);
|
|
|
|
|
2006-12-17 18:30:00 -07:00
|
|
|
err = do_pci_enable_device(dev, bars);
|
2005-07-28 12:37:33 -06:00
|
|
|
if (err < 0)
|
2006-12-17 18:30:00 -07:00
|
|
|
atomic_dec(&dev->enable_cnt);
|
2006-12-17 18:28:43 -07:00
|
|
|
return err;
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
2007-12-19 21:28:08 -07:00
|
|
|
/**
|
|
|
|
* pci_enable_device_io - Initialize a device for use with IO space
|
|
|
|
* @dev: PCI device to be initialized
|
|
|
|
*
|
|
|
|
* Initialize device before it's used by a driver. Ask low-level code
|
|
|
|
* to enable I/O resources. Wake up the device if it was suspended.
|
|
|
|
* Beware, this function can fail.
|
|
|
|
*/
|
|
|
|
int pci_enable_device_io(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return __pci_enable_device_flags(dev, IORESOURCE_IO);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_enable_device_mem - Initialize a device for use with Memory space
|
|
|
|
* @dev: PCI device to be initialized
|
|
|
|
*
|
|
|
|
* Initialize device before it's used by a driver. Ask low-level code
|
|
|
|
* to enable Memory resources. Wake up the device if it was suspended.
|
|
|
|
* Beware, this function can fail.
|
|
|
|
*/
|
|
|
|
int pci_enable_device_mem(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return __pci_enable_device_flags(dev, IORESOURCE_MEM);
|
|
|
|
}
|
|
|
|
|
PCI: switch pci_{enable,disable}_device() to be nestable
Changes the pci_{enable,disable}_device() functions to work in a
nested basis, so that eg, three calls to enable_device() require three
calls to disable_device().
The reason for this is to simplify PCI drivers for
multi-interface/capability devices. These are devices that cram more
than one interface in a single function. A relevant example of that is
the Wireless [USB] Host Controller Interface (similar to EHCI) [see
http://www.intel.com/technology/comms/wusb/whci.htm].
In these kind of devices, multiple interfaces are accessed through a
single bar and IRQ line. For that, the drivers map only the smallest
area of the bar to access their register banks and use shared IRQ
handlers.
However, because the order at which those drivers load cannot be known
ahead of time, the sequence in which the calls to pci_enable_device()
and pci_disable_device() cannot be predicted. Thus:
1. driverA starts pci_enable_device()
2. driverB starts pci_enable_device()
3. driverA shutdown pci_disable_device()
4. driverB shutdown pci_disable_device()
between steps 3 and 4, driver B would loose access to it's device,
even if it didn't intend to.
By using this modification, the device won't be disabled until all the
callers to enable() have called disable().
This is implemented by replacing 'struct pci_dev->is_enabled' from a
bitfield to an atomic use count. Each caller to enable increments it,
each caller to disable decrements it. When the count increments from 0
to 1, __pci_enable_device() is called to actually enable the
device. When it drops to zero, pci_disable_device() actually does the
disabling.
We keep the backend __pci_enable_device() for pci_default_resume() to
use and also change the sysfs method implementation, so that userspace
enabling/disabling the device doesn't disable it one time too much.
Signed-off-by: Inaky Perez-Gonzalez <inaky@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-11-22 13:40:31 -07:00
|
|
|
/**
|
|
|
|
* pci_enable_device - Initialize device before it's used by a driver.
|
|
|
|
* @dev: PCI device to be initialized
|
|
|
|
*
|
|
|
|
* Initialize device before it's used by a driver. Ask low-level code
|
|
|
|
* to enable I/O and memory. Wake up the device if it was suspended.
|
|
|
|
* Beware, this function can fail.
|
|
|
|
*
|
|
|
|
* Note we don't actually enable the device many times if we call
|
|
|
|
* this function repeatedly (we just increment the count).
|
|
|
|
*/
|
|
|
|
int pci_enable_device(struct pci_dev *dev)
|
|
|
|
{
|
2007-12-19 21:28:08 -07:00
|
|
|
return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
|
PCI: switch pci_{enable,disable}_device() to be nestable
Changes the pci_{enable,disable}_device() functions to work in a
nested basis, so that eg, three calls to enable_device() require three
calls to disable_device().
The reason for this is to simplify PCI drivers for
multi-interface/capability devices. These are devices that cram more
than one interface in a single function. A relevant example of that is
the Wireless [USB] Host Controller Interface (similar to EHCI) [see
http://www.intel.com/technology/comms/wusb/whci.htm].
In these kind of devices, multiple interfaces are accessed through a
single bar and IRQ line. For that, the drivers map only the smallest
area of the bar to access their register banks and use shared IRQ
handlers.
However, because the order at which those drivers load cannot be known
ahead of time, the sequence in which the calls to pci_enable_device()
and pci_disable_device() cannot be predicted. Thus:
1. driverA starts pci_enable_device()
2. driverB starts pci_enable_device()
3. driverA shutdown pci_disable_device()
4. driverB shutdown pci_disable_device()
between steps 3 and 4, driver B would loose access to it's device,
even if it didn't intend to.
By using this modification, the device won't be disabled until all the
callers to enable() have called disable().
This is implemented by replacing 'struct pci_dev->is_enabled' from a
bitfield to an atomic use count. Each caller to enable increments it,
each caller to disable decrements it. When the count increments from 0
to 1, __pci_enable_device() is called to actually enable the
device. When it drops to zero, pci_disable_device() actually does the
disabling.
We keep the backend __pci_enable_device() for pci_default_resume() to
use and also change the sysfs method implementation, so that userspace
enabling/disabling the device doesn't disable it one time too much.
Signed-off-by: Inaky Perez-Gonzalez <inaky@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-11-22 13:40:31 -07:00
|
|
|
}
|
|
|
|
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
/*
|
|
|
|
* Managed PCI resources. This manages device on/off, intx/msi/msix
|
|
|
|
* on/off and BAR regions. pci_dev itself records msi/msix status, so
|
|
|
|
* there's no need to track it separately. pci_devres is initialized
|
|
|
|
* when a device is enabled using managed PCI device enable interface.
|
|
|
|
*/
|
|
|
|
struct pci_devres {
|
2007-02-25 05:36:01 -07:00
|
|
|
unsigned int enabled:1;
|
|
|
|
unsigned int pinned:1;
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
unsigned int orig_intx:1;
|
|
|
|
unsigned int restore_intx:1;
|
|
|
|
u32 region_mask;
|
|
|
|
};
|
|
|
|
|
|
|
|
static void pcim_release(struct device *gendev, void *res)
|
|
|
|
{
|
|
|
|
struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
|
|
|
|
struct pci_devres *this = res;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (dev->msi_enabled)
|
|
|
|
pci_disable_msi(dev);
|
|
|
|
if (dev->msix_enabled)
|
|
|
|
pci_disable_msix(dev);
|
|
|
|
|
|
|
|
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
|
|
|
|
if (this->region_mask & (1 << i))
|
|
|
|
pci_release_region(dev, i);
|
|
|
|
|
|
|
|
if (this->restore_intx)
|
|
|
|
pci_intx(dev, this->orig_intx);
|
|
|
|
|
2007-02-25 05:36:01 -07:00
|
|
|
if (this->enabled && !this->pinned)
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
pci_disable_device(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct pci_devres *dr, *new_dr;
|
|
|
|
|
|
|
|
dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
|
|
|
|
if (dr)
|
|
|
|
return dr;
|
|
|
|
|
|
|
|
new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
|
|
|
|
if (!new_dr)
|
|
|
|
return NULL;
|
|
|
|
return devres_get(&pdev->dev, new_dr, NULL, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
if (pci_is_managed(pdev))
|
|
|
|
return devres_find(&pdev->dev, pcim_release, NULL, NULL);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pcim_enable_device - Managed pci_enable_device()
|
|
|
|
* @pdev: PCI device to be initialized
|
|
|
|
*
|
|
|
|
* Managed pci_enable_device().
|
|
|
|
*/
|
|
|
|
int pcim_enable_device(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct pci_devres *dr;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
dr = get_pci_dr(pdev);
|
|
|
|
if (unlikely(!dr))
|
|
|
|
return -ENOMEM;
|
2008-01-30 02:20:04 -07:00
|
|
|
if (dr->enabled)
|
|
|
|
return 0;
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
|
|
|
|
rc = pci_enable_device(pdev);
|
|
|
|
if (!rc) {
|
|
|
|
pdev->is_managed = 1;
|
2007-02-25 05:36:01 -07:00
|
|
|
dr->enabled = 1;
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
}
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pcim_pin_device - Pin managed PCI device
|
|
|
|
* @pdev: PCI device to pin
|
|
|
|
*
|
|
|
|
* Pin managed PCI device @pdev. Pinned device won't be disabled on
|
|
|
|
* driver detach. @pdev must have been enabled with
|
|
|
|
* pcim_enable_device().
|
|
|
|
*/
|
|
|
|
void pcim_pin_device(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct pci_devres *dr;
|
|
|
|
|
|
|
|
dr = find_pci_dr(pdev);
|
2007-02-25 05:36:01 -07:00
|
|
|
WARN_ON(!dr || !dr->enabled);
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
if (dr)
|
2007-02-25 05:36:01 -07:00
|
|
|
dr->pinned = 1;
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
}
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/**
|
|
|
|
* pcibios_disable_device - disable arch specific PCI resources for device dev
|
|
|
|
* @dev: the PCI device to disable
|
|
|
|
*
|
|
|
|
* Disables architecture specific PCI resources for the device. This
|
|
|
|
* is the default implementation. Architecture implementations can
|
|
|
|
* override this.
|
|
|
|
*/
|
|
|
|
void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_disable_device - Disable PCI device after use
|
|
|
|
* @dev: PCI device to be disabled
|
|
|
|
*
|
|
|
|
* Signal to the system that the PCI device is not in use by the system
|
|
|
|
* anymore. This only involves disabling PCI bus-mastering, if active.
|
PCI: switch pci_{enable,disable}_device() to be nestable
Changes the pci_{enable,disable}_device() functions to work in a
nested basis, so that eg, three calls to enable_device() require three
calls to disable_device().
The reason for this is to simplify PCI drivers for
multi-interface/capability devices. These are devices that cram more
than one interface in a single function. A relevant example of that is
the Wireless [USB] Host Controller Interface (similar to EHCI) [see
http://www.intel.com/technology/comms/wusb/whci.htm].
In these kind of devices, multiple interfaces are accessed through a
single bar and IRQ line. For that, the drivers map only the smallest
area of the bar to access their register banks and use shared IRQ
handlers.
However, because the order at which those drivers load cannot be known
ahead of time, the sequence in which the calls to pci_enable_device()
and pci_disable_device() cannot be predicted. Thus:
1. driverA starts pci_enable_device()
2. driverB starts pci_enable_device()
3. driverA shutdown pci_disable_device()
4. driverB shutdown pci_disable_device()
between steps 3 and 4, driver B would loose access to it's device,
even if it didn't intend to.
By using this modification, the device won't be disabled until all the
callers to enable() have called disable().
This is implemented by replacing 'struct pci_dev->is_enabled' from a
bitfield to an atomic use count. Each caller to enable increments it,
each caller to disable decrements it. When the count increments from 0
to 1, __pci_enable_device() is called to actually enable the
device. When it drops to zero, pci_disable_device() actually does the
disabling.
We keep the backend __pci_enable_device() for pci_default_resume() to
use and also change the sysfs method implementation, so that userspace
enabling/disabling the device doesn't disable it one time too much.
Signed-off-by: Inaky Perez-Gonzalez <inaky@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-11-22 13:40:31 -07:00
|
|
|
*
|
|
|
|
* Note we don't actually disable the device until all callers of
|
|
|
|
* pci_device_enable() have called pci_device_disable().
|
2005-04-16 16:20:36 -06:00
|
|
|
*/
|
|
|
|
void
|
|
|
|
pci_disable_device(struct pci_dev *dev)
|
|
|
|
{
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
struct pci_devres *dr;
|
2005-04-16 16:20:36 -06:00
|
|
|
u16 pci_command;
|
2006-05-25 20:58:27 -06:00
|
|
|
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
dr = find_pci_dr(dev);
|
|
|
|
if (dr)
|
2007-02-25 05:36:01 -07:00
|
|
|
dr->enabled = 0;
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
|
PCI: switch pci_{enable,disable}_device() to be nestable
Changes the pci_{enable,disable}_device() functions to work in a
nested basis, so that eg, three calls to enable_device() require three
calls to disable_device().
The reason for this is to simplify PCI drivers for
multi-interface/capability devices. These are devices that cram more
than one interface in a single function. A relevant example of that is
the Wireless [USB] Host Controller Interface (similar to EHCI) [see
http://www.intel.com/technology/comms/wusb/whci.htm].
In these kind of devices, multiple interfaces are accessed through a
single bar and IRQ line. For that, the drivers map only the smallest
area of the bar to access their register banks and use shared IRQ
handlers.
However, because the order at which those drivers load cannot be known
ahead of time, the sequence in which the calls to pci_enable_device()
and pci_disable_device() cannot be predicted. Thus:
1. driverA starts pci_enable_device()
2. driverB starts pci_enable_device()
3. driverA shutdown pci_disable_device()
4. driverB shutdown pci_disable_device()
between steps 3 and 4, driver B would loose access to it's device,
even if it didn't intend to.
By using this modification, the device won't be disabled until all the
callers to enable() have called disable().
This is implemented by replacing 'struct pci_dev->is_enabled' from a
bitfield to an atomic use count. Each caller to enable increments it,
each caller to disable decrements it. When the count increments from 0
to 1, __pci_enable_device() is called to actually enable the
device. When it drops to zero, pci_disable_device() actually does the
disabling.
We keep the backend __pci_enable_device() for pci_default_resume() to
use and also change the sysfs method implementation, so that userspace
enabling/disabling the device doesn't disable it one time too much.
Signed-off-by: Inaky Perez-Gonzalez <inaky@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2006-11-22 13:40:31 -07:00
|
|
|
if (atomic_sub_return(1, &dev->enable_cnt) != 0)
|
|
|
|
return;
|
|
|
|
|
2007-10-23 20:45:08 -06:00
|
|
|
/* Wait for all transactions are finished before disabling the device */
|
|
|
|
pcie_wait_pending_transaction(dev);
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &pci_command);
|
|
|
|
if (pci_command & PCI_COMMAND_MASTER) {
|
|
|
|
pci_command &= ~PCI_COMMAND_MASTER;
|
|
|
|
pci_write_config_word(dev, PCI_COMMAND, pci_command);
|
|
|
|
}
|
2005-04-07 23:53:31 -06:00
|
|
|
dev->is_busmaster = 0;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
pcibios_disable_device(dev);
|
|
|
|
}
|
|
|
|
|
2007-04-06 15:39:36 -06:00
|
|
|
/**
|
|
|
|
* pcibios_set_pcie_reset_state - set reset state for device dev
|
|
|
|
* @dev: the PCI-E device reset
|
|
|
|
* @state: Reset state to enter into
|
|
|
|
*
|
|
|
|
*
|
|
|
|
* Sets the PCI-E reset state for the device. This is the default
|
|
|
|
* implementation. Architecture implementations can override this.
|
|
|
|
*/
|
|
|
|
int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
|
|
|
|
enum pcie_reset_state state)
|
|
|
|
{
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_set_pcie_reset_state - set reset state for device dev
|
|
|
|
* @dev: the PCI-E device reset
|
|
|
|
* @state: Reset state to enter into
|
|
|
|
*
|
|
|
|
*
|
|
|
|
* Sets the PCI reset state for the device.
|
|
|
|
*/
|
|
|
|
int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
|
|
|
|
{
|
|
|
|
return pcibios_set_pcie_reset_state(dev, state);
|
|
|
|
}
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/**
|
2007-04-26 01:12:06 -06:00
|
|
|
* pci_enable_wake - enable PCI device as wakeup event source
|
|
|
|
* @dev: PCI device affected
|
|
|
|
* @state: PCI state from which device will issue wakeup events
|
|
|
|
* @enable: True to enable event generation; false to disable
|
|
|
|
*
|
|
|
|
* This enables the device as a wakeup event source, or disables it.
|
|
|
|
* When such events involves platform-specific hooks, those hooks are
|
|
|
|
* called automatically by this routine.
|
|
|
|
*
|
|
|
|
* Devices with legacy power management (no standard PCI PM capabilities)
|
|
|
|
* always require such platform hooks. Depending on the platform, devices
|
|
|
|
* supporting the standard PCI PME# signal may require such platform hooks;
|
|
|
|
* they always update bits in config space to allow PME# generation.
|
|
|
|
*
|
|
|
|
* -EIO is returned if the device can't ever be a wakeup event source.
|
|
|
|
* -EINVAL is returned if the device can't generate wakeup events from
|
|
|
|
* the specified PCI state. Returns zero if the operation is successful.
|
2005-04-16 16:20:36 -06:00
|
|
|
*/
|
|
|
|
int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
|
|
|
|
{
|
|
|
|
int pm;
|
2007-04-26 01:12:06 -06:00
|
|
|
int status;
|
2005-04-16 16:20:36 -06:00
|
|
|
u16 value;
|
|
|
|
|
2007-04-26 01:12:06 -06:00
|
|
|
/* Note that drivers should verify device_may_wakeup(&dev->dev)
|
|
|
|
* before calling this function. Platform code should report
|
|
|
|
* errors when drivers try to enable wakeup on devices that
|
|
|
|
* can't issue wakeups, or on which wakeups were disabled by
|
|
|
|
* userspace updating the /sys/devices.../power/wakeup file.
|
|
|
|
*/
|
|
|
|
|
|
|
|
status = call_platform_enable_wakeup(&dev->dev, enable);
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/* find PCI PM capability in list */
|
|
|
|
pm = pci_find_capability(dev, PCI_CAP_ID_PM);
|
|
|
|
|
2007-04-26 01:12:06 -06:00
|
|
|
/* If device doesn't support PM Capabilities, but caller wants to
|
|
|
|
* disable wake events, it's a NOP. Otherwise fail unless the
|
|
|
|
* platform hooks handled this legacy device already.
|
|
|
|
*/
|
|
|
|
if (!pm)
|
|
|
|
return enable ? status : 0;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/* Check device's ability to generate PME# */
|
|
|
|
pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
|
|
|
|
|
|
|
|
value &= PCI_PM_CAP_PME_MASK;
|
|
|
|
value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
|
|
|
|
|
|
|
|
/* Check if it can generate PME# from requested state. */
|
2007-04-26 01:12:06 -06:00
|
|
|
if (!value || !(value & (1 << state))) {
|
|
|
|
/* if it can't, revert what the platform hook changed,
|
|
|
|
* always reporting the base "EINVAL, can't PME#" error
|
|
|
|
*/
|
|
|
|
if (enable)
|
|
|
|
call_platform_enable_wakeup(&dev->dev, 0);
|
2005-04-16 16:20:36 -06:00
|
|
|
return enable ? -EINVAL : 0;
|
2007-04-26 01:12:06 -06:00
|
|
|
}
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
|
|
|
|
|
|
|
|
/* Clear PME_Status by writing 1 to it and enable PME# */
|
|
|
|
value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
|
|
|
|
|
|
|
|
if (!enable)
|
|
|
|
value &= ~PCI_PM_CTRL_PME_ENABLE;
|
|
|
|
|
|
|
|
pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
|
2007-04-26 01:12:06 -06:00
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
|
|
|
|
{
|
|
|
|
u8 pin;
|
|
|
|
|
2005-11-02 17:24:39 -07:00
|
|
|
pin = dev->pin;
|
2005-04-16 16:20:36 -06:00
|
|
|
if (!pin)
|
|
|
|
return -1;
|
|
|
|
pin--;
|
|
|
|
while (dev->bus->self) {
|
|
|
|
pin = (pin + PCI_SLOT(dev->devfn)) % 4;
|
|
|
|
dev = dev->bus->self;
|
|
|
|
}
|
|
|
|
*bridge = dev;
|
|
|
|
return pin;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_release_region - Release a PCI bar
|
|
|
|
* @pdev: PCI device whose resources were previously reserved by pci_request_region
|
|
|
|
* @bar: BAR to release
|
|
|
|
*
|
|
|
|
* Releases the PCI I/O and memory resources previously reserved by a
|
|
|
|
* successful call to pci_request_region. Call this function only
|
|
|
|
* after all use of the PCI regions has ceased.
|
|
|
|
*/
|
|
|
|
void pci_release_region(struct pci_dev *pdev, int bar)
|
|
|
|
{
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
struct pci_devres *dr;
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
if (pci_resource_len(pdev, bar) == 0)
|
|
|
|
return;
|
|
|
|
if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
|
|
|
|
release_region(pci_resource_start(pdev, bar),
|
|
|
|
pci_resource_len(pdev, bar));
|
|
|
|
else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
|
|
|
|
release_mem_region(pci_resource_start(pdev, bar),
|
|
|
|
pci_resource_len(pdev, bar));
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
|
|
|
|
dr = find_pci_dr(pdev);
|
|
|
|
if (dr)
|
|
|
|
dr->region_mask &= ~(1 << bar);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_request_region - Reserved PCI I/O and memory resource
|
|
|
|
* @pdev: PCI device whose resources are to be reserved
|
|
|
|
* @bar: BAR to be reserved
|
|
|
|
* @res_name: Name to be associated with resource.
|
|
|
|
*
|
|
|
|
* Mark the PCI region associated with PCI device @pdev BR @bar as
|
|
|
|
* being reserved by owner @res_name. Do not access any
|
|
|
|
* address inside the PCI regions unless this call returns
|
|
|
|
* successfully.
|
|
|
|
*
|
|
|
|
* Returns 0 on success, or %EBUSY on error. A warning
|
|
|
|
* message is also printed on failure.
|
|
|
|
*/
|
2006-03-04 19:52:42 -07:00
|
|
|
int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
struct pci_devres *dr;
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
if (pci_resource_len(pdev, bar) == 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
|
|
|
|
if (!request_region(pci_resource_start(pdev, bar),
|
|
|
|
pci_resource_len(pdev, bar), res_name))
|
|
|
|
goto err_out;
|
|
|
|
}
|
|
|
|
else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
|
|
|
|
if (!request_mem_region(pci_resource_start(pdev, bar),
|
|
|
|
pci_resource_len(pdev, bar), res_name))
|
|
|
|
goto err_out;
|
|
|
|
}
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
|
|
|
|
dr = find_pci_dr(pdev);
|
|
|
|
if (dr)
|
|
|
|
dr->region_mask |= 1 << bar;
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_out:
|
2006-06-12 16:14:29 -06:00
|
|
|
printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx "
|
|
|
|
"for device %s\n",
|
2005-04-16 16:20:36 -06:00
|
|
|
pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
|
|
|
|
bar + 1, /* PCI BAR # */
|
2006-06-12 16:14:29 -06:00
|
|
|
(unsigned long long)pci_resource_len(pdev, bar),
|
|
|
|
(unsigned long long)pci_resource_start(pdev, bar),
|
2005-04-16 16:20:36 -06:00
|
|
|
pci_name(pdev));
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
2006-12-17 18:31:06 -07:00
|
|
|
/**
|
|
|
|
* pci_release_selected_regions - Release selected PCI I/O and memory resources
|
|
|
|
* @pdev: PCI device whose resources were previously reserved
|
|
|
|
* @bars: Bitmask of BARs to be released
|
|
|
|
*
|
|
|
|
* Release selected PCI I/O and memory resources previously reserved.
|
|
|
|
* Call this function only after all use of the PCI regions has ceased.
|
|
|
|
*/
|
|
|
|
void pci_release_selected_regions(struct pci_dev *pdev, int bars)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 6; i++)
|
|
|
|
if (bars & (1 << i))
|
|
|
|
pci_release_region(pdev, i);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_request_selected_regions - Reserve selected PCI I/O and memory resources
|
|
|
|
* @pdev: PCI device whose resources are to be reserved
|
|
|
|
* @bars: Bitmask of BARs to be requested
|
|
|
|
* @res_name: Name to be associated with resource
|
|
|
|
*/
|
|
|
|
int pci_request_selected_regions(struct pci_dev *pdev, int bars,
|
|
|
|
const char *res_name)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 6; i++)
|
|
|
|
if (bars & (1 << i))
|
|
|
|
if(pci_request_region(pdev, i, res_name))
|
|
|
|
goto err_out;
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_out:
|
|
|
|
while(--i >= 0)
|
|
|
|
if (bars & (1 << i))
|
|
|
|
pci_release_region(pdev, i);
|
|
|
|
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_release_regions - Release reserved PCI I/O and memory resources
|
|
|
|
* @pdev: PCI device whose resources were previously reserved by pci_request_regions
|
|
|
|
*
|
|
|
|
* Releases all PCI I/O and memory resources previously reserved by a
|
|
|
|
* successful call to pci_request_regions. Call this function only
|
|
|
|
* after all use of the PCI regions has ceased.
|
|
|
|
*/
|
|
|
|
|
|
|
|
void pci_release_regions(struct pci_dev *pdev)
|
|
|
|
{
|
2006-12-17 18:31:06 -07:00
|
|
|
pci_release_selected_regions(pdev, (1 << 6) - 1);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_request_regions - Reserved PCI I/O and memory resources
|
|
|
|
* @pdev: PCI device whose resources are to be reserved
|
|
|
|
* @res_name: Name to be associated with resource.
|
|
|
|
*
|
|
|
|
* Mark all PCI regions associated with PCI device @pdev as
|
|
|
|
* being reserved by owner @res_name. Do not access any
|
|
|
|
* address inside the PCI regions unless this call returns
|
|
|
|
* successfully.
|
|
|
|
*
|
|
|
|
* Returns 0 on success, or %EBUSY on error. A warning
|
|
|
|
* message is also printed on failure.
|
|
|
|
*/
|
2006-03-04 19:52:42 -07:00
|
|
|
int pci_request_regions(struct pci_dev *pdev, const char *res_name)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
2006-12-17 18:31:06 -07:00
|
|
|
return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_set_master - enables bus-mastering for device dev
|
|
|
|
* @dev: the PCI device to enable
|
|
|
|
*
|
|
|
|
* Enables bus-mastering on the device and calls pcibios_set_master()
|
|
|
|
* to do the needed arch specific settings.
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
pci_set_master(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
u16 cmd;
|
|
|
|
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
|
|
|
if (! (cmd & PCI_COMMAND_MASTER)) {
|
|
|
|
pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
|
|
|
|
cmd |= PCI_COMMAND_MASTER;
|
|
|
|
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
|
|
|
}
|
|
|
|
dev->is_busmaster = 1;
|
|
|
|
pcibios_set_master(dev);
|
|
|
|
}
|
|
|
|
|
2006-10-10 08:01:21 -06:00
|
|
|
#ifdef PCI_DISABLE_MWI
|
|
|
|
int pci_set_mwi(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-07-09 12:55:54 -06:00
|
|
|
int pci_try_set_mwi(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2006-10-10 08:01:21 -06:00
|
|
|
void pci_clear_mwi(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
#else
|
2006-10-10 08:01:20 -06:00
|
|
|
|
|
|
|
#ifndef PCI_CACHE_LINE_BYTES
|
|
|
|
#define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
|
|
|
|
#endif
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/* This can be overridden by arch code. */
|
2006-10-10 08:01:20 -06:00
|
|
|
/* Don't forget this is measured in 32-bit words, not bytes */
|
|
|
|
u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/**
|
2006-10-10 08:01:21 -06:00
|
|
|
* pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
|
|
|
|
* @dev: the PCI device for which MWI is to be enabled
|
2005-04-16 16:20:36 -06:00
|
|
|
*
|
2006-10-10 08:01:21 -06:00
|
|
|
* Helper function for pci_set_mwi.
|
|
|
|
* Originally copied from drivers/net/acenic.c.
|
2005-04-16 16:20:36 -06:00
|
|
|
* Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
|
|
|
|
*
|
|
|
|
* RETURNS: An appropriate -ERRNO error value on error, or zero for success.
|
|
|
|
*/
|
|
|
|
static int
|
2006-10-10 08:01:21 -06:00
|
|
|
pci_set_cacheline_size(struct pci_dev *dev)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
|
|
|
u8 cacheline_size;
|
|
|
|
|
|
|
|
if (!pci_cache_line_size)
|
|
|
|
return -EINVAL; /* The system doesn't support MWI. */
|
|
|
|
|
|
|
|
/* Validate current setting: the PCI_CACHE_LINE_SIZE must be
|
|
|
|
equal to or multiple of the right value. */
|
|
|
|
pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
|
|
|
|
if (cacheline_size >= pci_cache_line_size &&
|
|
|
|
(cacheline_size % pci_cache_line_size) == 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* Write the correct value. */
|
|
|
|
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
|
|
|
|
/* Read it back. */
|
|
|
|
pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
|
|
|
|
if (cacheline_size == pci_cache_line_size)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
|
|
|
|
"by device %s\n", pci_cache_line_size << 2, pci_name(dev));
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_set_mwi - enables memory-write-invalidate PCI transaction
|
|
|
|
* @dev: the PCI device for which MWI is enabled
|
|
|
|
*
|
2007-07-09 12:55:54 -06:00
|
|
|
* Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
|
2005-04-16 16:20:36 -06:00
|
|
|
*
|
|
|
|
* RETURNS: An appropriate -ERRNO error value on error, or zero for success.
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
pci_set_mwi(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
u16 cmd;
|
|
|
|
|
2006-10-10 08:01:21 -06:00
|
|
|
rc = pci_set_cacheline_size(dev);
|
2005-04-16 16:20:36 -06:00
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
|
|
|
if (! (cmd & PCI_COMMAND_INVALIDATE)) {
|
2007-07-09 12:55:54 -06:00
|
|
|
pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n",
|
|
|
|
pci_name(dev));
|
2005-04-16 16:20:36 -06:00
|
|
|
cmd |= PCI_COMMAND_INVALIDATE;
|
|
|
|
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-07-09 12:55:54 -06:00
|
|
|
/**
|
|
|
|
* pci_try_set_mwi - enables memory-write-invalidate PCI transaction
|
|
|
|
* @dev: the PCI device for which MWI is enabled
|
|
|
|
*
|
|
|
|
* Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
|
|
|
|
* Callers are not required to check the return value.
|
|
|
|
*
|
|
|
|
* RETURNS: An appropriate -ERRNO error value on error, or zero for success.
|
|
|
|
*/
|
|
|
|
int pci_try_set_mwi(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int rc = pci_set_mwi(dev);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/**
|
|
|
|
* pci_clear_mwi - disables Memory-Write-Invalidate for device dev
|
|
|
|
* @dev: the PCI device to disable
|
|
|
|
*
|
|
|
|
* Disables PCI Memory-Write-Invalidate transaction on the device
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
pci_clear_mwi(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
u16 cmd;
|
|
|
|
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
|
|
|
if (cmd & PCI_COMMAND_INVALIDATE) {
|
|
|
|
cmd &= ~PCI_COMMAND_INVALIDATE;
|
|
|
|
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
|
|
|
}
|
|
|
|
}
|
2006-10-10 08:01:21 -06:00
|
|
|
#endif /* ! PCI_DISABLE_MWI */
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2005-08-15 13:23:41 -06:00
|
|
|
/**
|
|
|
|
* pci_intx - enables/disables PCI INTx for device dev
|
2005-10-23 12:57:38 -06:00
|
|
|
* @pdev: the PCI device to operate on
|
|
|
|
* @enable: boolean: whether to enable or disable PCI INTx
|
2005-08-15 13:23:41 -06:00
|
|
|
*
|
|
|
|
* Enables/disables PCI INTx for device dev
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
pci_intx(struct pci_dev *pdev, int enable)
|
|
|
|
{
|
|
|
|
u16 pci_command, new;
|
|
|
|
|
|
|
|
pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
|
|
|
|
|
|
|
|
if (enable) {
|
|
|
|
new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
|
|
|
|
} else {
|
|
|
|
new = pci_command | PCI_COMMAND_INTX_DISABLE;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (new != pci_command) {
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
struct pci_devres *dr;
|
|
|
|
|
2005-09-09 11:02:22 -06:00
|
|
|
pci_write_config_word(pdev, PCI_COMMAND, new);
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
|
|
|
|
dr = find_pci_dr(pdev);
|
|
|
|
if (dr && !dr->restore_intx) {
|
|
|
|
dr->restore_intx = 1;
|
|
|
|
dr->orig_intx = !enable;
|
|
|
|
}
|
2005-08-15 13:23:41 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-03-05 01:30:07 -07:00
|
|
|
/**
|
|
|
|
* pci_msi_off - disables any msi or msix capabilities
|
2007-03-16 20:55:52 -06:00
|
|
|
* @dev: the PCI device to operate on
|
2007-03-05 01:30:07 -07:00
|
|
|
*
|
|
|
|
* If you want to use msi see pci_enable_msi and friends.
|
|
|
|
* This is a lower level primitive that allows us to disable
|
|
|
|
* msi operation at the device level.
|
|
|
|
*/
|
|
|
|
void pci_msi_off(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int pos;
|
|
|
|
u16 control;
|
|
|
|
|
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
|
|
|
|
if (pos) {
|
|
|
|
pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
|
|
|
|
control &= ~PCI_MSI_FLAGS_ENABLE;
|
|
|
|
pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
|
|
|
|
}
|
|
|
|
pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
|
|
|
|
if (pos) {
|
|
|
|
pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
|
|
|
|
control &= ~PCI_MSIX_FLAGS_ENABLE;
|
|
|
|
pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
#ifndef HAVE_ARCH_PCI_SET_DMA_MASK
|
|
|
|
/*
|
|
|
|
* These can be overridden by arch-specific implementations
|
|
|
|
*/
|
|
|
|
int
|
|
|
|
pci_set_dma_mask(struct pci_dev *dev, u64 mask)
|
|
|
|
{
|
|
|
|
if (!pci_dma_supported(dev, mask))
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
dev->dma_mask = mask;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
|
|
|
|
{
|
|
|
|
if (!pci_dma_supported(dev, mask))
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
dev->dev.coherent_dma_mask = mask;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
2006-12-17 18:31:06 -07:00
|
|
|
|
2008-02-04 23:27:55 -07:00
|
|
|
#ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
|
|
|
|
int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
|
|
|
|
{
|
|
|
|
return dma_set_max_seg_size(&dev->dev, size);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_set_dma_max_seg_size);
|
|
|
|
#endif
|
|
|
|
|
2008-02-04 23:28:14 -07:00
|
|
|
#ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
|
|
|
|
int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
|
|
|
|
{
|
|
|
|
return dma_set_seg_boundary(&dev->dev, mask);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_set_dma_seg_boundary);
|
|
|
|
#endif
|
|
|
|
|
2007-05-15 05:59:13 -06:00
|
|
|
/**
|
|
|
|
* pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
|
|
|
|
* @dev: PCI device to query
|
|
|
|
*
|
|
|
|
* Returns mmrbc: maximum designed memory read count in bytes
|
|
|
|
* or appropriate error value.
|
|
|
|
*/
|
|
|
|
int pcix_get_max_mmrbc(struct pci_dev *dev)
|
|
|
|
{
|
2007-07-09 12:55:50 -06:00
|
|
|
int err, cap;
|
2007-05-15 05:59:13 -06:00
|
|
|
u32 stat;
|
|
|
|
|
|
|
|
cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
|
|
|
|
if (!cap)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
|
|
|
|
if (err)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2007-07-09 12:55:50 -06:00
|
|
|
return (stat & PCI_X_STATUS_MAX_READ) >> 12;
|
2007-05-15 05:59:13 -06:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pcix_get_max_mmrbc);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pcix_get_mmrbc - get PCI-X maximum memory read byte count
|
|
|
|
* @dev: PCI device to query
|
|
|
|
*
|
|
|
|
* Returns mmrbc: maximum memory read count in bytes
|
|
|
|
* or appropriate error value.
|
|
|
|
*/
|
|
|
|
int pcix_get_mmrbc(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int ret, cap;
|
|
|
|
u32 cmd;
|
|
|
|
|
|
|
|
cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
|
|
|
|
if (!cap)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
|
|
|
|
if (!ret)
|
|
|
|
ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pcix_get_mmrbc);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pcix_set_mmrbc - set PCI-X maximum memory read byte count
|
|
|
|
* @dev: PCI device to query
|
|
|
|
* @mmrbc: maximum memory read count in bytes
|
|
|
|
* valid values are 512, 1024, 2048, 4096
|
|
|
|
*
|
|
|
|
* If possible sets maximum memory read byte count, some bridges have erratas
|
|
|
|
* that prevent this.
|
|
|
|
*/
|
|
|
|
int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
|
|
|
|
{
|
|
|
|
int cap, err = -EINVAL;
|
|
|
|
u32 stat, cmd, v, o;
|
|
|
|
|
2007-08-13 06:53:14 -06:00
|
|
|
if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
|
2007-05-15 05:59:13 -06:00
|
|
|
goto out;
|
|
|
|
|
|
|
|
v = ffs(mmrbc) - 10;
|
|
|
|
|
|
|
|
cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
|
|
|
|
if (!cap)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
|
|
|
|
if (err)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
|
|
|
|
return -E2BIG;
|
|
|
|
|
|
|
|
err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
|
|
|
|
if (err)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
|
|
|
|
if (o != v) {
|
|
|
|
if (v > o && dev->bus &&
|
|
|
|
(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
cmd &= ~PCI_X_CMD_MAX_READ;
|
|
|
|
cmd |= v << 2;
|
|
|
|
err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pcix_set_mmrbc);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pcie_get_readrq - get PCI Express read request size
|
|
|
|
* @dev: PCI device to query
|
|
|
|
*
|
|
|
|
* Returns maximum memory read request in bytes
|
|
|
|
* or appropriate error value.
|
|
|
|
*/
|
|
|
|
int pcie_get_readrq(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int ret, cap;
|
|
|
|
u16 ctl;
|
|
|
|
|
|
|
|
cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
|
|
|
|
if (!cap)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
|
|
|
|
if (!ret)
|
|
|
|
ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pcie_get_readrq);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pcie_set_readrq - set PCI Express maximum memory read request
|
|
|
|
* @dev: PCI device to query
|
2007-07-23 22:42:11 -06:00
|
|
|
* @rq: maximum memory read count in bytes
|
2007-05-15 05:59:13 -06:00
|
|
|
* valid values are 128, 256, 512, 1024, 2048, 4096
|
|
|
|
*
|
|
|
|
* If possible sets maximum read byte count
|
|
|
|
*/
|
|
|
|
int pcie_set_readrq(struct pci_dev *dev, int rq)
|
|
|
|
{
|
|
|
|
int cap, err = -EINVAL;
|
|
|
|
u16 ctl, v;
|
|
|
|
|
2007-08-13 06:53:14 -06:00
|
|
|
if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
|
2007-05-15 05:59:13 -06:00
|
|
|
goto out;
|
|
|
|
|
|
|
|
v = (ffs(rq) - 8) << 12;
|
|
|
|
|
|
|
|
cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
|
|
|
|
if (!cap)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
|
|
|
|
if (err)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
|
|
|
|
ctl &= ~PCI_EXP_DEVCTL_READRQ;
|
|
|
|
ctl |= v;
|
|
|
|
err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
|
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pcie_set_readrq);
|
|
|
|
|
2006-12-17 18:31:06 -07:00
|
|
|
/**
|
|
|
|
* pci_select_bars - Make BAR mask from the type of resource
|
2007-02-10 15:41:56 -07:00
|
|
|
* @dev: the PCI device for which BAR mask is made
|
2006-12-17 18:31:06 -07:00
|
|
|
* @flags: resource type mask to be selected
|
|
|
|
*
|
|
|
|
* This helper routine makes bar mask from the type of resource.
|
|
|
|
*/
|
|
|
|
int pci_select_bars(struct pci_dev *dev, unsigned long flags)
|
|
|
|
{
|
|
|
|
int i, bars = 0;
|
|
|
|
for (i = 0; i < PCI_NUM_RESOURCES; i++)
|
|
|
|
if (pci_resource_flags(dev, i) & flags)
|
|
|
|
bars |= (1 << i);
|
|
|
|
return bars;
|
|
|
|
}
|
|
|
|
|
2007-10-11 14:57:27 -06:00
|
|
|
static void __devinit pci_no_domains(void)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_PCI_DOMAINS
|
|
|
|
pci_domains_supported = 0;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
static int __devinit pci_init(void)
|
|
|
|
{
|
|
|
|
struct pci_dev *dev = NULL;
|
|
|
|
|
|
|
|
while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
|
|
|
|
pci_fixup_device(pci_fixup_final, dev);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __devinit pci_setup(char *str)
|
|
|
|
{
|
|
|
|
while (str) {
|
|
|
|
char *k = strchr(str, ',');
|
|
|
|
if (k)
|
|
|
|
*k++ = 0;
|
|
|
|
if (*str && (str = pcibios_setup(str)) && *str) {
|
2006-03-05 22:33:34 -07:00
|
|
|
if (!strcmp(str, "nomsi")) {
|
|
|
|
pci_no_msi();
|
2007-10-05 14:17:58 -06:00
|
|
|
} else if (!strcmp(str, "noaer")) {
|
|
|
|
pci_no_aer();
|
2007-10-11 14:57:27 -06:00
|
|
|
} else if (!strcmp(str, "nodomains")) {
|
|
|
|
pci_no_domains();
|
2007-02-05 17:36:06 -07:00
|
|
|
} else if (!strncmp(str, "cbiosize=", 9)) {
|
|
|
|
pci_cardbus_io_size = memparse(str + 9, &str);
|
|
|
|
} else if (!strncmp(str, "cbmemsize=", 10)) {
|
|
|
|
pci_cardbus_mem_size = memparse(str + 10, &str);
|
2006-03-05 22:33:34 -07:00
|
|
|
} else {
|
|
|
|
printk(KERN_ERR "PCI: Unknown option `%s'\n",
|
|
|
|
str);
|
|
|
|
}
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
str = k;
|
|
|
|
}
|
2006-09-26 02:52:41 -06:00
|
|
|
return 0;
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
2006-09-26 02:52:41 -06:00
|
|
|
early_param("pci", pci_setup);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
device_initcall(pci_init);
|
|
|
|
|
2007-07-26 23:43:35 -06:00
|
|
|
EXPORT_SYMBOL(pci_reenable_device);
|
2007-12-19 21:28:08 -07:00
|
|
|
EXPORT_SYMBOL(pci_enable_device_io);
|
|
|
|
EXPORT_SYMBOL(pci_enable_device_mem);
|
2005-04-16 16:20:36 -06:00
|
|
|
EXPORT_SYMBOL(pci_enable_device);
|
devres: device resource management
Implement device resource management, in short, devres. A device
driver can allocate arbirary size of devres data which is associated
with a release function. On driver detach, release function is
invoked on the devres data, then, devres data is freed.
devreses are typed by associated release functions. Some devreses are
better represented by single instance of the type while others need
multiple instances sharing the same release function. Both usages are
supported.
devreses can be grouped using devres group such that a device driver
can easily release acquired resources halfway through initialization
or selectively release resources (e.g. resources for port 1 out of 4
ports).
This patch adds devres core including documentation and the following
managed interfaces.
* alloc/free : devm_kzalloc(), devm_kzfree()
* IO region : devm_request_region(), devm_release_region()
* IRQ : devm_request_irq(), devm_free_irq()
* DMA : dmam_alloc_coherent(), dmam_free_coherent(),
dmam_declare_coherent_memory(), dmam_pool_create(),
dmam_pool_destroy()
* PCI : pcim_enable_device(), pcim_pin_device(), pci_is_managed()
* iomap : devm_ioport_map(), devm_ioport_unmap(), devm_ioremap(),
devm_ioremap_nocache(), devm_iounmap(), pcim_iomap_table(),
pcim_iomap(), pcim_iounmap()
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-01-20 00:00:26 -07:00
|
|
|
EXPORT_SYMBOL(pcim_enable_device);
|
|
|
|
EXPORT_SYMBOL(pcim_pin_device);
|
2005-04-16 16:20:36 -06:00
|
|
|
EXPORT_SYMBOL(pci_disable_device);
|
|
|
|
EXPORT_SYMBOL(pci_find_capability);
|
|
|
|
EXPORT_SYMBOL(pci_bus_find_capability);
|
|
|
|
EXPORT_SYMBOL(pci_release_regions);
|
|
|
|
EXPORT_SYMBOL(pci_request_regions);
|
|
|
|
EXPORT_SYMBOL(pci_release_region);
|
|
|
|
EXPORT_SYMBOL(pci_request_region);
|
2006-12-17 18:31:06 -07:00
|
|
|
EXPORT_SYMBOL(pci_release_selected_regions);
|
|
|
|
EXPORT_SYMBOL(pci_request_selected_regions);
|
2005-04-16 16:20:36 -06:00
|
|
|
EXPORT_SYMBOL(pci_set_master);
|
|
|
|
EXPORT_SYMBOL(pci_set_mwi);
|
2007-07-09 12:55:54 -06:00
|
|
|
EXPORT_SYMBOL(pci_try_set_mwi);
|
2005-04-16 16:20:36 -06:00
|
|
|
EXPORT_SYMBOL(pci_clear_mwi);
|
2005-08-15 13:23:41 -06:00
|
|
|
EXPORT_SYMBOL_GPL(pci_intx);
|
2005-04-16 16:20:36 -06:00
|
|
|
EXPORT_SYMBOL(pci_set_dma_mask);
|
|
|
|
EXPORT_SYMBOL(pci_set_consistent_dma_mask);
|
|
|
|
EXPORT_SYMBOL(pci_assign_resource);
|
|
|
|
EXPORT_SYMBOL(pci_find_parent_resource);
|
2006-12-17 18:31:06 -07:00
|
|
|
EXPORT_SYMBOL(pci_select_bars);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
EXPORT_SYMBOL(pci_set_power_state);
|
|
|
|
EXPORT_SYMBOL(pci_save_state);
|
|
|
|
EXPORT_SYMBOL(pci_restore_state);
|
|
|
|
EXPORT_SYMBOL(pci_enable_wake);
|
2007-04-06 15:39:36 -06:00
|
|
|
EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
|
2005-04-16 16:20:36 -06:00
|
|
|
|