2009-12-04 07:41:28 -07:00
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/*
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* linux/arch/arm/mach-mmp/irq-mmp2.c
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*
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* Generic IRQ handling, GPIO IRQ demultiplexing, etc.
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*
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* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
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* Copyright: Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/regs-icu.h>
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2010-07-15 08:22:33 -06:00
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#include <mach/mmp2.h>
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2009-12-04 07:41:28 -07:00
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#include "common.h"
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static void icu_mask_irq(unsigned int irq)
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{
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uint32_t r = __raw_readl(ICU_INT_CONF(irq));
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r &= ~ICU_INT_ROUTE_PJ4_IRQ;
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__raw_writel(r, ICU_INT_CONF(irq));
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}
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static void icu_unmask_irq(unsigned int irq)
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{
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uint32_t r = __raw_readl(ICU_INT_CONF(irq));
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r |= ICU_INT_ROUTE_PJ4_IRQ;
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__raw_writel(r, ICU_INT_CONF(irq));
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}
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static struct irq_chip icu_irq_chip = {
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.name = "icu_irq",
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2010-01-25 04:02:50 -07:00
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.mask = icu_mask_irq,
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2009-12-04 07:41:28 -07:00
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.mask_ack = icu_mask_irq,
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.unmask = icu_unmask_irq,
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};
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2010-02-03 08:01:18 -07:00
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static void pmic_irq_ack(unsigned int irq)
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{
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if (irq == IRQ_MMP2_PMIC)
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mmp2_clear_pmic_int();
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}
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2009-12-04 07:41:28 -07:00
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#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \
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static void _name_##_mask_irq(unsigned int irq) \
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{ \
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uint32_t r; \
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r = __raw_readl(prefix##_MASK) | (1 << (irq - irq_base)); \
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__raw_writel(r, prefix##_MASK); \
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}
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#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
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static void _name_##_unmask_irq(unsigned int irq) \
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{ \
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uint32_t r; \
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r = __raw_readl(prefix##_MASK) & ~(1 << (irq - irq_base)); \
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__raw_writel(r, prefix##_MASK); \
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}
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#define SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \
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static void _name_##_irq_demux(unsigned int irq, struct irq_desc *desc) \
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{ \
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unsigned long status, mask, n; \
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mask = __raw_readl(prefix##_MASK); \
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while (1) { \
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status = __raw_readl(prefix##_STATUS) & ~mask; \
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if (status == 0) \
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break; \
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n = find_first_bit(&status, BITS_PER_LONG); \
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while (n < BITS_PER_LONG) { \
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generic_handle_irq(irq_base + n); \
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n = find_next_bit(&status, BITS_PER_LONG, n+1); \
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} \
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} \
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}
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#define SECOND_IRQ_CHIP(_name_, irq_base, prefix) \
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SECOND_IRQ_MASK(_name_, irq_base, prefix) \
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SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
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SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \
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static struct irq_chip _name_##_irq_chip = { \
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.name = #_name_, \
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2010-01-25 04:02:50 -07:00
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.mask = _name_##_mask_irq, \
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2009-12-04 07:41:28 -07:00
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.unmask = _name_##_unmask_irq, \
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}
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SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4);
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SECOND_IRQ_CHIP(rtc, IRQ_MMP2_RTC_BASE, MMP2_ICU_INT5);
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SECOND_IRQ_CHIP(twsi, IRQ_MMP2_TWSI_BASE, MMP2_ICU_INT17);
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SECOND_IRQ_CHIP(misc, IRQ_MMP2_MISC_BASE, MMP2_ICU_INT35);
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SECOND_IRQ_CHIP(ssp, IRQ_MMP2_SSP_BASE, MMP2_ICU_INT51);
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static void init_mux_irq(struct irq_chip *chip, int start, int num)
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{
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int irq;
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for (irq = start; num > 0; irq++, num--) {
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2010-02-03 00:39:35 -07:00
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/* mask and clear the IRQ */
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chip->mask(irq);
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if (chip->ack)
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chip->ack(irq);
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2009-12-04 07:41:28 -07:00
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set_irq_chip(irq, chip);
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set_irq_flags(irq, IRQF_VALID);
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set_irq_handler(irq, handle_level_irq);
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}
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}
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2010-01-25 04:03:54 -07:00
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void __init mmp2_init_icu(void)
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2009-12-04 07:41:28 -07:00
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{
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int irq;
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for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
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icu_mask_irq(irq);
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set_irq_chip(irq, &icu_irq_chip);
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set_irq_flags(irq, IRQF_VALID);
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switch (irq) {
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case IRQ_MMP2_PMIC_MUX:
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case IRQ_MMP2_RTC_MUX:
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case IRQ_MMP2_TWSI_MUX:
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case IRQ_MMP2_MISC_MUX:
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case IRQ_MMP2_SSP_MUX:
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break;
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default:
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set_irq_handler(irq, handle_level_irq);
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break;
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}
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}
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2010-02-03 08:01:18 -07:00
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/* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register
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* to be written to clear the interrupt
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*/
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pmic_irq_chip.ack = pmic_irq_ack;
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2009-12-04 07:41:28 -07:00
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init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
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init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);
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init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5);
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init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15);
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init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2);
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set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
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set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
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set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
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set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
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set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
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}
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