365 lines
8.6 KiB
C
365 lines
8.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
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* Author: Olivier Bideau <olivier.bideau@st.com> for STMicroelectronics.
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* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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static DEFINE_SPINLOCK(rlock);
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#define RCC_OCENSETR 0x0C
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#define RCC_HSICFGR 0x18
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#define RCC_RDLSICR 0x144
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#define RCC_PLL1CR 0x80
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#define RCC_PLL1CFGR1 0x84
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#define RCC_PLL1CFGR2 0x88
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#define RCC_PLL2CR 0x94
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#define RCC_PLL2CFGR1 0x98
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#define RCC_PLL2CFGR2 0x9C
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#define RCC_PLL3CR 0x880
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#define RCC_PLL3CFGR1 0x884
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#define RCC_PLL3CFGR2 0x888
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#define RCC_PLL4CR 0x894
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#define RCC_PLL4CFGR1 0x898
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#define RCC_PLL4CFGR2 0x89C
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#define RCC_APB1ENSETR 0xA00
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#define RCC_APB2ENSETR 0xA08
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#define RCC_APB3ENSETR 0xA10
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#define RCC_APB4ENSETR 0x200
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#define RCC_APB5ENSETR 0x208
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#define RCC_AHB2ENSETR 0xA18
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#define RCC_AHB3ENSETR 0xA20
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#define RCC_AHB4ENSETR 0xA28
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#define RCC_AHB5ENSETR 0x210
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#define RCC_AHB6ENSETR 0x218
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#define RCC_AHB6LPENSETR 0x318
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#define RCC_RCK12SELR 0x28
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#define RCC_RCK3SELR 0x820
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#define RCC_RCK4SELR 0x824
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#define RCC_MPCKSELR 0x20
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#define RCC_ASSCKSELR 0x24
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#define RCC_MSSCKSELR 0x48
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#define RCC_SPI6CKSELR 0xC4
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#define RCC_SDMMC12CKSELR 0x8F4
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#define RCC_SDMMC3CKSELR 0x8F8
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#define RCC_FMCCKSELR 0x904
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#define RCC_I2C46CKSELR 0xC0
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#define RCC_I2C12CKSELR 0x8C0
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#define RCC_I2C35CKSELR 0x8C4
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#define RCC_UART1CKSELR 0xC8
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#define RCC_QSPICKSELR 0x900
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#define RCC_ETHCKSELR 0x8FC
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#define RCC_RNG1CKSELR 0xCC
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#define RCC_RNG2CKSELR 0x920
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#define RCC_GPUCKSELR 0x938
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#define RCC_USBCKSELR 0x91C
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#define RCC_STGENCKSELR 0xD4
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#define RCC_SPDIFCKSELR 0x914
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#define RCC_SPI2S1CKSELR 0x8D8
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#define RCC_SPI2S23CKSELR 0x8DC
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#define RCC_SPI2S45CKSELR 0x8E0
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#define RCC_CECCKSELR 0x918
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#define RCC_LPTIM1CKSELR 0x934
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#define RCC_LPTIM23CKSELR 0x930
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#define RCC_LPTIM45CKSELR 0x92C
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#define RCC_UART24CKSELR 0x8E8
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#define RCC_UART35CKSELR 0x8EC
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#define RCC_UART6CKSELR 0x8E4
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#define RCC_UART78CKSELR 0x8F0
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#define RCC_FDCANCKSELR 0x90C
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#define RCC_SAI1CKSELR 0x8C8
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#define RCC_SAI2CKSELR 0x8CC
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#define RCC_SAI3CKSELR 0x8D0
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#define RCC_SAI4CKSELR 0x8D4
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#define RCC_ADCCKSELR 0x928
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#define RCC_MPCKDIVR 0x2C
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#define RCC_DSICKSELR 0x924
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#define RCC_CPERCKSELR 0xD0
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#define RCC_MCO1CFGR 0x800
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#define RCC_MCO2CFGR 0x804
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#define RCC_BDCR 0x140
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#define RCC_AXIDIVR 0x30
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#define RCC_MCUDIVR 0x830
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#define RCC_APB1DIVR 0x834
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#define RCC_APB2DIVR 0x838
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#define RCC_APB3DIVR 0x83C
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#define RCC_APB4DIVR 0x3C
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#define RCC_APB5DIVR 0x40
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#define RCC_TIMG1PRER 0x828
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#define RCC_TIMG2PRER 0x82C
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#define RCC_RTCDIVR 0x44
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#define RCC_DBGCFGR 0x80C
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#define RCC_CLR 0x4
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struct clock_config {
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u32 id;
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const char *name;
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union {
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const char *parent_name;
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const char * const *parent_names;
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};
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int num_parents;
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unsigned long flags;
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void *cfg;
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struct clk_hw * (*func)(struct device *dev,
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struct clk_hw_onecell_data *clk_data,
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void __iomem *base, spinlock_t *lock,
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const struct clock_config *cfg);
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};
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#define NO_ID ~0
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struct gate_cfg {
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u32 reg_off;
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u8 bit_idx;
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u8 gate_flags;
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};
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struct fixed_factor_cfg {
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unsigned int mult;
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unsigned int div;
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};
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struct div_cfg {
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u32 reg_off;
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u8 shift;
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u8 width;
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u8 div_flags;
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const struct clk_div_table *table;
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};
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static struct clk_hw *
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_clk_hw_register_gate(struct device *dev,
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struct clk_hw_onecell_data *clk_data,
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void __iomem *base, spinlock_t *lock,
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const struct clock_config *cfg)
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{
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struct gate_cfg *gate_cfg = cfg->cfg;
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return clk_hw_register_gate(dev,
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cfg->name,
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cfg->parent_name,
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cfg->flags,
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gate_cfg->reg_off + base,
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gate_cfg->bit_idx,
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gate_cfg->gate_flags,
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lock);
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}
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static struct clk_hw *
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_clk_hw_register_fixed_factor(struct device *dev,
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struct clk_hw_onecell_data *clk_data,
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void __iomem *base, spinlock_t *lock,
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const struct clock_config *cfg)
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{
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struct fixed_factor_cfg *ff_cfg = cfg->cfg;
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return clk_hw_register_fixed_factor(dev, cfg->name, cfg->parent_name,
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cfg->flags, ff_cfg->mult,
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ff_cfg->div);
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}
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static struct clk_hw *
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_clk_hw_register_divider_table(struct device *dev,
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struct clk_hw_onecell_data *clk_data,
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void __iomem *base, spinlock_t *lock,
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const struct clock_config *cfg)
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{
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struct div_cfg *div_cfg = cfg->cfg;
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return clk_hw_register_divider_table(dev,
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cfg->name,
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cfg->parent_name,
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cfg->flags,
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div_cfg->reg_off + base,
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div_cfg->shift,
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div_cfg->width,
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div_cfg->div_flags,
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div_cfg->table,
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lock);
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}
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#define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
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{\
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.id = _id,\
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.name = _name,\
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.parent_name = _parent,\
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.flags = _flags,\
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.cfg = &(struct gate_cfg) {\
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.reg_off = _offset,\
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.bit_idx = _bit_idx,\
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.gate_flags = _gate_flags,\
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},\
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.func = _clk_hw_register_gate,\
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}
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#define FIXED_FACTOR(_id, _name, _parent, _flags, _mult, _div)\
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{\
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.id = _id,\
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.name = _name,\
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.parent_name = _parent,\
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.flags = _flags,\
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.cfg = &(struct fixed_factor_cfg) {\
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.mult = _mult,\
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.div = _div,\
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},\
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.func = _clk_hw_register_fixed_factor,\
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}
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#define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
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_div_flags, _div_table)\
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{\
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.id = _id,\
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.name = _name,\
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.parent_name = _parent,\
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.flags = _flags,\
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.cfg = &(struct div_cfg) {\
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.reg_off = _offset,\
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.shift = _shift,\
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.width = _width,\
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.div_flags = _div_flags,\
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.table = _div_table,\
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},\
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.func = _clk_hw_register_divider_table,\
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}
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#define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\
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DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
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_div_flags, NULL)
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static const struct clock_config stm32mp1_clock_cfg[] = {
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/* Oscillator divider */
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DIV(NO_ID, "clk-hsi-div", "clk-hsi", 0, RCC_HSICFGR, 0, 2,
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CLK_DIVIDER_READ_ONLY),
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/* External / Internal Oscillators */
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GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
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GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
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FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
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};
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struct stm32_clock_match_data {
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const struct clock_config *cfg;
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unsigned int num;
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unsigned int maxbinding;
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};
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static struct stm32_clock_match_data stm32mp1_data = {
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.cfg = stm32mp1_clock_cfg,
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.num = ARRAY_SIZE(stm32mp1_clock_cfg),
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.maxbinding = STM32MP1_LAST_CLK,
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};
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static const struct of_device_id stm32mp1_match_data[] = {
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{
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.compatible = "st,stm32mp1-rcc",
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.data = &stm32mp1_data,
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},
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{ }
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};
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static int stm32_register_hw_clk(struct device *dev,
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struct clk_hw_onecell_data *clk_data,
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void __iomem *base, spinlock_t *lock,
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const struct clock_config *cfg)
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{
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static struct clk_hw **hws;
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struct clk_hw *hw = ERR_PTR(-ENOENT);
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hws = clk_data->hws;
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if (cfg->func)
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hw = (*cfg->func)(dev, clk_data, base, lock, cfg);
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if (IS_ERR(hw)) {
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pr_err("Unable to register %s\n", cfg->name);
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return PTR_ERR(hw);
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}
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if (cfg->id != NO_ID)
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hws[cfg->id] = hw;
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return 0;
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}
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static int stm32_rcc_init(struct device_node *np,
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void __iomem *base,
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const struct of_device_id *match_data)
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{
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struct clk_hw_onecell_data *clk_data;
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struct clk_hw **hws;
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const struct of_device_id *match;
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const struct stm32_clock_match_data *data;
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int err, n, max_binding;
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match = of_match_node(match_data, np);
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if (!match) {
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pr_err("%s: match data not found\n", __func__);
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return -ENODEV;
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}
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data = match->data;
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max_binding = data->maxbinding;
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clk_data = kzalloc(sizeof(*clk_data) +
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sizeof(*clk_data->hws) * max_binding,
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GFP_KERNEL);
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if (!clk_data)
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return -ENOMEM;
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clk_data->num = max_binding;
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hws = clk_data->hws;
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for (n = 0; n < max_binding; n++)
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hws[n] = ERR_PTR(-ENOENT);
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for (n = 0; n < data->num; n++) {
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err = stm32_register_hw_clk(NULL, clk_data, base, &rlock,
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&data->cfg[n]);
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if (err) {
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pr_err("%s: can't register %s\n", __func__,
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data->cfg[n].name);
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kfree(clk_data);
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return err;
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}
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}
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return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
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}
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static void stm32mp1_rcc_init(struct device_node *np)
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{
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void __iomem *base;
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base = of_iomap(np, 0);
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if (!base) {
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pr_err("%s: unable to map resource", np->name);
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of_node_put(np);
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return;
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}
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if (stm32_rcc_init(np, base, stm32mp1_match_data)) {
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iounmap(base);
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of_node_put(np);
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}
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}
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CLK_OF_DECLARE_DRIVER(stm32mp1_rcc, "st,stm32mp1-rcc", stm32mp1_rcc_init);
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