2012-05-11 07:35:33 -06:00
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/*
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* Driver for the ADC present in the Atmel AT91 evaluation boards.
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*
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* Copyright 2011 Free Electrons
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*
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* Licensed under the GPLv2 or later.
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*/
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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2012-05-11 07:35:37 -06:00
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#include <linux/of.h>
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#include <linux/of_device.h>
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2012-05-11 07:35:33 -06:00
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/wait.h>
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#include <linux/platform_data/at91_adc.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/trigger.h>
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#include <linux/iio/trigger_consumer.h>
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2012-06-18 10:33:49 -06:00
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#include <linux/iio/triggered_buffer.h>
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2012-05-11 07:35:33 -06:00
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#include <mach/at91_adc.h>
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#define AT91_ADC_CHAN(st, ch) \
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(st->registers->channel_base + (ch * 4))
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#define at91_adc_readl(st, reg) \
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(readl_relaxed(st->reg_base + reg))
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#define at91_adc_writel(st, reg, val) \
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(writel_relaxed(val, st->reg_base + reg))
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2013-08-27 05:28:00 -06:00
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struct at91_adc_caps {
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struct at91_adc_reg_desc registers;
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};
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2012-05-11 07:35:33 -06:00
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struct at91_adc_state {
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struct clk *adc_clk;
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u16 *buffer;
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unsigned long channels_mask;
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struct clk *clk;
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bool done;
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int irq;
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u16 last_value;
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struct mutex lock;
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u8 num_channels;
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void __iomem *reg_base;
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struct at91_adc_reg_desc *registers;
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u8 startup_time;
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2013-03-29 08:54:00 -06:00
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u8 sample_hold_time;
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2013-03-29 08:54:00 -06:00
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bool sleep_mode;
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2012-05-11 07:35:33 -06:00
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struct iio_trigger **trig;
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struct at91_adc_trigger *trigger_list;
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u32 trigger_number;
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bool use_external;
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u32 vref_mv;
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2013-03-29 08:54:00 -06:00
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u32 res; /* resolution used for convertions */
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bool low_res; /* the resolution corresponds to the lowest one */
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2012-05-11 07:35:33 -06:00
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wait_queue_head_t wq_data_avail;
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2013-08-27 05:28:00 -06:00
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struct at91_adc_caps *caps;
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2012-05-11 07:35:33 -06:00
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};
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static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
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{
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struct iio_poll_func *pf = p;
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struct iio_dev *idev = pf->indio_dev;
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struct at91_adc_state *st = iio_priv(idev);
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int i, j = 0;
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for (i = 0; i < idev->masklength; i++) {
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if (!test_bit(i, idev->active_scan_mask))
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continue;
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st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, i));
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j++;
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}
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if (idev->scan_timestamp) {
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s64 *timestamp = (s64 *)((u8 *)st->buffer +
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ALIGN(j, sizeof(s64)));
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*timestamp = pf->timestamp;
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}
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2013-09-15 10:50:00 -06:00
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iio_push_to_buffers(idev, st->buffer);
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2012-05-11 07:35:33 -06:00
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iio_trigger_notify_done(idev->trig);
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/* Needed to ACK the DRDY interruption */
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at91_adc_readl(st, AT91_ADC_LCDR);
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enable_irq(st->irq);
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return IRQ_HANDLED;
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}
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static irqreturn_t at91_adc_eoc_trigger(int irq, void *private)
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{
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struct iio_dev *idev = private;
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struct at91_adc_state *st = iio_priv(idev);
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u32 status = at91_adc_readl(st, st->registers->status_register);
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if (!(status & st->registers->drdy_mask))
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return IRQ_HANDLED;
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if (iio_buffer_enabled(idev)) {
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disable_irq_nosync(irq);
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iio_trigger_poll(idev->trig, iio_get_time_ns());
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} else {
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st->last_value = at91_adc_readl(st, AT91_ADC_LCDR);
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st->done = true;
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wake_up_interruptible(&st->wq_data_avail);
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}
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return IRQ_HANDLED;
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}
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static int at91_adc_channel_init(struct iio_dev *idev)
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{
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struct at91_adc_state *st = iio_priv(idev);
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struct iio_chan_spec *chan_array, *timestamp;
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int bit, idx = 0;
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idev->num_channels = bitmap_weight(&st->channels_mask,
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st->num_channels) + 1;
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2012-10-29 02:25:00 -06:00
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chan_array = devm_kzalloc(&idev->dev,
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((idev->num_channels + 1) *
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sizeof(struct iio_chan_spec)),
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GFP_KERNEL);
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2012-05-11 07:35:33 -06:00
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if (!chan_array)
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return -ENOMEM;
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for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
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struct iio_chan_spec *chan = chan_array + idx;
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chan->type = IIO_VOLTAGE;
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chan->indexed = 1;
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chan->channel = bit;
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chan->scan_index = idx;
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chan->scan_type.sign = 'u';
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2013-03-29 08:54:00 -06:00
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chan->scan_type.realbits = st->res;
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2012-05-11 07:35:33 -06:00
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chan->scan_type.storagebits = 16;
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2013-02-27 12:06:10 -07:00
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chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
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chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
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2012-05-11 07:35:33 -06:00
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idx++;
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}
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timestamp = chan_array + idx;
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timestamp->type = IIO_TIMESTAMP;
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timestamp->channel = -1;
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timestamp->scan_index = idx;
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timestamp->scan_type.sign = 's';
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timestamp->scan_type.realbits = 64;
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timestamp->scan_type.storagebits = 64;
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idev->channels = chan_array;
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return idev->num_channels;
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}
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static u8 at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
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struct at91_adc_trigger *triggers,
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const char *trigger_name)
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{
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struct at91_adc_state *st = iio_priv(idev);
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u8 value = 0;
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int i;
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for (i = 0; i < st->trigger_number; i++) {
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char *name = kasprintf(GFP_KERNEL,
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"%s-dev%d-%s",
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idev->name,
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idev->id,
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triggers[i].name);
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if (!name)
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return -ENOMEM;
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if (strcmp(trigger_name, name) == 0) {
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value = triggers[i].value;
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kfree(name);
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break;
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}
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kfree(name);
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}
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return value;
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}
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static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
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{
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2013-03-25 02:58:00 -06:00
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struct iio_dev *idev = iio_trigger_get_drvdata(trig);
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2012-05-11 07:35:33 -06:00
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struct at91_adc_state *st = iio_priv(idev);
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struct iio_buffer *buffer = idev->buffer;
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struct at91_adc_reg_desc *reg = st->registers;
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u32 status = at91_adc_readl(st, reg->trigger_register);
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u8 value;
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u8 bit;
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value = at91_adc_get_trigger_value_by_name(idev,
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st->trigger_list,
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idev->trig->name);
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if (value == 0)
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return -EINVAL;
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if (state) {
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st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
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if (st->buffer == NULL)
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return -ENOMEM;
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at91_adc_writel(st, reg->trigger_register,
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status | value);
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for_each_set_bit(bit, buffer->scan_mask,
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st->num_channels) {
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struct iio_chan_spec const *chan = idev->channels + bit;
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at91_adc_writel(st, AT91_ADC_CHER,
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AT91_ADC_CH(chan->channel));
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}
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at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
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} else {
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at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
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at91_adc_writel(st, reg->trigger_register,
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status & ~value);
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for_each_set_bit(bit, buffer->scan_mask,
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st->num_channels) {
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struct iio_chan_spec const *chan = idev->channels + bit;
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at91_adc_writel(st, AT91_ADC_CHDR,
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AT91_ADC_CH(chan->channel));
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}
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kfree(st->buffer);
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}
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return 0;
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}
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static const struct iio_trigger_ops at91_adc_trigger_ops = {
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.owner = THIS_MODULE,
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.set_trigger_state = &at91_adc_configure_trigger,
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};
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static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
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struct at91_adc_trigger *trigger)
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{
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struct iio_trigger *trig;
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int ret;
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trig = iio_trigger_alloc("%s-dev%d-%s", idev->name,
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idev->id, trigger->name);
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if (trig == NULL)
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return NULL;
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trig->dev.parent = idev->dev.parent;
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2013-03-25 02:58:00 -06:00
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iio_trigger_set_drvdata(trig, idev);
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2012-05-11 07:35:33 -06:00
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trig->ops = &at91_adc_trigger_ops;
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ret = iio_trigger_register(trig);
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if (ret)
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return NULL;
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return trig;
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}
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static int at91_adc_trigger_init(struct iio_dev *idev)
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{
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struct at91_adc_state *st = iio_priv(idev);
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int i, ret;
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2012-10-29 02:25:00 -06:00
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st->trig = devm_kzalloc(&idev->dev,
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2013-09-19 15:42:00 -06:00
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st->trigger_number * sizeof(*st->trig),
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2012-10-29 02:25:00 -06:00
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GFP_KERNEL);
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2012-05-11 07:35:33 -06:00
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if (st->trig == NULL) {
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ret = -ENOMEM;
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goto error_ret;
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}
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for (i = 0; i < st->trigger_number; i++) {
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if (st->trigger_list[i].is_external && !(st->use_external))
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continue;
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st->trig[i] = at91_adc_allocate_trigger(idev,
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st->trigger_list + i);
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if (st->trig[i] == NULL) {
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dev_err(&idev->dev,
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"Could not allocate trigger %d\n", i);
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ret = -ENOMEM;
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goto error_trigger;
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}
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}
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return 0;
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error_trigger:
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for (i--; i >= 0; i--) {
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iio_trigger_unregister(st->trig[i]);
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iio_trigger_free(st->trig[i]);
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}
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error_ret:
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return ret;
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}
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static void at91_adc_trigger_remove(struct iio_dev *idev)
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{
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struct at91_adc_state *st = iio_priv(idev);
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int i;
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for (i = 0; i < st->trigger_number; i++) {
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iio_trigger_unregister(st->trig[i]);
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iio_trigger_free(st->trig[i]);
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}
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}
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static int at91_adc_buffer_init(struct iio_dev *idev)
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{
|
2012-06-18 10:33:49 -06:00
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return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
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&at91_adc_trigger_handler, NULL);
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2012-05-11 07:35:33 -06:00
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}
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static void at91_adc_buffer_remove(struct iio_dev *idev)
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{
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2012-06-18 10:33:49 -06:00
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iio_triggered_buffer_cleanup(idev);
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2012-05-11 07:35:33 -06:00
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}
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static int at91_adc_read_raw(struct iio_dev *idev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct at91_adc_state *st = iio_priv(idev);
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int ret;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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mutex_lock(&st->lock);
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at91_adc_writel(st, AT91_ADC_CHER,
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AT91_ADC_CH(chan->channel));
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|
|
at91_adc_writel(st, AT91_ADC_IER, st->registers->drdy_mask);
|
|
|
|
at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
|
|
|
|
|
|
|
|
ret = wait_event_interruptible_timeout(st->wq_data_avail,
|
|
|
|
st->done,
|
|
|
|
msecs_to_jiffies(1000));
|
|
|
|
if (ret == 0)
|
2012-06-26 02:43:05 -06:00
|
|
|
ret = -ETIMEDOUT;
|
|
|
|
if (ret < 0) {
|
|
|
|
mutex_unlock(&st->lock);
|
2012-05-11 07:35:33 -06:00
|
|
|
return ret;
|
2012-06-26 02:43:05 -06:00
|
|
|
}
|
2012-05-11 07:35:33 -06:00
|
|
|
|
|
|
|
*val = st->last_value;
|
|
|
|
|
|
|
|
at91_adc_writel(st, AT91_ADC_CHDR,
|
|
|
|
AT91_ADC_CH(chan->channel));
|
|
|
|
at91_adc_writel(st, AT91_ADC_IDR, st->registers->drdy_mask);
|
|
|
|
|
|
|
|
st->last_value = 0;
|
|
|
|
st->done = false;
|
|
|
|
mutex_unlock(&st->lock);
|
|
|
|
return IIO_VAL_INT;
|
|
|
|
|
|
|
|
case IIO_CHAN_INFO_SCALE:
|
|
|
|
*val = (st->vref_mv * 1000) >> chan->scan_type.realbits;
|
|
|
|
*val2 = 0;
|
|
|
|
return IIO_VAL_INT_PLUS_MICRO;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2013-03-29 08:54:00 -06:00
|
|
|
static int at91_adc_of_get_resolution(struct at91_adc_state *st,
|
|
|
|
struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct iio_dev *idev = iio_priv_to_dev(st);
|
|
|
|
struct device_node *np = pdev->dev.of_node;
|
|
|
|
int count, i, ret = 0;
|
|
|
|
char *res_name, *s;
|
|
|
|
u32 *resolutions;
|
|
|
|
|
|
|
|
count = of_property_count_strings(np, "atmel,adc-res-names");
|
|
|
|
if (count < 2) {
|
|
|
|
dev_err(&idev->dev, "You must specified at least two resolution names for "
|
|
|
|
"adc-res-names property in the DT\n");
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
|
|
|
resolutions = kmalloc(count * sizeof(*resolutions), GFP_KERNEL);
|
|
|
|
if (!resolutions)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) {
|
|
|
|
dev_err(&idev->dev, "Missing adc-res property in the DT.\n");
|
|
|
|
ret = -ENODEV;
|
|
|
|
goto ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name))
|
|
|
|
res_name = "highres";
|
|
|
|
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (strcmp(res_name, s))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
st->res = resolutions[i];
|
|
|
|
if (!strcmp(res_name, "lowres"))
|
|
|
|
st->low_res = true;
|
|
|
|
else
|
|
|
|
st->low_res = false;
|
|
|
|
|
|
|
|
dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
|
|
|
|
goto ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_err(&idev->dev, "There is no resolution for %s\n", res_name);
|
|
|
|
|
|
|
|
ret:
|
|
|
|
kfree(resolutions);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-08-27 05:28:00 -06:00
|
|
|
static const struct of_device_id at91_adc_dt_ids[];
|
|
|
|
|
2012-05-11 07:35:37 -06:00
|
|
|
static int at91_adc_probe_dt(struct at91_adc_state *st,
|
|
|
|
struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct iio_dev *idev = iio_priv_to_dev(st);
|
|
|
|
struct device_node *node = pdev->dev.of_node;
|
|
|
|
struct device_node *trig_node;
|
|
|
|
int i = 0, ret;
|
|
|
|
u32 prop;
|
|
|
|
|
|
|
|
if (!node)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2013-08-27 05:28:00 -06:00
|
|
|
st->caps = (struct at91_adc_caps *)
|
|
|
|
of_match_device(at91_adc_dt_ids, &pdev->dev)->data;
|
|
|
|
|
2012-05-11 07:35:37 -06:00
|
|
|
st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
|
|
|
|
|
|
|
|
if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
|
|
|
|
dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error_ret;
|
|
|
|
}
|
|
|
|
st->channels_mask = prop;
|
|
|
|
|
|
|
|
if (of_property_read_u32(node, "atmel,adc-num-channels", &prop)) {
|
|
|
|
dev_err(&idev->dev, "Missing adc-num-channels property in the DT.\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error_ret;
|
|
|
|
}
|
|
|
|
st->num_channels = prop;
|
|
|
|
|
2013-03-29 08:54:00 -06:00
|
|
|
st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode");
|
|
|
|
|
2012-05-11 07:35:37 -06:00
|
|
|
if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
|
|
|
|
dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error_ret;
|
|
|
|
}
|
|
|
|
st->startup_time = prop;
|
|
|
|
|
2013-03-29 08:54:00 -06:00
|
|
|
prop = 0;
|
|
|
|
of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop);
|
|
|
|
st->sample_hold_time = prop;
|
2012-05-11 07:35:37 -06:00
|
|
|
|
|
|
|
if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
|
|
|
|
dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error_ret;
|
|
|
|
}
|
|
|
|
st->vref_mv = prop;
|
|
|
|
|
2013-03-29 08:54:00 -06:00
|
|
|
ret = at91_adc_of_get_resolution(st, pdev);
|
|
|
|
if (ret)
|
|
|
|
goto error_ret;
|
|
|
|
|
2013-08-27 05:28:00 -06:00
|
|
|
st->registers = &st->caps->registers;
|
2012-05-11 07:35:37 -06:00
|
|
|
st->trigger_number = of_get_child_count(node);
|
2012-10-29 02:25:00 -06:00
|
|
|
st->trigger_list = devm_kzalloc(&idev->dev, st->trigger_number *
|
|
|
|
sizeof(struct at91_adc_trigger),
|
|
|
|
GFP_KERNEL);
|
2012-05-11 07:35:37 -06:00
|
|
|
if (!st->trigger_list) {
|
|
|
|
dev_err(&idev->dev, "Could not allocate trigger list memory.\n");
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto error_ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
for_each_child_of_node(node, trig_node) {
|
|
|
|
struct at91_adc_trigger *trig = st->trigger_list + i;
|
|
|
|
const char *name;
|
|
|
|
|
|
|
|
if (of_property_read_string(trig_node, "trigger-name", &name)) {
|
|
|
|
dev_err(&idev->dev, "Missing trigger-name property in the DT.\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error_ret;
|
|
|
|
}
|
|
|
|
trig->name = name;
|
|
|
|
|
|
|
|
if (of_property_read_u32(trig_node, "trigger-value", &prop)) {
|
|
|
|
dev_err(&idev->dev, "Missing trigger-value property in the DT.\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error_ret;
|
|
|
|
}
|
|
|
|
trig->value = prop;
|
|
|
|
trig->is_external = of_property_read_bool(trig_node, "trigger-external");
|
|
|
|
i++;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
error_ret:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-05-11 07:35:33 -06:00
|
|
|
static int at91_adc_probe_pdata(struct at91_adc_state *st,
|
|
|
|
struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct at91_adc_data *pdata = pdev->dev.platform_data;
|
|
|
|
|
|
|
|
if (!pdata)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
st->use_external = pdata->use_external_triggers;
|
|
|
|
st->vref_mv = pdata->vref;
|
|
|
|
st->channels_mask = pdata->channels_used;
|
|
|
|
st->num_channels = pdata->num_channels;
|
|
|
|
st->startup_time = pdata->startup_time;
|
|
|
|
st->trigger_number = pdata->trigger_number;
|
|
|
|
st->trigger_list = pdata->trigger_list;
|
|
|
|
st->registers = pdata->registers;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct iio_info at91_adc_info = {
|
|
|
|
.driver_module = THIS_MODULE,
|
|
|
|
.read_raw = &at91_adc_read_raw,
|
|
|
|
};
|
|
|
|
|
2012-12-21 14:21:43 -07:00
|
|
|
static int at91_adc_probe(struct platform_device *pdev)
|
2012-05-11 07:35:33 -06:00
|
|
|
{
|
2013-03-29 08:54:00 -06:00
|
|
|
unsigned int prsc, mstrclk, ticks, adc_clk, shtim;
|
2012-05-11 07:35:33 -06:00
|
|
|
int ret;
|
|
|
|
struct iio_dev *idev;
|
|
|
|
struct at91_adc_state *st;
|
|
|
|
struct resource *res;
|
2013-03-29 08:54:00 -06:00
|
|
|
u32 reg;
|
2012-05-11 07:35:33 -06:00
|
|
|
|
2013-07-22 05:02:00 -06:00
|
|
|
idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state));
|
|
|
|
if (!idev)
|
|
|
|
return -ENOMEM;
|
2012-05-11 07:35:33 -06:00
|
|
|
|
|
|
|
st = iio_priv(idev);
|
|
|
|
|
2012-05-11 07:35:37 -06:00
|
|
|
if (pdev->dev.of_node)
|
|
|
|
ret = at91_adc_probe_dt(st, pdev);
|
|
|
|
else
|
|
|
|
ret = at91_adc_probe_pdata(st, pdev);
|
|
|
|
|
2012-05-11 07:35:33 -06:00
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "No platform data available.\n");
|
2013-07-22 05:02:00 -06:00
|
|
|
return -EINVAL;
|
2012-05-11 07:35:33 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, idev);
|
|
|
|
|
|
|
|
idev->dev.parent = &pdev->dev;
|
|
|
|
idev->name = dev_name(&pdev->dev);
|
|
|
|
idev->modes = INDIO_DIRECT_MODE;
|
|
|
|
idev->info = &at91_adc_info;
|
|
|
|
|
|
|
|
st->irq = platform_get_irq(pdev, 0);
|
|
|
|
if (st->irq < 0) {
|
|
|
|
dev_err(&pdev->dev, "No IRQ ID is designated\n");
|
2013-07-22 05:02:00 -06:00
|
|
|
return -ENODEV;
|
2012-05-11 07:35:33 -06:00
|
|
|
}
|
|
|
|
|
2012-07-31 07:09:00 -06:00
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2012-05-11 07:35:33 -06:00
|
|
|
|
2013-01-21 03:09:04 -07:00
|
|
|
st->reg_base = devm_ioremap_resource(&pdev->dev, res);
|
|
|
|
if (IS_ERR(st->reg_base)) {
|
2013-07-22 05:02:00 -06:00
|
|
|
return PTR_ERR(st->reg_base);
|
2012-05-11 07:35:33 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable all IRQs before setting up the handler
|
|
|
|
*/
|
|
|
|
at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
|
|
|
|
at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
|
|
|
|
ret = request_irq(st->irq,
|
|
|
|
at91_adc_eoc_trigger,
|
|
|
|
0,
|
|
|
|
pdev->dev.driver->name,
|
|
|
|
idev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
|
2013-07-22 05:02:00 -06:00
|
|
|
return ret;
|
2012-05-11 07:35:33 -06:00
|
|
|
}
|
|
|
|
|
2012-07-31 07:09:00 -06:00
|
|
|
st->clk = devm_clk_get(&pdev->dev, "adc_clk");
|
2012-05-11 07:35:33 -06:00
|
|
|
if (IS_ERR(st->clk)) {
|
|
|
|
dev_err(&pdev->dev, "Failed to get the clock.\n");
|
|
|
|
ret = PTR_ERR(st->clk);
|
|
|
|
goto error_free_irq;
|
|
|
|
}
|
|
|
|
|
2012-08-26 10:00:00 -06:00
|
|
|
ret = clk_prepare_enable(st->clk);
|
2012-05-11 07:35:33 -06:00
|
|
|
if (ret) {
|
2012-08-26 10:00:00 -06:00
|
|
|
dev_err(&pdev->dev,
|
|
|
|
"Could not prepare or enable the clock.\n");
|
2012-07-31 07:09:00 -06:00
|
|
|
goto error_free_irq;
|
2012-05-11 07:35:33 -06:00
|
|
|
}
|
|
|
|
|
2012-07-31 07:09:00 -06:00
|
|
|
st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
|
2012-05-11 07:35:33 -06:00
|
|
|
if (IS_ERR(st->adc_clk)) {
|
|
|
|
dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
|
2012-08-25 13:57:09 -06:00
|
|
|
ret = PTR_ERR(st->adc_clk);
|
2012-05-11 07:35:33 -06:00
|
|
|
goto error_disable_clk;
|
|
|
|
}
|
|
|
|
|
2012-08-26 10:00:00 -06:00
|
|
|
ret = clk_prepare_enable(st->adc_clk);
|
2012-05-11 07:35:33 -06:00
|
|
|
if (ret) {
|
2012-08-26 10:00:00 -06:00
|
|
|
dev_err(&pdev->dev,
|
|
|
|
"Could not prepare or enable the ADC clock.\n");
|
2012-07-31 07:09:00 -06:00
|
|
|
goto error_disable_clk;
|
2012-05-11 07:35:33 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Prescaler rate computation using the formula from the Atmel's
|
|
|
|
* datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
|
|
|
|
* specified by the electrical characteristics of the board.
|
|
|
|
*/
|
|
|
|
mstrclk = clk_get_rate(st->clk);
|
|
|
|
adc_clk = clk_get_rate(st->adc_clk);
|
|
|
|
prsc = (mstrclk / (2 * adc_clk)) - 1;
|
|
|
|
|
|
|
|
if (!st->startup_time) {
|
|
|
|
dev_err(&pdev->dev, "No startup time available.\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto error_disable_adc_clk;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Number of ticks needed to cover the startup time of the ADC as
|
|
|
|
* defined in the electrical characteristics of the board, divided by 8.
|
|
|
|
* The formula thus is : Startup Time = (ticks + 1) * 8 / ADC Clock
|
|
|
|
*/
|
|
|
|
ticks = round_up((st->startup_time * adc_clk /
|
|
|
|
1000000) - 1, 8) / 8;
|
2013-03-29 08:54:00 -06:00
|
|
|
/*
|
|
|
|
* a minimal Sample and Hold Time is necessary for the ADC to guarantee
|
|
|
|
* the best converted final value between two channels selection
|
|
|
|
* The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
|
|
|
|
*/
|
|
|
|
shtim = round_up((st->sample_hold_time * adc_clk /
|
|
|
|
1000000) - 1, 1);
|
|
|
|
|
2013-08-27 05:28:00 -06:00
|
|
|
reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
|
|
|
|
reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
|
2013-03-29 08:54:00 -06:00
|
|
|
if (st->low_res)
|
2013-03-29 08:54:00 -06:00
|
|
|
reg |= AT91_ADC_LOWRES;
|
|
|
|
if (st->sleep_mode)
|
|
|
|
reg |= AT91_ADC_SLEEP;
|
2013-03-29 08:54:00 -06:00
|
|
|
reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM;
|
2013-03-29 08:54:00 -06:00
|
|
|
at91_adc_writel(st, AT91_ADC_MR, reg);
|
2012-05-11 07:35:33 -06:00
|
|
|
|
|
|
|
/* Setup the ADC channels available on the board */
|
|
|
|
ret = at91_adc_channel_init(idev);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
|
|
|
|
goto error_disable_adc_clk;
|
|
|
|
}
|
|
|
|
|
|
|
|
init_waitqueue_head(&st->wq_data_avail);
|
|
|
|
mutex_init(&st->lock);
|
|
|
|
|
|
|
|
ret = at91_adc_buffer_init(idev);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
|
|
|
|
goto error_disable_adc_clk;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = at91_adc_trigger_init(idev);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
|
|
|
|
goto error_unregister_buffer;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = iio_device_register(idev);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&pdev->dev, "Couldn't register the device.\n");
|
|
|
|
goto error_remove_triggers;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
error_remove_triggers:
|
|
|
|
at91_adc_trigger_remove(idev);
|
|
|
|
error_unregister_buffer:
|
|
|
|
at91_adc_buffer_remove(idev);
|
|
|
|
error_disable_adc_clk:
|
2012-08-26 10:00:00 -06:00
|
|
|
clk_disable_unprepare(st->adc_clk);
|
2012-05-11 07:35:33 -06:00
|
|
|
error_disable_clk:
|
2012-08-26 10:00:00 -06:00
|
|
|
clk_disable_unprepare(st->clk);
|
2012-05-11 07:35:33 -06:00
|
|
|
error_free_irq:
|
|
|
|
free_irq(st->irq, idev);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-12-21 14:21:43 -07:00
|
|
|
static int at91_adc_remove(struct platform_device *pdev)
|
2012-05-11 07:35:33 -06:00
|
|
|
{
|
|
|
|
struct iio_dev *idev = platform_get_drvdata(pdev);
|
|
|
|
struct at91_adc_state *st = iio_priv(idev);
|
|
|
|
|
|
|
|
iio_device_unregister(idev);
|
|
|
|
at91_adc_trigger_remove(idev);
|
|
|
|
at91_adc_buffer_remove(idev);
|
|
|
|
clk_disable_unprepare(st->adc_clk);
|
2012-08-26 10:00:00 -06:00
|
|
|
clk_disable_unprepare(st->clk);
|
2012-05-11 07:35:33 -06:00
|
|
|
free_irq(st->irq, idev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-05-22 23:26:00 -06:00
|
|
|
#ifdef CONFIG_OF
|
2013-08-27 05:28:00 -06:00
|
|
|
static struct at91_adc_caps at91sam9260_caps = {
|
|
|
|
.registers = {
|
|
|
|
.channel_base = AT91_ADC_CHR(0),
|
|
|
|
.drdy_mask = AT91_ADC_DRDY,
|
|
|
|
.status_register = AT91_ADC_SR,
|
|
|
|
.trigger_register = AT91_ADC_TRGR_9260,
|
2013-08-27 05:28:00 -06:00
|
|
|
.mr_prescal_mask = AT91_ADC_PRESCAL_9260,
|
|
|
|
.mr_startup_mask = AT91_ADC_STARTUP_9260,
|
2013-08-27 05:28:00 -06:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct at91_adc_caps at91sam9g45_caps = {
|
|
|
|
.registers = {
|
|
|
|
.channel_base = AT91_ADC_CHR(0),
|
|
|
|
.drdy_mask = AT91_ADC_DRDY,
|
|
|
|
.status_register = AT91_ADC_SR,
|
|
|
|
.trigger_register = AT91_ADC_TRGR_9G45,
|
2013-08-27 05:28:00 -06:00
|
|
|
.mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
|
|
|
|
.mr_startup_mask = AT91_ADC_STARTUP_9G45,
|
2013-08-27 05:28:00 -06:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct at91_adc_caps at91sam9x5_caps = {
|
|
|
|
.registers = {
|
|
|
|
.channel_base = AT91_ADC_CDR0_9X5,
|
|
|
|
.drdy_mask = AT91_ADC_SR_DRDY_9X5,
|
|
|
|
.status_register = AT91_ADC_SR_9X5,
|
|
|
|
.trigger_register = AT91_ADC_TRGR_9X5,
|
2013-08-27 05:28:00 -06:00
|
|
|
/* prescal mask is same as 9G45 */
|
|
|
|
.mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
|
|
|
|
.mr_startup_mask = AT91_ADC_STARTUP_9X5,
|
2013-08-27 05:28:00 -06:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-05-11 07:35:37 -06:00
|
|
|
static const struct of_device_id at91_adc_dt_ids[] = {
|
2013-08-27 05:28:00 -06:00
|
|
|
{ .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps },
|
|
|
|
{ .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps },
|
|
|
|
{ .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps },
|
2012-05-11 07:35:37 -06:00
|
|
|
{},
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
|
2013-05-22 23:26:00 -06:00
|
|
|
#endif
|
2012-05-11 07:35:37 -06:00
|
|
|
|
2012-05-11 07:35:33 -06:00
|
|
|
static struct platform_driver at91_adc_driver = {
|
|
|
|
.probe = at91_adc_probe,
|
2012-12-21 14:21:43 -07:00
|
|
|
.remove = at91_adc_remove,
|
2012-05-11 07:35:33 -06:00
|
|
|
.driver = {
|
|
|
|
.name = "at91_adc",
|
2012-05-11 07:35:37 -06:00
|
|
|
.of_match_table = of_match_ptr(at91_adc_dt_ids),
|
2012-05-11 07:35:33 -06:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
module_platform_driver(at91_adc_driver);
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
|
|
|
|
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
|