2012-02-01 14:04:47 -07:00
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/*
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* Driver for the NVIDIA Tegra pinmux
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*
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* Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
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*
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* Derived from code:
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* Copyright (C) 2010 Google, Inc.
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* Copyright (C) 2010 NVIDIA Corporation
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* Copyright (C) 2009-2011 ST-Ericsson AB
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/pinctrl/pinconf.h>
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#include <mach/pinconf-tegra.h>
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#include "pinctrl-tegra.h"
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#define DRIVER_NAME "tegra-pinmux-disabled"
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struct tegra_pmx {
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struct device *dev;
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struct pinctrl_dev *pctl;
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const struct tegra_pinctrl_soc_data *soc;
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int nbanks;
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void __iomem **regs;
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};
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static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
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{
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return readl(pmx->regs[bank] + reg);
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}
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static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
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{
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writel(val, pmx->regs[bank] + reg);
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}
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2012-03-29 23:55:40 -06:00
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static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
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2012-02-01 14:04:47 -07:00
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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2012-03-29 23:55:40 -06:00
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return pmx->soc->ngroups;
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2012-02-01 14:04:47 -07:00
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}
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static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
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unsigned group)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->soc->groups[group].name;
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}
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static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned group,
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const unsigned **pins,
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unsigned *num_pins)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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*pins = pmx->soc->groups[group].pins;
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*num_pins = pmx->soc->groups[group].npins;
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return 0;
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}
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static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
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struct seq_file *s,
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unsigned offset)
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{
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seq_printf(s, " " DRIVER_NAME);
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}
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static struct pinctrl_ops tegra_pinctrl_ops = {
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2012-03-29 23:55:40 -06:00
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.get_groups_count = tegra_pinctrl_get_groups_count,
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2012-02-01 14:04:47 -07:00
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.get_group_name = tegra_pinctrl_get_group_name,
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.get_group_pins = tegra_pinctrl_get_group_pins,
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.pin_dbg_show = tegra_pinctrl_pin_dbg_show,
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};
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2012-03-29 23:55:40 -06:00
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static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
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2012-02-01 14:04:47 -07:00
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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2012-03-29 23:55:40 -06:00
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return pmx->soc->nfunctions;
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2012-02-01 14:04:47 -07:00
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}
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static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
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unsigned function)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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return pmx->soc->functions[function].name;
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}
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static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
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unsigned function,
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const char * const **groups,
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unsigned * const num_groups)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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*groups = pmx->soc->functions[function].groups;
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*num_groups = pmx->soc->functions[function].ngroups;
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return 0;
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}
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static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
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unsigned group)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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const struct tegra_pingroup *g;
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int i;
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u32 val;
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g = &pmx->soc->groups[group];
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if (g->mux_reg < 0)
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return -EINVAL;
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for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
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if (g->funcs[i] == function)
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break;
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}
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if (i == ARRAY_SIZE(g->funcs))
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return -EINVAL;
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val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
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val &= ~(0x3 << g->mux_bit);
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val |= i << g->mux_bit;
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pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
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return 0;
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}
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static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
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unsigned function, unsigned group)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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const struct tegra_pingroup *g;
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u32 val;
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g = &pmx->soc->groups[group];
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if (g->mux_reg < 0)
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return;
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val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
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val &= ~(0x3 << g->mux_bit);
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val |= g->func_safe << g->mux_bit;
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pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
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}
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static struct pinmux_ops tegra_pinmux_ops = {
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2012-03-29 23:55:40 -06:00
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.get_functions_count = tegra_pinctrl_get_funcs_count,
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2012-02-01 14:04:47 -07:00
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.get_function_name = tegra_pinctrl_get_func_name,
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.get_function_groups = tegra_pinctrl_get_func_groups,
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.enable = tegra_pinctrl_enable,
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.disable = tegra_pinctrl_disable,
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};
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static int tegra_pinconf_reg(struct tegra_pmx *pmx,
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const struct tegra_pingroup *g,
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enum tegra_pinconf_param param,
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s8 *bank, s16 *reg, s8 *bit, s8 *width)
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{
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switch (param) {
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case TEGRA_PINCONF_PARAM_PULL:
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*bank = g->pupd_bank;
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*reg = g->pupd_reg;
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*bit = g->pupd_bit;
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*width = 2;
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break;
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case TEGRA_PINCONF_PARAM_TRISTATE:
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*bank = g->tri_bank;
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*reg = g->tri_reg;
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*bit = g->tri_bit;
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*width = 1;
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break;
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case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
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*bank = g->einput_bank;
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*reg = g->einput_reg;
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*bit = g->einput_bit;
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*width = 1;
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break;
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case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
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*bank = g->odrain_bank;
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*reg = g->odrain_reg;
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*bit = g->odrain_bit;
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*width = 1;
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break;
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case TEGRA_PINCONF_PARAM_LOCK:
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*bank = g->lock_bank;
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*reg = g->lock_reg;
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*bit = g->lock_bit;
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*width = 1;
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break;
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case TEGRA_PINCONF_PARAM_IORESET:
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*bank = g->ioreset_bank;
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*reg = g->ioreset_reg;
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*bit = g->ioreset_bit;
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*width = 1;
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break;
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case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
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*bank = g->drv_bank;
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*reg = g->drv_reg;
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*bit = g->hsm_bit;
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*width = 1;
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break;
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case TEGRA_PINCONF_PARAM_SCHMITT:
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*bank = g->drv_bank;
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*reg = g->drv_reg;
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*bit = g->schmitt_bit;
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*width = 1;
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break;
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case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
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*bank = g->drv_bank;
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*reg = g->drv_reg;
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*bit = g->lpmd_bit;
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*width = 1;
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break;
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case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
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*bank = g->drv_bank;
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*reg = g->drv_reg;
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*bit = g->drvdn_bit;
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*width = g->drvdn_width;
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break;
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case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
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*bank = g->drv_bank;
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*reg = g->drv_reg;
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*bit = g->drvup_bit;
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*width = g->drvup_width;
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break;
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case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
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*bank = g->drv_bank;
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*reg = g->drv_reg;
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*bit = g->slwf_bit;
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*width = g->slwf_width;
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break;
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case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
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*bank = g->drv_bank;
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*reg = g->drv_reg;
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*bit = g->slwr_bit;
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*width = g->slwr_width;
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break;
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default:
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dev_err(pmx->dev, "Invalid config param %04x\n", param);
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return -ENOTSUPP;
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}
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if (*reg < 0) {
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dev_err(pmx->dev,
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"Config param %04x not supported on group %s\n",
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param, g->name);
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return -ENOTSUPP;
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}
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return 0;
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}
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static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
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unsigned pin, unsigned long *config)
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{
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return -ENOTSUPP;
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}
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static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
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unsigned pin, unsigned long config)
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{
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return -ENOTSUPP;
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}
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static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
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unsigned group, unsigned long *config)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
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u16 arg;
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const struct tegra_pingroup *g;
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int ret;
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s8 bank, bit, width;
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s16 reg;
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u32 val, mask;
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g = &pmx->soc->groups[group];
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ret = tegra_pinconf_reg(pmx, g, param, &bank, ®, &bit, &width);
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if (ret < 0)
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return ret;
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val = pmx_readl(pmx, bank, reg);
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mask = (1 << width) - 1;
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arg = (val >> bit) & mask;
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*config = TEGRA_PINCONF_PACK(param, arg);
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return 0;
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}
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static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
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unsigned group, unsigned long config)
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{
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struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
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u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
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const struct tegra_pingroup *g;
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int ret;
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s8 bank, bit, width;
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s16 reg;
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u32 val, mask;
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g = &pmx->soc->groups[group];
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ret = tegra_pinconf_reg(pmx, g, param, &bank, ®, &bit, &width);
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if (ret < 0)
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return ret;
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val = pmx_readl(pmx, bank, reg);
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/* LOCK can't be cleared */
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if (param == TEGRA_PINCONF_PARAM_LOCK) {
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if ((val & BIT(bit)) && !arg)
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return -EINVAL;
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}
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/* Special-case Boolean values; allow any non-zero as true */
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if (width == 1)
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arg = !!arg;
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/* Range-check user-supplied value */
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mask = (1 << width) - 1;
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if (arg & ~mask)
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return -EINVAL;
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/* Update register */
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val &= ~(mask << bit);
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val |= arg << bit;
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pmx_writel(pmx, val, bank, reg);
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return 0;
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}
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static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
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struct seq_file *s, unsigned offset)
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{
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}
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static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
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struct seq_file *s, unsigned selector)
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{
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}
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struct pinconf_ops tegra_pinconf_ops = {
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.pin_config_get = tegra_pinconf_get,
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.pin_config_set = tegra_pinconf_set,
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.pin_config_group_get = tegra_pinconf_group_get,
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.pin_config_group_set = tegra_pinconf_group_set,
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.pin_config_dbg_show = tegra_pinconf_dbg_show,
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.pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
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};
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static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
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.name = "Tegra GPIOs",
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.id = 0,
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.base = 0,
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};
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static struct pinctrl_desc tegra_pinctrl_desc = {
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.name = DRIVER_NAME,
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.pctlops = &tegra_pinctrl_ops,
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.pmxops = &tegra_pinmux_ops,
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.confops = &tegra_pinconf_ops,
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.owner = THIS_MODULE,
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};
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static struct of_device_id tegra_pinctrl_of_match[] __devinitdata = {
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#ifdef CONFIG_PINCTRL_TEGRA20
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{
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.compatible = "nvidia,tegra20-pinmux-disabled",
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.data = tegra20_pinctrl_init,
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},
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#endif
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#ifdef CONFIG_PINCTRL_TEGRA30
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{
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.compatible = "nvidia,tegra30-pinmux-disabled",
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.data = tegra30_pinctrl_init,
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},
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#endif
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{},
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};
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static int __devinit tegra_pinctrl_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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tegra_pinctrl_soc_initf initf = NULL;
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struct tegra_pmx *pmx;
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struct resource *res;
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int i;
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match = of_match_device(tegra_pinctrl_of_match, &pdev->dev);
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if (match)
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initf = (tegra_pinctrl_soc_initf)match->data;
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#ifdef CONFIG_PINCTRL_TEGRA20
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if (!initf)
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initf = tegra20_pinctrl_init;
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#endif
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if (!initf) {
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dev_err(&pdev->dev,
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"Could not determine SoC-specific init func\n");
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return -EINVAL;
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}
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pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
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if (!pmx) {
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dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
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return -ENOMEM;
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}
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pmx->dev = &pdev->dev;
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(*initf)(&pmx->soc);
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tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
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tegra_pinctrl_desc.pins = pmx->soc->pins;
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tegra_pinctrl_desc.npins = pmx->soc->npins;
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for (i = 0; ; i++) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, i);
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if (!res)
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break;
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}
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pmx->nbanks = i;
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pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
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GFP_KERNEL);
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if (!pmx->regs) {
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dev_err(&pdev->dev, "Can't alloc regs pointer\n");
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return -ENODEV;
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}
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for (i = 0; i < pmx->nbanks; i++) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, i);
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if (!res) {
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dev_err(&pdev->dev, "Missing MEM resource\n");
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return -ENODEV;
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}
|
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|
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if (!devm_request_mem_region(&pdev->dev, res->start,
|
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|
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resource_size(res),
|
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|
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dev_name(&pdev->dev))) {
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|
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dev_err(&pdev->dev,
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|
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"Couldn't request MEM resource %d\n", i);
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return -ENODEV;
|
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}
|
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|
|
pmx->regs[i] = devm_ioremap(&pdev->dev, res->start,
|
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|
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resource_size(res));
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|
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if (!pmx->regs[i]) {
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dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
|
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|
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return -ENODEV;
|
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|
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}
|
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}
|
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|
|
pmx->pctl = pinctrl_register(&tegra_pinctrl_desc, &pdev->dev, pmx);
|
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|
|
if (IS_ERR(pmx->pctl)) {
|
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|
|
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
|
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|
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return PTR_ERR(pmx->pctl);
|
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}
|
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|
|
pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
|
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|
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platform_set_drvdata(pdev, pmx);
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|
|
dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
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|
|
return 0;
|
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|
|
}
|
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|
|
static int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
|
|
|
|
{
|
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|
|
struct tegra_pmx *pmx = platform_get_drvdata(pdev);
|
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|
|
|
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|
|
pinctrl_remove_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
|
|
|
|
pinctrl_unregister(pmx->pctl);
|
|
|
|
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|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver tegra_pinctrl_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = DRIVER_NAME,
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.of_match_table = tegra_pinctrl_of_match,
|
|
|
|
},
|
|
|
|
.probe = tegra_pinctrl_probe,
|
|
|
|
.remove = __devexit_p(tegra_pinctrl_remove),
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init tegra_pinctrl_init(void)
|
|
|
|
{
|
|
|
|
return platform_driver_register(&tegra_pinctrl_driver);
|
|
|
|
}
|
|
|
|
arch_initcall(tegra_pinctrl_init);
|
|
|
|
|
|
|
|
static void __exit tegra_pinctrl_exit(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&tegra_pinctrl_driver);
|
|
|
|
}
|
|
|
|
module_exit(tegra_pinctrl_exit);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
|
|
|
|
MODULE_DESCRIPTION("NVIDIA Tegra pinctrl driver");
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_DEVICE_TABLE(of, tegra_pinctrl_of_match);
|