2008-03-05 09:52:39 -07:00
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#include <linux/delay.h>
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2005-04-16 16:20:36 -06:00
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#include <linux/pci.h>
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#include <linux/module.h>
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2006-10-17 23:47:25 -06:00
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#include <linux/sched.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2005-04-16 16:20:36 -06:00
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#include <linux/ioport.h>
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2006-10-19 09:41:28 -06:00
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#include <linux/wait.h>
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2005-04-16 16:20:36 -06:00
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2005-11-05 17:45:08 -07:00
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#include "pci.h"
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2005-04-16 16:20:36 -06:00
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/*
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* This interrupt-safe spinlock protects all accesses to PCI
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* configuration space.
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*/
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2011-11-04 02:46:00 -06:00
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DEFINE_RAW_SPINLOCK(pci_lock);
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2005-04-16 16:20:36 -06:00
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/*
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* Wrappers for all PCI configuration access functions. They just check
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* alignment, do locking and call the low-level functions pointed to
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* by pci_dev->ops.
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*/
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#define PCI_byte_BAD 0
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#define PCI_word_BAD (pos & 1)
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#define PCI_dword_BAD (pos & 3)
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#define PCI_OP_READ(size,type,len) \
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int pci_bus_read_config_##size \
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(struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
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{ \
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int res; \
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unsigned long flags; \
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u32 data = 0; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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2010-02-17 07:35:19 -07:00
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raw_spin_lock_irqsave(&pci_lock, flags); \
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2005-04-16 16:20:36 -06:00
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res = bus->ops->read(bus, devfn, pos, len, &data); \
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*value = (type)data; \
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2010-02-17 07:35:19 -07:00
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raw_spin_unlock_irqrestore(&pci_lock, flags); \
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2005-04-16 16:20:36 -06:00
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return res; \
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}
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#define PCI_OP_WRITE(size,type,len) \
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int pci_bus_write_config_##size \
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(struct pci_bus *bus, unsigned int devfn, int pos, type value) \
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{ \
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int res; \
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unsigned long flags; \
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if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
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2010-02-17 07:35:19 -07:00
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raw_spin_lock_irqsave(&pci_lock, flags); \
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2005-04-16 16:20:36 -06:00
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res = bus->ops->write(bus, devfn, pos, len, value); \
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2010-02-17 07:35:19 -07:00
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raw_spin_unlock_irqrestore(&pci_lock, flags); \
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2005-04-16 16:20:36 -06:00
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return res; \
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}
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PCI_OP_READ(byte, u8, 1)
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PCI_OP_READ(word, u16, 2)
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PCI_OP_READ(dword, u32, 4)
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PCI_OP_WRITE(byte, u8, 1)
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PCI_OP_WRITE(word, u16, 2)
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PCI_OP_WRITE(dword, u32, 4)
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EXPORT_SYMBOL(pci_bus_read_config_byte);
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EXPORT_SYMBOL(pci_bus_read_config_word);
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EXPORT_SYMBOL(pci_bus_read_config_dword);
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EXPORT_SYMBOL(pci_bus_write_config_byte);
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EXPORT_SYMBOL(pci_bus_write_config_word);
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EXPORT_SYMBOL(pci_bus_write_config_dword);
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2005-09-27 02:21:55 -06:00
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2009-04-23 20:45:17 -06:00
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/**
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* pci_bus_set_ops - Set raw operations of pci bus
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* @bus: pci bus struct
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* @ops: new raw operations
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*
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* Return previous raw operations
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*/
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struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
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{
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struct pci_ops *old_ops;
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unsigned long flags;
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2010-02-17 07:35:19 -07:00
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raw_spin_lock_irqsave(&pci_lock, flags);
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2009-04-23 20:45:17 -06:00
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old_ops = bus->ops;
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bus->ops = ops;
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2010-02-17 07:35:19 -07:00
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raw_spin_unlock_irqrestore(&pci_lock, flags);
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2009-04-23 20:45:17 -06:00
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return old_ops;
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}
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EXPORT_SYMBOL(pci_bus_set_ops);
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2008-12-18 10:17:16 -07:00
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/**
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* pci_read_vpd - Read one entry from Vital Product Data
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* @dev: pci device struct
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* @pos: offset in vpd space
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* @count: number of bytes to read
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* @buf: pointer to where to store result
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*
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*/
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ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
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{
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if (!dev->vpd || !dev->vpd->ops)
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return -ENODEV;
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return dev->vpd->ops->read(dev, pos, count, buf);
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}
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EXPORT_SYMBOL(pci_read_vpd);
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/**
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* pci_write_vpd - Write entry to Vital Product Data
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* @dev: pci device struct
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* @pos: offset in vpd space
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2009-04-10 16:17:50 -06:00
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* @count: number of bytes to write
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* @buf: buffer containing write data
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2008-12-18 10:17:16 -07:00
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*
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*/
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ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
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{
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if (!dev->vpd || !dev->vpd->ops)
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return -ENODEV;
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return dev->vpd->ops->write(dev, pos, count, buf);
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}
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EXPORT_SYMBOL(pci_write_vpd);
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2006-10-19 09:41:28 -06:00
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/*
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* The following routines are to prevent the user from accessing PCI config
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* space when it's unsafe to do so. Some devices require this during BIST and
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* we're required to prevent it during D-state transitions.
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*
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* We have a bit per device to indicate it's blocked and a global wait queue
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* for callers to sleep on until devices are unblocked.
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*/
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2011-11-04 02:45:59 -06:00
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static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
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2005-09-27 02:21:55 -06:00
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2011-11-04 02:45:59 -06:00
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static noinline void pci_wait_cfg(struct pci_dev *dev)
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2006-10-19 09:41:28 -06:00
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{
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DECLARE_WAITQUEUE(wait, current);
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2011-11-04 02:45:59 -06:00
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__add_wait_queue(&pci_cfg_wait, &wait);
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2006-10-19 09:41:28 -06:00
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do {
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set_current_state(TASK_UNINTERRUPTIBLE);
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2010-02-17 07:35:19 -07:00
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raw_spin_unlock_irq(&pci_lock);
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2006-10-19 09:41:28 -06:00
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schedule();
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2010-02-17 07:35:19 -07:00
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raw_spin_lock_irq(&pci_lock);
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2011-11-04 02:45:59 -06:00
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} while (dev->block_cfg_access);
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__remove_wait_queue(&pci_cfg_wait, &wait);
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2005-09-27 02:21:55 -06:00
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}
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2011-04-17 09:20:32 -06:00
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/* Returns 0 on success, negative values indicate error. */
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2005-09-27 02:21:55 -06:00
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#define PCI_USER_READ_CONFIG(size,type) \
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int pci_user_read_config_##size \
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(struct pci_dev *dev, int pos, type *val) \
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{ \
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int ret = 0; \
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u32 data = -1; \
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2011-04-17 09:20:32 -06:00
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if (PCI_##size##_BAD) \
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return -EINVAL; \
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2010-02-17 07:35:19 -07:00
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raw_spin_lock_irq(&pci_lock); \
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2011-11-04 02:45:59 -06:00
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if (unlikely(dev->block_cfg_access)) \
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pci_wait_cfg(dev); \
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2006-10-19 09:41:28 -06:00
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ret = dev->bus->ops->read(dev->bus, dev->devfn, \
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2005-09-27 02:21:55 -06:00
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pos, sizeof(type), &data); \
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2010-02-17 07:35:19 -07:00
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raw_spin_unlock_irq(&pci_lock); \
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2005-09-27 02:21:55 -06:00
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*val = (type)data; \
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2011-04-17 09:20:32 -06:00
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if (ret > 0) \
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ret = -EINVAL; \
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2005-09-27 02:21:55 -06:00
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return ret; \
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2012-06-10 23:27:19 -06:00
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} \
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EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
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2005-09-27 02:21:55 -06:00
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2011-04-17 09:20:32 -06:00
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/* Returns 0 on success, negative values indicate error. */
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2005-09-27 02:21:55 -06:00
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#define PCI_USER_WRITE_CONFIG(size,type) \
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int pci_user_write_config_##size \
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(struct pci_dev *dev, int pos, type val) \
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{ \
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int ret = -EIO; \
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2011-04-17 09:20:32 -06:00
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if (PCI_##size##_BAD) \
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return -EINVAL; \
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2010-02-17 07:35:19 -07:00
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raw_spin_lock_irq(&pci_lock); \
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2011-11-04 02:45:59 -06:00
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if (unlikely(dev->block_cfg_access)) \
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pci_wait_cfg(dev); \
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2006-10-19 09:41:28 -06:00
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ret = dev->bus->ops->write(dev->bus, dev->devfn, \
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2005-09-27 02:21:55 -06:00
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pos, sizeof(type), val); \
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2010-02-17 07:35:19 -07:00
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raw_spin_unlock_irq(&pci_lock); \
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2011-04-17 09:20:32 -06:00
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if (ret > 0) \
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ret = -EINVAL; \
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2005-09-27 02:21:55 -06:00
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return ret; \
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2012-06-10 23:27:19 -06:00
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} \
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EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
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2005-09-27 02:21:55 -06:00
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PCI_USER_READ_CONFIG(byte, u8)
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PCI_USER_READ_CONFIG(word, u16)
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PCI_USER_READ_CONFIG(dword, u32)
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PCI_USER_WRITE_CONFIG(byte, u8)
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PCI_USER_WRITE_CONFIG(word, u16)
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PCI_USER_WRITE_CONFIG(dword, u32)
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2008-03-05 09:52:39 -07:00
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/* VPD access through PCI 2.2+ VPD capability */
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#define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1)
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struct pci_vpd_pci22 {
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struct pci_vpd base;
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2008-12-18 10:17:16 -07:00
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struct mutex lock;
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u16 flag;
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2008-03-05 09:52:39 -07:00
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bool busy;
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2008-12-18 10:17:16 -07:00
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u8 cap;
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2008-03-05 09:52:39 -07:00
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};
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2008-12-18 10:17:16 -07:00
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/*
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* Wait for last operation to complete.
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* This code has to spin since there is no other notification from the PCI
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* hardware. Since the VPD is often implemented by serial attachment to an
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* EEPROM, it may take many milliseconds to complete.
|
2011-04-17 09:20:32 -06:00
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*
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* Returns 0 on success, negative values indicate error.
|
2008-12-18 10:17:16 -07:00
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*/
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2008-03-05 09:52:39 -07:00
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static int pci_vpd_pci22_wait(struct pci_dev *dev)
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{
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struct pci_vpd_pci22 *vpd =
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container_of(dev->vpd, struct pci_vpd_pci22, base);
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2008-12-18 10:17:16 -07:00
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unsigned long timeout = jiffies + HZ/20 + 2;
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u16 status;
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2008-03-05 09:52:39 -07:00
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int ret;
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if (!vpd->busy)
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return 0;
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for (;;) {
|
2008-12-18 10:17:16 -07:00
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ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
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2008-03-05 09:52:39 -07:00
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&status);
|
2011-04-17 09:20:32 -06:00
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if (ret < 0)
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2008-03-05 09:52:39 -07:00
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return ret;
|
2008-12-18 10:17:16 -07:00
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if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
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2008-03-05 09:52:39 -07:00
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vpd->busy = false;
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return 0;
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}
|
2008-12-18 10:17:16 -07:00
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2010-05-17 12:25:14 -06:00
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if (time_after(jiffies, timeout)) {
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dev_printk(KERN_DEBUG, &dev->dev,
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|
|
|
"vpd r/w failed. This is likely a firmware "
|
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|
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"bug on this device. Contact the card "
|
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|
|
"vendor for a firmware update.");
|
2008-03-05 09:52:39 -07:00
|
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|
return -ETIMEDOUT;
|
2010-05-17 12:25:14 -06:00
|
|
|
}
|
2008-12-18 10:17:16 -07:00
|
|
|
if (fatal_signal_pending(current))
|
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|
|
return -EINTR;
|
|
|
|
if (!cond_resched())
|
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|
|
udelay(10);
|
2008-03-05 09:52:39 -07:00
|
|
|
}
|
|
|
|
}
|
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|
|
2008-12-18 10:17:16 -07:00
|
|
|
static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count,
|
|
|
|
void *arg)
|
2008-03-05 09:52:39 -07:00
|
|
|
{
|
|
|
|
struct pci_vpd_pci22 *vpd =
|
|
|
|
container_of(dev->vpd, struct pci_vpd_pci22, base);
|
2008-12-18 10:17:16 -07:00
|
|
|
int ret;
|
|
|
|
loff_t end = pos + count;
|
|
|
|
u8 *buf = arg;
|
2008-03-05 09:52:39 -07:00
|
|
|
|
2008-12-18 10:17:16 -07:00
|
|
|
if (pos < 0 || pos > vpd->base.len || end > vpd->base.len)
|
2008-03-05 09:52:39 -07:00
|
|
|
return -EINVAL;
|
|
|
|
|
2008-12-18 10:17:16 -07:00
|
|
|
if (mutex_lock_killable(&vpd->lock))
|
|
|
|
return -EINTR;
|
|
|
|
|
2008-03-05 09:52:39 -07:00
|
|
|
ret = pci_vpd_pci22_wait(dev);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2008-12-18 10:17:16 -07:00
|
|
|
|
2008-12-18 10:17:16 -07:00
|
|
|
while (pos < end) {
|
|
|
|
u32 val;
|
|
|
|
unsigned int i, skip;
|
|
|
|
|
|
|
|
ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
|
|
|
|
pos & ~3);
|
|
|
|
if (ret < 0)
|
|
|
|
break;
|
|
|
|
vpd->busy = true;
|
|
|
|
vpd->flag = PCI_VPD_ADDR_F;
|
|
|
|
ret = pci_vpd_pci22_wait(dev);
|
|
|
|
if (ret < 0)
|
|
|
|
break;
|
|
|
|
|
|
|
|
ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
|
|
|
|
if (ret < 0)
|
|
|
|
break;
|
|
|
|
|
|
|
|
skip = pos & 3;
|
|
|
|
for (i = 0; i < sizeof(u32); i++) {
|
|
|
|
if (i >= skip) {
|
|
|
|
*buf++ = val;
|
|
|
|
if (++pos == end)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
val >>= 8;
|
|
|
|
}
|
|
|
|
}
|
2008-03-05 09:52:39 -07:00
|
|
|
out:
|
2008-12-18 10:17:16 -07:00
|
|
|
mutex_unlock(&vpd->lock);
|
2008-12-18 10:17:16 -07:00
|
|
|
return ret ? ret : count;
|
2008-03-05 09:52:39 -07:00
|
|
|
}
|
|
|
|
|
2008-12-18 10:17:16 -07:00
|
|
|
static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count,
|
|
|
|
const void *arg)
|
2008-03-05 09:52:39 -07:00
|
|
|
{
|
|
|
|
struct pci_vpd_pci22 *vpd =
|
|
|
|
container_of(dev->vpd, struct pci_vpd_pci22, base);
|
2008-12-18 10:17:16 -07:00
|
|
|
const u8 *buf = arg;
|
|
|
|
loff_t end = pos + count;
|
2008-12-18 10:17:16 -07:00
|
|
|
int ret = 0;
|
2008-03-05 09:52:39 -07:00
|
|
|
|
2008-12-18 10:17:16 -07:00
|
|
|
if (pos < 0 || (pos & 3) || (count & 3) || end > vpd->base.len)
|
2008-03-05 09:52:39 -07:00
|
|
|
return -EINVAL;
|
|
|
|
|
2008-12-18 10:17:16 -07:00
|
|
|
if (mutex_lock_killable(&vpd->lock))
|
|
|
|
return -EINTR;
|
2008-12-18 10:17:16 -07:00
|
|
|
|
2008-03-05 09:52:39 -07:00
|
|
|
ret = pci_vpd_pci22_wait(dev);
|
|
|
|
if (ret < 0)
|
|
|
|
goto out;
|
2008-12-18 10:17:16 -07:00
|
|
|
|
|
|
|
while (pos < end) {
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
val = *buf++;
|
|
|
|
val |= *buf++ << 8;
|
|
|
|
val |= *buf++ << 16;
|
|
|
|
val |= *buf++ << 24;
|
|
|
|
|
|
|
|
ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
|
|
|
|
if (ret < 0)
|
|
|
|
break;
|
|
|
|
ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
|
|
|
|
pos | PCI_VPD_ADDR_F);
|
|
|
|
if (ret < 0)
|
|
|
|
break;
|
|
|
|
|
|
|
|
vpd->busy = true;
|
|
|
|
vpd->flag = 0;
|
|
|
|
ret = pci_vpd_pci22_wait(dev);
|
2011-04-17 09:22:21 -06:00
|
|
|
if (ret < 0)
|
|
|
|
break;
|
2008-12-18 10:17:16 -07:00
|
|
|
|
|
|
|
pos += sizeof(u32);
|
|
|
|
}
|
2008-03-05 09:52:39 -07:00
|
|
|
out:
|
2008-12-18 10:17:16 -07:00
|
|
|
mutex_unlock(&vpd->lock);
|
2008-12-18 10:17:16 -07:00
|
|
|
return ret ? ret : count;
|
2008-03-05 09:52:39 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void pci_vpd_pci22_release(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
kfree(container_of(dev->vpd, struct pci_vpd_pci22, base));
|
|
|
|
}
|
|
|
|
|
2008-12-18 10:17:16 -07:00
|
|
|
static const struct pci_vpd_ops pci_vpd_pci22_ops = {
|
2008-03-05 09:52:39 -07:00
|
|
|
.read = pci_vpd_pci22_read,
|
|
|
|
.write = pci_vpd_pci22_write,
|
|
|
|
.release = pci_vpd_pci22_release,
|
|
|
|
};
|
|
|
|
|
|
|
|
int pci_vpd_pci22_init(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
struct pci_vpd_pci22 *vpd;
|
|
|
|
u8 cap;
|
|
|
|
|
|
|
|
cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
|
|
|
|
if (!cap)
|
|
|
|
return -ENODEV;
|
|
|
|
vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
|
|
|
|
if (!vpd)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2008-07-02 11:59:04 -06:00
|
|
|
vpd->base.len = PCI_VPD_PCI22_SIZE;
|
2008-03-05 09:52:39 -07:00
|
|
|
vpd->base.ops = &pci_vpd_pci22_ops;
|
2008-12-18 10:17:16 -07:00
|
|
|
mutex_init(&vpd->lock);
|
2008-03-05 09:52:39 -07:00
|
|
|
vpd->cap = cap;
|
|
|
|
vpd->busy = false;
|
|
|
|
dev->vpd = &vpd->base;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-12-18 10:17:16 -07:00
|
|
|
/**
|
|
|
|
* pci_vpd_truncate - Set available Vital Product Data size
|
|
|
|
* @dev: pci device struct
|
|
|
|
* @size: available memory in bytes
|
|
|
|
*
|
|
|
|
* Adjust size of available VPD area.
|
|
|
|
*/
|
|
|
|
int pci_vpd_truncate(struct pci_dev *dev, size_t size)
|
|
|
|
{
|
|
|
|
if (!dev->vpd)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/* limited by the access method */
|
|
|
|
if (size > dev->vpd->len)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
dev->vpd->len = size;
|
2009-03-31 16:23:41 -06:00
|
|
|
if (dev->vpd->attr)
|
|
|
|
dev->vpd->attr->size = size;
|
2008-12-18 10:17:16 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_vpd_truncate);
|
|
|
|
|
2005-09-27 02:21:55 -06:00
|
|
|
/**
|
2011-11-04 02:45:59 -06:00
|
|
|
* pci_cfg_access_lock - Lock PCI config reads/writes
|
2005-09-27 02:21:55 -06:00
|
|
|
* @dev: pci device struct
|
|
|
|
*
|
2011-11-04 02:45:59 -06:00
|
|
|
* When access is locked, any userspace reads or writes to config
|
|
|
|
* space and concurrent lock requests will sleep until access is
|
|
|
|
* allowed via pci_cfg_access_unlocked again.
|
2006-10-19 09:41:28 -06:00
|
|
|
*/
|
2011-11-04 02:45:59 -06:00
|
|
|
void pci_cfg_access_lock(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
might_sleep();
|
|
|
|
|
|
|
|
raw_spin_lock_irq(&pci_lock);
|
|
|
|
if (dev->block_cfg_access)
|
|
|
|
pci_wait_cfg(dev);
|
|
|
|
dev->block_cfg_access = 1;
|
|
|
|
raw_spin_unlock_irq(&pci_lock);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_cfg_access_trylock - try to lock PCI config reads/writes
|
|
|
|
* @dev: pci device struct
|
|
|
|
*
|
|
|
|
* Same as pci_cfg_access_lock, but will return 0 if access is
|
|
|
|
* already locked, 1 otherwise. This function can be used from
|
|
|
|
* atomic contexts.
|
|
|
|
*/
|
|
|
|
bool pci_cfg_access_trylock(struct pci_dev *dev)
|
2005-09-27 02:21:55 -06:00
|
|
|
{
|
|
|
|
unsigned long flags;
|
2011-11-04 02:45:59 -06:00
|
|
|
bool locked = true;
|
2005-09-27 02:21:55 -06:00
|
|
|
|
2010-02-17 07:35:19 -07:00
|
|
|
raw_spin_lock_irqsave(&pci_lock, flags);
|
2011-11-04 02:45:59 -06:00
|
|
|
if (dev->block_cfg_access)
|
|
|
|
locked = false;
|
|
|
|
else
|
|
|
|
dev->block_cfg_access = 1;
|
2010-02-17 07:35:19 -07:00
|
|
|
raw_spin_unlock_irqrestore(&pci_lock, flags);
|
2006-10-19 09:41:28 -06:00
|
|
|
|
2011-11-04 02:45:59 -06:00
|
|
|
return locked;
|
2005-09-27 02:21:55 -06:00
|
|
|
}
|
2011-11-04 02:45:59 -06:00
|
|
|
EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
|
2005-09-27 02:21:55 -06:00
|
|
|
|
|
|
|
/**
|
2011-11-04 02:45:59 -06:00
|
|
|
* pci_cfg_access_unlock - Unlock PCI config reads/writes
|
2005-09-27 02:21:55 -06:00
|
|
|
* @dev: pci device struct
|
|
|
|
*
|
2011-11-04 02:45:59 -06:00
|
|
|
* This function allows PCI config accesses to resume.
|
2006-10-19 09:41:28 -06:00
|
|
|
*/
|
2011-11-04 02:45:59 -06:00
|
|
|
void pci_cfg_access_unlock(struct pci_dev *dev)
|
2005-09-27 02:21:55 -06:00
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
2010-02-17 07:35:19 -07:00
|
|
|
raw_spin_lock_irqsave(&pci_lock, flags);
|
2006-10-19 09:41:28 -06:00
|
|
|
|
|
|
|
/* This indicates a problem in the caller, but we don't need
|
|
|
|
* to kill them, unlike a double-block above. */
|
2011-11-04 02:45:59 -06:00
|
|
|
WARN_ON(!dev->block_cfg_access);
|
2006-10-19 09:41:28 -06:00
|
|
|
|
2011-11-04 02:45:59 -06:00
|
|
|
dev->block_cfg_access = 0;
|
|
|
|
wake_up_all(&pci_cfg_wait);
|
2010-02-17 07:35:19 -07:00
|
|
|
raw_spin_unlock_irqrestore(&pci_lock, flags);
|
2005-09-27 02:21:55 -06:00
|
|
|
}
|
2011-11-04 02:45:59 -06:00
|
|
|
EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
|
PCI: Add accessors for PCI Express Capability
The PCI Express Capability (PCIe spec r3.0, sec 7.8) comes in two
versions, v1 and v2. In v1 Capability structures (PCIe spec r1.0 and
r1.1), some fields are optional, so the structure size depends on the
device type.
This patch adds functions to access this capability so drivers don't
have to be aware of the differences between v1 and v2. Note that these
new functions apply only to the "PCI Express Capability," not to any of
the other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
Function pcie_capability_read_word/dword() reads the PCIe Capabilities
register and returns the value in the reference parameter "val". If
the PCIe Capabilities register is not implemented on the PCIe device,
"val" is set to 0.
Function pcie_capability_write_word/dword() writes the value to the
specified PCIe Capability register.
Function pcie_capability_clear_and_set_word/dword() sets and/or clears bits
of a PCIe Capability register.
[bhelgaas: changelog, drop "pci_" prefixes, don't export
pcie_capability_reg_implemented()]
Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-07-24 03:20:05 -06:00
|
|
|
|
|
|
|
static inline int pcie_cap_version(const struct pci_dev *dev)
|
|
|
|
{
|
2013-01-25 17:55:45 -07:00
|
|
|
return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
|
PCI: Add accessors for PCI Express Capability
The PCI Express Capability (PCIe spec r3.0, sec 7.8) comes in two
versions, v1 and v2. In v1 Capability structures (PCIe spec r1.0 and
r1.1), some fields are optional, so the structure size depends on the
device type.
This patch adds functions to access this capability so drivers don't
have to be aware of the differences between v1 and v2. Note that these
new functions apply only to the "PCI Express Capability," not to any of
the other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
Function pcie_capability_read_word/dword() reads the PCIe Capabilities
register and returns the value in the reference parameter "val". If
the PCIe Capabilities register is not implemented on the PCIe device,
"val" is set to 0.
Function pcie_capability_write_word/dword() writes the value to the
specified PCIe Capability register.
Function pcie_capability_clear_and_set_word/dword() sets and/or clears bits
of a PCIe Capability register.
[bhelgaas: changelog, drop "pci_" prefixes, don't export
pcie_capability_reg_implemented()]
Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-07-24 03:20:05 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int type = pci_pcie_type(dev);
|
|
|
|
|
|
|
|
return pcie_cap_version(dev) > 1 ||
|
|
|
|
type == PCI_EXP_TYPE_ROOT_PORT ||
|
|
|
|
type == PCI_EXP_TYPE_ENDPOINT ||
|
|
|
|
type == PCI_EXP_TYPE_LEG_END;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int type = pci_pcie_type(dev);
|
|
|
|
|
|
|
|
return pcie_cap_version(dev) > 1 ||
|
|
|
|
type == PCI_EXP_TYPE_ROOT_PORT ||
|
|
|
|
(type == PCI_EXP_TYPE_DOWNSTREAM &&
|
2013-01-25 17:55:45 -07:00
|
|
|
pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT);
|
PCI: Add accessors for PCI Express Capability
The PCI Express Capability (PCIe spec r3.0, sec 7.8) comes in two
versions, v1 and v2. In v1 Capability structures (PCIe spec r1.0 and
r1.1), some fields are optional, so the structure size depends on the
device type.
This patch adds functions to access this capability so drivers don't
have to be aware of the differences between v1 and v2. Note that these
new functions apply only to the "PCI Express Capability," not to any of
the other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
Function pcie_capability_read_word/dword() reads the PCIe Capabilities
register and returns the value in the reference parameter "val". If
the PCIe Capabilities register is not implemented on the PCIe device,
"val" is set to 0.
Function pcie_capability_write_word/dword() writes the value to the
specified PCIe Capability register.
Function pcie_capability_clear_and_set_word/dword() sets and/or clears bits
of a PCIe Capability register.
[bhelgaas: changelog, drop "pci_" prefixes, don't export
pcie_capability_reg_implemented()]
Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-07-24 03:20:05 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
int type = pci_pcie_type(dev);
|
|
|
|
|
|
|
|
return pcie_cap_version(dev) > 1 ||
|
|
|
|
type == PCI_EXP_TYPE_ROOT_PORT ||
|
|
|
|
type == PCI_EXP_TYPE_RC_EC;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
|
|
|
|
{
|
|
|
|
if (!pci_is_pcie(dev))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
switch (pos) {
|
2013-02-14 11:35:42 -07:00
|
|
|
case PCI_EXP_FLAGS:
|
PCI: Add accessors for PCI Express Capability
The PCI Express Capability (PCIe spec r3.0, sec 7.8) comes in two
versions, v1 and v2. In v1 Capability structures (PCIe spec r1.0 and
r1.1), some fields are optional, so the structure size depends on the
device type.
This patch adds functions to access this capability so drivers don't
have to be aware of the differences between v1 and v2. Note that these
new functions apply only to the "PCI Express Capability," not to any of
the other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
Function pcie_capability_read_word/dword() reads the PCIe Capabilities
register and returns the value in the reference parameter "val". If
the PCIe Capabilities register is not implemented on the PCIe device,
"val" is set to 0.
Function pcie_capability_write_word/dword() writes the value to the
specified PCIe Capability register.
Function pcie_capability_clear_and_set_word/dword() sets and/or clears bits
of a PCIe Capability register.
[bhelgaas: changelog, drop "pci_" prefixes, don't export
pcie_capability_reg_implemented()]
Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-07-24 03:20:05 -06:00
|
|
|
return true;
|
|
|
|
case PCI_EXP_DEVCAP:
|
|
|
|
case PCI_EXP_DEVCTL:
|
|
|
|
case PCI_EXP_DEVSTA:
|
|
|
|
return pcie_cap_has_devctl(dev);
|
|
|
|
case PCI_EXP_LNKCAP:
|
|
|
|
case PCI_EXP_LNKCTL:
|
|
|
|
case PCI_EXP_LNKSTA:
|
|
|
|
return pcie_cap_has_lnkctl(dev);
|
|
|
|
case PCI_EXP_SLTCAP:
|
|
|
|
case PCI_EXP_SLTCTL:
|
|
|
|
case PCI_EXP_SLTSTA:
|
|
|
|
return pcie_cap_has_sltctl(dev);
|
|
|
|
case PCI_EXP_RTCTL:
|
|
|
|
case PCI_EXP_RTCAP:
|
|
|
|
case PCI_EXP_RTSTA:
|
|
|
|
return pcie_cap_has_rtctl(dev);
|
|
|
|
case PCI_EXP_DEVCAP2:
|
|
|
|
case PCI_EXP_DEVCTL2:
|
|
|
|
case PCI_EXP_LNKCAP2:
|
|
|
|
case PCI_EXP_LNKCTL2:
|
|
|
|
case PCI_EXP_LNKSTA2:
|
|
|
|
return pcie_cap_version(dev) > 1;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Note that these accessor functions are only for the "PCI Express
|
|
|
|
* Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
|
|
|
|
* other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
|
|
|
|
*/
|
|
|
|
int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
*val = 0;
|
|
|
|
if (pos & 1)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (pcie_capability_reg_implemented(dev, pos)) {
|
|
|
|
ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
|
|
|
|
/*
|
|
|
|
* Reset *val to 0 if pci_read_config_word() fails, it may
|
|
|
|
* have been written as 0xFFFF if hardware error happens
|
|
|
|
* during pci_read_config_word().
|
|
|
|
*/
|
|
|
|
if (ret)
|
|
|
|
*val = 0;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* For Functions that do not implement the Slot Capabilities,
|
|
|
|
* Slot Status, and Slot Control registers, these spaces must
|
|
|
|
* be hardwired to 0b, with the exception of the Presence Detect
|
|
|
|
* State bit in the Slot Status register of Downstream Ports,
|
|
|
|
* which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
|
|
|
|
*/
|
|
|
|
if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&
|
|
|
|
pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
|
|
|
|
*val = PCI_EXP_SLTSTA_PDS;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pcie_capability_read_word);
|
|
|
|
|
|
|
|
int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
*val = 0;
|
|
|
|
if (pos & 3)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (pcie_capability_reg_implemented(dev, pos)) {
|
|
|
|
ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
|
|
|
|
/*
|
|
|
|
* Reset *val to 0 if pci_read_config_dword() fails, it may
|
|
|
|
* have been written as 0xFFFFFFFF if hardware error happens
|
|
|
|
* during pci_read_config_dword().
|
|
|
|
*/
|
|
|
|
if (ret)
|
|
|
|
*val = 0;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL &&
|
|
|
|
pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
|
|
|
|
*val = PCI_EXP_SLTSTA_PDS;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pcie_capability_read_dword);
|
|
|
|
|
|
|
|
int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
|
|
|
|
{
|
|
|
|
if (pos & 1)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (!pcie_capability_reg_implemented(dev, pos))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pcie_capability_write_word);
|
|
|
|
|
|
|
|
int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
|
|
|
|
{
|
|
|
|
if (pos & 3)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (!pcie_capability_reg_implemented(dev, pos))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pcie_capability_write_dword);
|
|
|
|
|
|
|
|
int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
|
|
|
|
u16 clear, u16 set)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
u16 val;
|
|
|
|
|
|
|
|
ret = pcie_capability_read_word(dev, pos, &val);
|
|
|
|
if (!ret) {
|
|
|
|
val &= ~clear;
|
|
|
|
val |= set;
|
|
|
|
ret = pcie_capability_write_word(dev, pos, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
|
|
|
|
|
|
|
|
int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
|
|
|
|
u32 clear, u32 set)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
ret = pcie_capability_read_dword(dev, pos, &val);
|
|
|
|
if (!ret) {
|
|
|
|
val &= ~clear;
|
|
|
|
val |= set;
|
|
|
|
ret = pcie_capability_write_dword(dev, pos, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
|