2009-06-22 07:36:29 -06:00
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/*
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2009-11-06 05:52:22 -07:00
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* Synopsys DesignWare I2C adapter driver (master only).
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2009-06-22 07:36:29 -06:00
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*
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* Based on the TI DAVINCI I2C adapter driver.
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*
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* Copyright (C) 2006 Texas Instruments.
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* Copyright (C) 2007 MontaVista Software Inc.
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* Copyright (C) 2009 Provigent Ltd.
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*
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* ----------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* ----------------------------------------------------------------------------
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*
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*/
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#include <linux/clk.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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2011-10-29 03:57:23 -06:00
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#include <linux/i2c.h>
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2009-06-22 07:36:29 -06:00
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#include <linux/interrupt.h>
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#include <linux/io.h>
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2011-10-29 03:57:23 -06:00
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#include <linux/delay.h>
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#include "i2c-designware-core.h"
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2009-11-06 05:51:57 -07:00
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2009-06-22 07:36:29 -06:00
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static char *abort_sources[] = {
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2009-11-06 05:52:22 -07:00
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[ABRT_7B_ADDR_NOACK] =
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2009-06-22 07:36:29 -06:00
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"slave address not acknowledged (7bit mode)",
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2009-11-06 05:52:22 -07:00
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[ABRT_10ADDR1_NOACK] =
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2009-06-22 07:36:29 -06:00
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"first address byte not acknowledged (10bit mode)",
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2009-11-06 05:52:22 -07:00
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[ABRT_10ADDR2_NOACK] =
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2009-06-22 07:36:29 -06:00
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"second address byte not acknowledged (10bit mode)",
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2009-11-06 05:52:22 -07:00
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[ABRT_TXDATA_NOACK] =
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2009-06-22 07:36:29 -06:00
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"data not acknowledged",
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2009-11-06 05:52:22 -07:00
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[ABRT_GCALL_NOACK] =
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2009-06-22 07:36:29 -06:00
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"no acknowledgement for a general call",
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2009-11-06 05:52:22 -07:00
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[ABRT_GCALL_READ] =
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2009-06-22 07:36:29 -06:00
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"read after general call",
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2009-11-06 05:52:22 -07:00
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[ABRT_SBYTE_ACKDET] =
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2009-06-22 07:36:29 -06:00
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"start byte acknowledged",
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2009-11-06 05:52:22 -07:00
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[ABRT_SBYTE_NORSTRT] =
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2009-06-22 07:36:29 -06:00
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"trying to send start byte when restart is disabled",
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2009-11-06 05:52:22 -07:00
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[ABRT_10B_RD_NORSTRT] =
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2009-06-22 07:36:29 -06:00
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"trying to read when restart is disabled (10bit mode)",
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2009-11-06 05:52:22 -07:00
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[ABRT_MASTER_DIS] =
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2009-06-22 07:36:29 -06:00
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"trying to use disabled adapter",
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2009-11-06 05:52:22 -07:00
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[ARB_LOST] =
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2009-06-22 07:36:29 -06:00
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"lost arbitration",
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};
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2011-10-29 03:57:23 -06:00
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u32 dw_readl(struct dw_i2c_dev *dev, int offset)
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2011-10-06 12:26:25 -06:00
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{
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2011-10-06 12:26:27 -06:00
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u32 value = readl(dev->base + offset);
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if (dev->swab)
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return swab32(value);
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else
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return value;
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2011-10-06 12:26:25 -06:00
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}
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2011-10-29 03:57:23 -06:00
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void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
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2011-10-06 12:26:25 -06:00
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{
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2011-10-06 12:26:27 -06:00
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if (dev->swab)
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b = swab32(b);
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2011-10-06 12:26:25 -06:00
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writel(b, dev->base + offset);
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}
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i2c-designware: Improved _HCNT/_LCNT calculation
* Calculate with accurate conditional expressions from DW manuals.
* Round ic_clk by adding 0.5 as it's important at high ic_clk rate.
* Take into account "tHD;STA" issue for _HCNT calculation.
* Take into account "tf" for _LCNT calculation.
* Add "cond" and "offset" fot further correction requirements.
For _HCNT calculation, there's one issue needs to be carefully
considered; DesignWare I2C core doesn't seem to have solid strategy
to meet the tHD;STA timing spec. If you configure _HCNT based on the
tHIGH timing spec, it easily results in violation of the tHD;STA spec.
After many trials, we came to the conclusion that the tHD;STA period
is proportional to (_HCNT + 3). For the safety's sake, this should be
selected by default.
As for _LCNT calculation, DW I2C core has one characteristic behavior;
he starts counting the SCL CNTs for the LOW period of the SCL clock
(tLOW) as soon as it pulls the SCL line. At that time, he doesn't take
into account the fall time of SCL signal (tf), IOW, he starts counting
CNTs without confirming the SCL input voltage has dropped to below VIL.
This characteristics becomes a problem on some platforms where tf is
considerably long, and results in violation of the tLOW timing spec.
To make the driver configurable as much as possible for various cases,
we'd have separated arguments "tf" and "offset", and for safety default
values should be 0.3 us and 0, respectively.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-11-06 05:47:01 -07:00
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static u32
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i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
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{
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/*
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* DesignWare I2C core doesn't seem to have solid strategy to meet
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* the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
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* will result in violation of the tHD;STA spec.
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*/
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if (cond)
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/*
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* Conditional expression:
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*
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* IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
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*
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* This is based on the DW manuals, and represents an ideal
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* configuration. The resulting I2C bus speed will be
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* faster than any of the others.
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*
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* If your hardware is free from tHD;STA issue, try this one.
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*/
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return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset;
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else
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/*
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* Conditional expression:
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*
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* IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
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*
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* This is just experimental rule; the tHD;STA period turned
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* out to be proportinal to (_HCNT + 3). With this setting,
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* we could meet both tHIGH and tHD;STA timing specs.
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*
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* If unsure, you'd better to take this alternative.
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*
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* The reason why we need to take into account "tf" here,
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* is the same as described in i2c_dw_scl_lcnt().
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*/
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return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset;
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}
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static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
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{
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/*
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* Conditional expression:
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*
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* IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
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*
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* DW I2C core starts counting the SCL CNTs for the LOW period
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* of the SCL clock (tLOW) as soon as it pulls the SCL line.
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* In order to meet the tLOW timing spec, we need to take into
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* account the fall time of SCL signal (tf). Default tf value
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* should be 0.3 us, for safety.
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*/
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return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset;
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}
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2009-06-22 07:36:29 -06:00
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/**
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* i2c_dw_init() - initialize the designware i2c master hardware
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* @dev: device private data
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*
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* This functions configures and enables the I2C master.
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* This function is called during I2C init function, and in case of timeout at
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* run time.
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*/
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2011-10-29 03:57:23 -06:00
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int i2c_dw_init(struct dw_i2c_dev *dev)
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2009-06-22 07:36:29 -06:00
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{
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2011-10-06 12:26:30 -06:00
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u32 input_clock_khz;
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2011-10-06 12:26:32 -06:00
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u32 hcnt, lcnt;
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2011-10-06 12:26:28 -06:00
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u32 reg;
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2011-10-06 12:26:30 -06:00
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input_clock_khz = dev->get_clk_rate_khz(dev);
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2011-10-06 12:26:28 -06:00
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/* Configure register endianess access */
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reg = dw_readl(dev, DW_IC_COMP_TYPE);
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if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
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dev->swab = 1;
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reg = DW_IC_COMP_TYPE_VALUE;
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}
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if (reg != DW_IC_COMP_TYPE_VALUE) {
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dev_err(dev->dev, "Unknown Synopsys component type: "
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"0x%08x\n", reg);
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return -ENODEV;
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}
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2009-06-22 07:36:29 -06:00
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/* Disable the adapter */
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2011-10-06 12:26:25 -06:00
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dw_writel(dev, 0, DW_IC_ENABLE);
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2009-06-22 07:36:29 -06:00
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/* set standard and fast speed deviders for high/low periods */
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i2c-designware: Improved _HCNT/_LCNT calculation
* Calculate with accurate conditional expressions from DW manuals.
* Round ic_clk by adding 0.5 as it's important at high ic_clk rate.
* Take into account "tHD;STA" issue for _HCNT calculation.
* Take into account "tf" for _LCNT calculation.
* Add "cond" and "offset" fot further correction requirements.
For _HCNT calculation, there's one issue needs to be carefully
considered; DesignWare I2C core doesn't seem to have solid strategy
to meet the tHD;STA timing spec. If you configure _HCNT based on the
tHIGH timing spec, it easily results in violation of the tHD;STA spec.
After many trials, we came to the conclusion that the tHD;STA period
is proportional to (_HCNT + 3). For the safety's sake, this should be
selected by default.
As for _LCNT calculation, DW I2C core has one characteristic behavior;
he starts counting the SCL CNTs for the LOW period of the SCL clock
(tLOW) as soon as it pulls the SCL line. At that time, he doesn't take
into account the fall time of SCL signal (tf), IOW, he starts counting
CNTs without confirming the SCL input voltage has dropped to below VIL.
This characteristics becomes a problem on some platforms where tf is
considerably long, and results in violation of the tLOW timing spec.
To make the driver configurable as much as possible for various cases,
we'd have separated arguments "tf" and "offset", and for safety default
values should be 0.3 us and 0, respectively.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-11-06 05:47:01 -07:00
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/* Standard-mode */
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hcnt = i2c_dw_scl_hcnt(input_clock_khz,
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40, /* tHD;STA = tHIGH = 4.0 us */
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3, /* tf = 0.3 us */
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0, /* 0: DW default, 1: Ideal */
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0); /* No offset */
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lcnt = i2c_dw_scl_lcnt(input_clock_khz,
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47, /* tLOW = 4.7 us */
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3, /* tf = 0.3 us */
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0); /* No offset */
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2011-10-06 12:26:25 -06:00
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dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
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dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
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i2c-designware: Improved _HCNT/_LCNT calculation
* Calculate with accurate conditional expressions from DW manuals.
* Round ic_clk by adding 0.5 as it's important at high ic_clk rate.
* Take into account "tHD;STA" issue for _HCNT calculation.
* Take into account "tf" for _LCNT calculation.
* Add "cond" and "offset" fot further correction requirements.
For _HCNT calculation, there's one issue needs to be carefully
considered; DesignWare I2C core doesn't seem to have solid strategy
to meet the tHD;STA timing spec. If you configure _HCNT based on the
tHIGH timing spec, it easily results in violation of the tHD;STA spec.
After many trials, we came to the conclusion that the tHD;STA period
is proportional to (_HCNT + 3). For the safety's sake, this should be
selected by default.
As for _LCNT calculation, DW I2C core has one characteristic behavior;
he starts counting the SCL CNTs for the LOW period of the SCL clock
(tLOW) as soon as it pulls the SCL line. At that time, he doesn't take
into account the fall time of SCL signal (tf), IOW, he starts counting
CNTs without confirming the SCL input voltage has dropped to below VIL.
This characteristics becomes a problem on some platforms where tf is
considerably long, and results in violation of the tLOW timing spec.
To make the driver configurable as much as possible for various cases,
we'd have separated arguments "tf" and "offset", and for safety default
values should be 0.3 us and 0, respectively.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-11-06 05:47:01 -07:00
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dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
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/* Fast-mode */
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hcnt = i2c_dw_scl_hcnt(input_clock_khz,
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6, /* tHD;STA = tHIGH = 0.6 us */
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3, /* tf = 0.3 us */
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0, /* 0: DW default, 1: Ideal */
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0); /* No offset */
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lcnt = i2c_dw_scl_lcnt(input_clock_khz,
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13, /* tLOW = 1.3 us */
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3, /* tf = 0.3 us */
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0); /* No offset */
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2011-10-06 12:26:25 -06:00
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dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
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dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
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i2c-designware: Improved _HCNT/_LCNT calculation
* Calculate with accurate conditional expressions from DW manuals.
* Round ic_clk by adding 0.5 as it's important at high ic_clk rate.
* Take into account "tHD;STA" issue for _HCNT calculation.
* Take into account "tf" for _LCNT calculation.
* Add "cond" and "offset" fot further correction requirements.
For _HCNT calculation, there's one issue needs to be carefully
considered; DesignWare I2C core doesn't seem to have solid strategy
to meet the tHD;STA timing spec. If you configure _HCNT based on the
tHIGH timing spec, it easily results in violation of the tHD;STA spec.
After many trials, we came to the conclusion that the tHD;STA period
is proportional to (_HCNT + 3). For the safety's sake, this should be
selected by default.
As for _LCNT calculation, DW I2C core has one characteristic behavior;
he starts counting the SCL CNTs for the LOW period of the SCL clock
(tLOW) as soon as it pulls the SCL line. At that time, he doesn't take
into account the fall time of SCL signal (tf), IOW, he starts counting
CNTs without confirming the SCL input voltage has dropped to below VIL.
This characteristics becomes a problem on some platforms where tf is
considerably long, and results in violation of the tLOW timing spec.
To make the driver configurable as much as possible for various cases,
we'd have separated arguments "tf" and "offset", and for safety default
values should be 0.3 us and 0, respectively.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-11-06 05:47:01 -07:00
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dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
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2009-06-22 07:36:29 -06:00
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2009-11-06 05:48:12 -07:00
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/* Configure Tx/Rx FIFO threshold levels */
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2011-10-06 12:26:25 -06:00
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dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL);
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dw_writel(dev, 0, DW_IC_RX_TL);
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2009-11-06 05:48:12 -07:00
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2009-06-22 07:36:29 -06:00
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/* configure the i2c master */
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2011-10-06 12:26:32 -06:00
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dw_writel(dev, dev->master_cfg , DW_IC_CON);
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2011-10-06 12:26:28 -06:00
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return 0;
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2009-06-22 07:36:29 -06:00
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}
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/*
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* Waiting for bus not busy
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*/
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static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
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{
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int timeout = TIMEOUT;
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2011-10-06 12:26:25 -06:00
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while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
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2009-06-22 07:36:29 -06:00
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if (timeout <= 0) {
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dev_warn(dev->dev, "timeout waiting for bus ready\n");
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return -ETIMEDOUT;
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}
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timeout--;
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mdelay(1);
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}
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return 0;
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}
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2009-11-06 05:48:55 -07:00
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static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
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{
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|
struct i2c_msg *msgs = dev->msgs;
|
|
|
|
u32 ic_con;
|
|
|
|
|
|
|
|
/* Disable the adapter */
|
2011-10-06 12:26:25 -06:00
|
|
|
dw_writel(dev, 0, DW_IC_ENABLE);
|
2009-11-06 05:48:55 -07:00
|
|
|
|
|
|
|
/* set the slave (target) address */
|
2011-10-06 12:26:25 -06:00
|
|
|
dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR);
|
2009-11-06 05:48:55 -07:00
|
|
|
|
|
|
|
/* if the slave address is ten bit address, enable 10BITADDR */
|
2011-10-06 12:26:25 -06:00
|
|
|
ic_con = dw_readl(dev, DW_IC_CON);
|
2009-11-06 05:48:55 -07:00
|
|
|
if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
|
|
|
|
ic_con |= DW_IC_CON_10BITADDR_MASTER;
|
|
|
|
else
|
|
|
|
ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
|
2011-10-06 12:26:25 -06:00
|
|
|
dw_writel(dev, ic_con, DW_IC_CON);
|
2009-11-06 05:48:55 -07:00
|
|
|
|
|
|
|
/* Enable the adapter */
|
2011-10-06 12:26:25 -06:00
|
|
|
dw_writel(dev, 1, DW_IC_ENABLE);
|
2009-11-06 05:50:40 -07:00
|
|
|
|
|
|
|
/* Enable interrupts */
|
2011-10-06 12:26:25 -06:00
|
|
|
dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
|
2009-11-06 05:48:55 -07:00
|
|
|
}
|
|
|
|
|
2009-06-22 07:36:29 -06:00
|
|
|
/*
|
2009-11-06 05:50:40 -07:00
|
|
|
* Initiate (and continue) low level master read/write transaction.
|
|
|
|
* This function is only called from i2c_dw_isr, and pumping i2c_msg
|
|
|
|
* messages into the tx buffer. Even if the size of i2c_msg data is
|
|
|
|
* longer than the size of the tx buffer, it handles everything.
|
2009-06-22 07:36:29 -06:00
|
|
|
*/
|
2011-10-29 03:57:23 -06:00
|
|
|
void
|
2009-11-06 05:46:04 -07:00
|
|
|
i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
|
2009-06-22 07:36:29 -06:00
|
|
|
{
|
|
|
|
struct i2c_msg *msgs = dev->msgs;
|
2009-11-06 05:48:55 -07:00
|
|
|
u32 intr_mask;
|
2009-11-06 05:49:39 -07:00
|
|
|
int tx_limit, rx_limit;
|
2009-11-06 05:43:52 -07:00
|
|
|
u32 addr = msgs[dev->msg_write_idx].addr;
|
|
|
|
u32 buf_len = dev->tx_buf_len;
|
2011-07-27 00:06:29 -06:00
|
|
|
u8 *buf = dev->tx_buf;
|
2009-06-22 07:36:29 -06:00
|
|
|
|
2009-11-06 05:50:40 -07:00
|
|
|
intr_mask = DW_IC_INTR_DEFAULT_MASK;
|
2009-11-06 05:47:30 -07:00
|
|
|
|
2009-11-06 05:46:29 -07:00
|
|
|
for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
|
2009-11-06 05:52:22 -07:00
|
|
|
/*
|
|
|
|
* if target address has changed, we need to
|
2009-06-22 07:36:29 -06:00
|
|
|
* reprogram the target address in the i2c
|
|
|
|
* adapter when we are done with this transfer
|
|
|
|
*/
|
2009-11-06 05:51:18 -07:00
|
|
|
if (msgs[dev->msg_write_idx].addr != addr) {
|
|
|
|
dev_err(dev->dev,
|
|
|
|
"%s: invalid target address\n", __func__);
|
|
|
|
dev->msg_err = -EINVAL;
|
|
|
|
break;
|
|
|
|
}
|
2009-06-22 07:36:29 -06:00
|
|
|
|
|
|
|
if (msgs[dev->msg_write_idx].len == 0) {
|
|
|
|
dev_err(dev->dev,
|
|
|
|
"%s: invalid message length\n", __func__);
|
|
|
|
dev->msg_err = -EINVAL;
|
2009-11-06 05:51:18 -07:00
|
|
|
break;
|
2009-06-22 07:36:29 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
|
|
|
|
/* new i2c_msg */
|
2009-11-06 05:49:14 -07:00
|
|
|
buf = msgs[dev->msg_write_idx].buf;
|
2009-06-22 07:36:29 -06:00
|
|
|
buf_len = msgs[dev->msg_write_idx].len;
|
|
|
|
}
|
|
|
|
|
2011-10-06 12:26:25 -06:00
|
|
|
tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
|
|
|
|
rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
|
2009-11-06 05:49:39 -07:00
|
|
|
|
2009-06-22 07:36:29 -06:00
|
|
|
while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
|
|
|
|
if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
|
2011-10-06 12:26:25 -06:00
|
|
|
dw_writel(dev, 0x100, DW_IC_DATA_CMD);
|
2009-06-22 07:36:29 -06:00
|
|
|
rx_limit--;
|
|
|
|
} else
|
2011-10-06 12:26:25 -06:00
|
|
|
dw_writel(dev, *buf++, DW_IC_DATA_CMD);
|
2009-06-22 07:36:29 -06:00
|
|
|
tx_limit--; buf_len--;
|
|
|
|
}
|
2009-11-06 05:47:30 -07:00
|
|
|
|
2009-11-06 05:49:14 -07:00
|
|
|
dev->tx_buf = buf;
|
2009-11-06 05:47:30 -07:00
|
|
|
dev->tx_buf_len = buf_len;
|
|
|
|
|
|
|
|
if (buf_len > 0) {
|
|
|
|
/* more bytes to be written */
|
|
|
|
dev->status |= STATUS_WRITE_IN_PROGRESS;
|
|
|
|
break;
|
2009-11-06 05:51:00 -07:00
|
|
|
} else
|
2009-11-06 05:47:30 -07:00
|
|
|
dev->status &= ~STATUS_WRITE_IN_PROGRESS;
|
2009-06-22 07:36:29 -06:00
|
|
|
}
|
|
|
|
|
2009-11-06 05:51:00 -07:00
|
|
|
/*
|
|
|
|
* If i2c_msg index search is completed, we don't need TX_EMPTY
|
|
|
|
* interrupt any more.
|
|
|
|
*/
|
|
|
|
if (dev->msg_write_idx == dev->msgs_num)
|
|
|
|
intr_mask &= ~DW_IC_INTR_TX_EMPTY;
|
|
|
|
|
2009-11-06 05:51:18 -07:00
|
|
|
if (dev->msg_err)
|
|
|
|
intr_mask = 0;
|
|
|
|
|
2011-10-29 03:57:23 -06:00
|
|
|
dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
|
2009-06-22 07:36:29 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2009-11-06 05:45:39 -07:00
|
|
|
i2c_dw_read(struct dw_i2c_dev *dev)
|
2009-06-22 07:36:29 -06:00
|
|
|
{
|
|
|
|
struct i2c_msg *msgs = dev->msgs;
|
2009-11-06 05:49:39 -07:00
|
|
|
int rx_valid;
|
2009-06-22 07:36:29 -06:00
|
|
|
|
2009-11-06 05:46:29 -07:00
|
|
|
for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
|
2009-11-06 05:43:52 -07:00
|
|
|
u32 len;
|
2009-06-22 07:36:29 -06:00
|
|
|
u8 *buf;
|
|
|
|
|
|
|
|
if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
|
|
|
|
len = msgs[dev->msg_read_idx].len;
|
|
|
|
buf = msgs[dev->msg_read_idx].buf;
|
|
|
|
} else {
|
|
|
|
len = dev->rx_buf_len;
|
|
|
|
buf = dev->rx_buf;
|
|
|
|
}
|
|
|
|
|
2011-10-06 12:26:25 -06:00
|
|
|
rx_valid = dw_readl(dev, DW_IC_RXFLR);
|
2009-11-06 05:49:39 -07:00
|
|
|
|
2009-06-22 07:36:29 -06:00
|
|
|
for (; len > 0 && rx_valid > 0; len--, rx_valid--)
|
2011-10-06 12:26:25 -06:00
|
|
|
*buf++ = dw_readl(dev, DW_IC_DATA_CMD);
|
2009-06-22 07:36:29 -06:00
|
|
|
|
|
|
|
if (len > 0) {
|
|
|
|
dev->status |= STATUS_READ_IN_PROGRESS;
|
|
|
|
dev->rx_buf_len = len;
|
|
|
|
dev->rx_buf = buf;
|
|
|
|
return;
|
|
|
|
} else
|
|
|
|
dev->status &= ~STATUS_READ_IN_PROGRESS;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-11-06 05:51:57 -07:00
|
|
|
static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
|
|
|
|
{
|
|
|
|
unsigned long abort_source = dev->abort_source;
|
|
|
|
int i;
|
|
|
|
|
2009-11-16 04:40:14 -07:00
|
|
|
if (abort_source & DW_IC_TX_ABRT_NOACK) {
|
2010-03-05 14:41:37 -07:00
|
|
|
for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
|
2009-11-16 04:40:14 -07:00
|
|
|
dev_dbg(dev->dev,
|
|
|
|
"%s: %s\n", __func__, abort_sources[i]);
|
|
|
|
return -EREMOTEIO;
|
|
|
|
}
|
|
|
|
|
2010-03-05 14:41:37 -07:00
|
|
|
for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
|
2009-11-06 05:51:57 -07:00
|
|
|
dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
|
|
|
|
|
|
|
|
if (abort_source & DW_IC_TX_ARB_LOST)
|
|
|
|
return -EAGAIN;
|
|
|
|
else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
|
|
|
|
return -EINVAL; /* wrong msgs[] data */
|
|
|
|
else
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
2009-06-22 07:36:29 -06:00
|
|
|
/*
|
|
|
|
* Prepare controller for a transaction and call i2c_dw_xfer_msg
|
|
|
|
*/
|
2011-10-29 03:57:23 -06:00
|
|
|
int
|
2009-06-22 07:36:29 -06:00
|
|
|
i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
|
|
|
|
{
|
|
|
|
struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
|
|
|
|
|
|
|
|
mutex_lock(&dev->lock);
|
|
|
|
|
|
|
|
INIT_COMPLETION(dev->cmd_complete);
|
|
|
|
dev->msgs = msgs;
|
|
|
|
dev->msgs_num = num;
|
|
|
|
dev->cmd_err = 0;
|
|
|
|
dev->msg_write_idx = 0;
|
|
|
|
dev->msg_read_idx = 0;
|
|
|
|
dev->msg_err = 0;
|
|
|
|
dev->status = STATUS_IDLE;
|
2009-11-06 05:51:57 -07:00
|
|
|
dev->abort_source = 0;
|
2009-06-22 07:36:29 -06:00
|
|
|
|
|
|
|
ret = i2c_dw_wait_bus_not_busy(dev);
|
|
|
|
if (ret < 0)
|
|
|
|
goto done;
|
|
|
|
|
|
|
|
/* start the transfers */
|
2009-11-06 05:48:55 -07:00
|
|
|
i2c_dw_xfer_init(dev);
|
2009-06-22 07:36:29 -06:00
|
|
|
|
|
|
|
/* wait for tx to complete */
|
|
|
|
ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ);
|
|
|
|
if (ret == 0) {
|
|
|
|
dev_err(dev->dev, "controller timed out\n");
|
|
|
|
i2c_dw_init(dev);
|
|
|
|
ret = -ETIMEDOUT;
|
|
|
|
goto done;
|
|
|
|
} else if (ret < 0)
|
|
|
|
goto done;
|
|
|
|
|
|
|
|
if (dev->msg_err) {
|
|
|
|
ret = dev->msg_err;
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* no error */
|
|
|
|
if (likely(!dev->cmd_err)) {
|
i2c-designware: Process i2c_msg messages in the interrupt handler
Symptom:
--------
When we're going to send/receive the longer size of data than the Tx
FIFO length, the I2C transaction will be divided into several separated
transactions, limited by the Tx FIFO length.
Details:
--------
As a hardware feature, DW I2C core generates a STOP condition whenever
the Tx FIFO becomes empty (strictly speaking, whenever the last byte in
the Tx FIFO is sent out), even if we have more bytes to be written.
Then, once a new transmit data is written to the Tx FIFO, DW I2C core
will initiate a new transaction, which leads to another START condition.
This explains how the transaction in question goes, and implies that
current tasklet-based dw_i2c_pump_msg() strategy couldn't meet the
timing constraint required for avoiding Tx FIFO underrun.
To avoid this scenario, we must keep providing new transmit data within
a given time period. In case of Fast-mode + 32-byte Tx FIFO, for
instance, it takes about 22.5[us] to process single byte, and 720[us] in
total.
This patch removes the existing tasklet-based "pump" system, and move
its jobs into the interrupt handler.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-11-06 05:47:51 -07:00
|
|
|
/* Disable the adapter */
|
2011-10-06 12:26:25 -06:00
|
|
|
dw_writel(dev, 0, DW_IC_ENABLE);
|
2009-06-22 07:36:29 -06:00
|
|
|
ret = num;
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We have an error */
|
|
|
|
if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
|
2009-11-06 05:51:57 -07:00
|
|
|
ret = i2c_dw_handle_tx_abort(dev);
|
|
|
|
goto done;
|
2009-06-22 07:36:29 -06:00
|
|
|
}
|
|
|
|
ret = -EIO;
|
|
|
|
|
|
|
|
done:
|
|
|
|
mutex_unlock(&dev->lock);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-10-29 03:57:23 -06:00
|
|
|
u32 i2c_dw_func(struct i2c_adapter *adap)
|
2009-06-22 07:36:29 -06:00
|
|
|
{
|
2011-10-06 12:26:31 -06:00
|
|
|
struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
|
|
|
|
return dev->functionality;
|
2009-06-22 07:36:29 -06:00
|
|
|
}
|
|
|
|
|
2009-11-06 05:44:37 -07:00
|
|
|
static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
|
|
|
|
{
|
|
|
|
u32 stat;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The IC_INTR_STAT register just indicates "enabled" interrupts.
|
|
|
|
* Ths unmasked raw version of interrupt status bits are available
|
|
|
|
* in the IC_RAW_INTR_STAT register.
|
|
|
|
*
|
|
|
|
* That is,
|
2011-10-29 03:57:23 -06:00
|
|
|
* stat = dw_readl(IC_INTR_STAT);
|
2009-11-06 05:44:37 -07:00
|
|
|
* equals to,
|
2011-10-29 03:57:23 -06:00
|
|
|
* stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
|
2009-11-06 05:44:37 -07:00
|
|
|
*
|
|
|
|
* The raw version might be useful for debugging purposes.
|
|
|
|
*/
|
2011-10-06 12:26:25 -06:00
|
|
|
stat = dw_readl(dev, DW_IC_INTR_STAT);
|
2009-11-06 05:44:37 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Do not use the IC_CLR_INTR register to clear interrupts, or
|
|
|
|
* you'll miss some interrupts, triggered during the period from
|
2011-10-29 03:57:23 -06:00
|
|
|
* dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
|
2009-11-06 05:44:37 -07:00
|
|
|
*
|
|
|
|
* Instead, use the separately-prepared IC_CLR_* registers.
|
|
|
|
*/
|
|
|
|
if (stat & DW_IC_INTR_RX_UNDER)
|
2011-10-06 12:26:25 -06:00
|
|
|
dw_readl(dev, DW_IC_CLR_RX_UNDER);
|
2009-11-06 05:44:37 -07:00
|
|
|
if (stat & DW_IC_INTR_RX_OVER)
|
2011-10-06 12:26:25 -06:00
|
|
|
dw_readl(dev, DW_IC_CLR_RX_OVER);
|
2009-11-06 05:44:37 -07:00
|
|
|
if (stat & DW_IC_INTR_TX_OVER)
|
2011-10-06 12:26:25 -06:00
|
|
|
dw_readl(dev, DW_IC_CLR_TX_OVER);
|
2009-11-06 05:44:37 -07:00
|
|
|
if (stat & DW_IC_INTR_RD_REQ)
|
2011-10-06 12:26:25 -06:00
|
|
|
dw_readl(dev, DW_IC_CLR_RD_REQ);
|
2009-11-06 05:44:37 -07:00
|
|
|
if (stat & DW_IC_INTR_TX_ABRT) {
|
|
|
|
/*
|
|
|
|
* The IC_TX_ABRT_SOURCE register is cleared whenever
|
|
|
|
* the IC_CLR_TX_ABRT is read. Preserve it beforehand.
|
|
|
|
*/
|
2011-10-06 12:26:25 -06:00
|
|
|
dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
|
|
|
|
dw_readl(dev, DW_IC_CLR_TX_ABRT);
|
2009-11-06 05:44:37 -07:00
|
|
|
}
|
|
|
|
if (stat & DW_IC_INTR_RX_DONE)
|
2011-10-06 12:26:25 -06:00
|
|
|
dw_readl(dev, DW_IC_CLR_RX_DONE);
|
2009-11-06 05:44:37 -07:00
|
|
|
if (stat & DW_IC_INTR_ACTIVITY)
|
2011-10-06 12:26:25 -06:00
|
|
|
dw_readl(dev, DW_IC_CLR_ACTIVITY);
|
2009-11-06 05:44:37 -07:00
|
|
|
if (stat & DW_IC_INTR_STOP_DET)
|
2011-10-06 12:26:25 -06:00
|
|
|
dw_readl(dev, DW_IC_CLR_STOP_DET);
|
2009-11-06 05:44:37 -07:00
|
|
|
if (stat & DW_IC_INTR_START_DET)
|
2011-10-06 12:26:25 -06:00
|
|
|
dw_readl(dev, DW_IC_CLR_START_DET);
|
2009-11-06 05:44:37 -07:00
|
|
|
if (stat & DW_IC_INTR_GEN_CALL)
|
2011-10-06 12:26:25 -06:00
|
|
|
dw_readl(dev, DW_IC_CLR_GEN_CALL);
|
2009-11-06 05:44:37 -07:00
|
|
|
|
|
|
|
return stat;
|
|
|
|
}
|
|
|
|
|
2009-06-22 07:36:29 -06:00
|
|
|
/*
|
|
|
|
* Interrupt service routine. This gets called whenever an I2C interrupt
|
|
|
|
* occurs.
|
|
|
|
*/
|
2011-10-29 03:57:23 -06:00
|
|
|
irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
|
2009-06-22 07:36:29 -06:00
|
|
|
{
|
|
|
|
struct dw_i2c_dev *dev = dev_id;
|
2011-10-06 12:26:33 -06:00
|
|
|
u32 stat, enabled;
|
|
|
|
|
|
|
|
enabled = dw_readl(dev, DW_IC_ENABLE);
|
|
|
|
stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
|
|
|
|
dev_dbg(dev->dev, "%s: %s enabled= 0x%x stat=0x%x\n", __func__,
|
|
|
|
dev->adapter.name, enabled, stat);
|
|
|
|
if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
|
|
|
|
return IRQ_NONE;
|
2009-06-22 07:36:29 -06:00
|
|
|
|
2009-11-06 05:44:37 -07:00
|
|
|
stat = i2c_dw_read_clear_intrbits(dev);
|
|
|
|
|
2009-06-22 07:36:29 -06:00
|
|
|
if (stat & DW_IC_INTR_TX_ABRT) {
|
|
|
|
dev->cmd_err |= DW_IC_ERR_TX_ABRT;
|
|
|
|
dev->status = STATUS_IDLE;
|
2009-11-06 05:51:36 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Anytime TX_ABRT is set, the contents of the tx/rx
|
|
|
|
* buffers are flushed. Make sure to skip them.
|
|
|
|
*/
|
2011-10-06 12:26:25 -06:00
|
|
|
dw_writel(dev, 0, DW_IC_INTR_MASK);
|
2009-11-06 05:51:36 -07:00
|
|
|
goto tx_aborted;
|
i2c-designware: Process i2c_msg messages in the interrupt handler
Symptom:
--------
When we're going to send/receive the longer size of data than the Tx
FIFO length, the I2C transaction will be divided into several separated
transactions, limited by the Tx FIFO length.
Details:
--------
As a hardware feature, DW I2C core generates a STOP condition whenever
the Tx FIFO becomes empty (strictly speaking, whenever the last byte in
the Tx FIFO is sent out), even if we have more bytes to be written.
Then, once a new transmit data is written to the Tx FIFO, DW I2C core
will initiate a new transaction, which leads to another START condition.
This explains how the transaction in question goes, and implies that
current tasklet-based dw_i2c_pump_msg() strategy couldn't meet the
timing constraint required for avoiding Tx FIFO underrun.
To avoid this scenario, we must keep providing new transmit data within
a given time period. In case of Fast-mode + 32-byte Tx FIFO, for
instance, it takes about 22.5[us] to process single byte, and 720[us] in
total.
This patch removes the existing tasklet-based "pump" system, and move
its jobs into the interrupt handler.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-11-06 05:47:51 -07:00
|
|
|
}
|
|
|
|
|
2009-11-06 05:48:33 -07:00
|
|
|
if (stat & DW_IC_INTR_RX_FULL)
|
i2c-designware: Process i2c_msg messages in the interrupt handler
Symptom:
--------
When we're going to send/receive the longer size of data than the Tx
FIFO length, the I2C transaction will be divided into several separated
transactions, limited by the Tx FIFO length.
Details:
--------
As a hardware feature, DW I2C core generates a STOP condition whenever
the Tx FIFO becomes empty (strictly speaking, whenever the last byte in
the Tx FIFO is sent out), even if we have more bytes to be written.
Then, once a new transmit data is written to the Tx FIFO, DW I2C core
will initiate a new transaction, which leads to another START condition.
This explains how the transaction in question goes, and implies that
current tasklet-based dw_i2c_pump_msg() strategy couldn't meet the
timing constraint required for avoiding Tx FIFO underrun.
To avoid this scenario, we must keep providing new transmit data within
a given time period. In case of Fast-mode + 32-byte Tx FIFO, for
instance, it takes about 22.5[us] to process single byte, and 720[us] in
total.
This patch removes the existing tasklet-based "pump" system, and move
its jobs into the interrupt handler.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-11-06 05:47:51 -07:00
|
|
|
i2c_dw_read(dev);
|
2009-11-06 05:48:33 -07:00
|
|
|
|
|
|
|
if (stat & DW_IC_INTR_TX_EMPTY)
|
i2c-designware: Process i2c_msg messages in the interrupt handler
Symptom:
--------
When we're going to send/receive the longer size of data than the Tx
FIFO length, the I2C transaction will be divided into several separated
transactions, limited by the Tx FIFO length.
Details:
--------
As a hardware feature, DW I2C core generates a STOP condition whenever
the Tx FIFO becomes empty (strictly speaking, whenever the last byte in
the Tx FIFO is sent out), even if we have more bytes to be written.
Then, once a new transmit data is written to the Tx FIFO, DW I2C core
will initiate a new transaction, which leads to another START condition.
This explains how the transaction in question goes, and implies that
current tasklet-based dw_i2c_pump_msg() strategy couldn't meet the
timing constraint required for avoiding Tx FIFO underrun.
To avoid this scenario, we must keep providing new transmit data within
a given time period. In case of Fast-mode + 32-byte Tx FIFO, for
instance, it takes about 22.5[us] to process single byte, and 720[us] in
total.
This patch removes the existing tasklet-based "pump" system, and move
its jobs into the interrupt handler.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-11-06 05:47:51 -07:00
|
|
|
i2c_dw_xfer_msg(dev);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* No need to modify or disable the interrupt mask here.
|
|
|
|
* i2c_dw_xfer_msg() will take care of it according to
|
|
|
|
* the current transmit status.
|
|
|
|
*/
|
2009-06-22 07:36:29 -06:00
|
|
|
|
2009-11-06 05:51:36 -07:00
|
|
|
tx_aborted:
|
2009-11-06 05:51:18 -07:00
|
|
|
if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
|
2009-06-22 07:36:29 -06:00
|
|
|
complete(&dev->cmd_complete);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|