2005-10-10 06:36:14 -06:00
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/*
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* This file contains miscellaneous low-level functions.
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
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* and Paul Mackerras.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/config.h>
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#include <linux/sys.h>
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#include <asm/unistd.h>
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#include <asm/errno.h>
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/cache.h>
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#include <asm/cputable.h>
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#include <asm/mmu.h>
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#include <asm/ppc_asm.h>
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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.text
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2005-10-19 17:23:26 -06:00
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/*
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* This returns the high 64 bits of the product of two 64-bit numbers.
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*/
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_GLOBAL(mulhdu)
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cmpwi r6,0
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cmpwi cr1,r3,0
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mr r10,r4
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mulhwu r4,r4,r5
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beq 1f
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mulhwu r0,r10,r6
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mullw r7,r10,r5
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addc r7,r0,r7
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addze r4,r4
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1: beqlr cr1 /* all done if high part of A is 0 */
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mr r10,r3
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mullw r9,r3,r5
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mulhwu r3,r3,r5
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beq 2f
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mullw r0,r10,r6
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mulhwu r8,r10,r6
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addc r7,r0,r7
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adde r4,r4,r8
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addze r3,r3
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2: addc r4,r4,r9
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addze r3,r3
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blr
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2005-10-10 06:36:14 -06:00
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/*
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* Returns (address we're running at) - (address we were linked at)
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* for use before the text and data are mapped to KERNELBASE.
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*/
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_GLOBAL(reloc_offset)
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mflr r0
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bl 1f
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1: mflr r3
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2005-10-12 01:44:55 -06:00
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LOADADDR(r4,1b)
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2005-10-10 06:36:14 -06:00
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subf r3,r4,r3
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mtlr r0
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blr
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/*
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* add_reloc_offset(x) returns x + reloc_offset().
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*/
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_GLOBAL(add_reloc_offset)
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mflr r0
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bl 1f
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1: mflr r5
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2005-10-12 01:44:55 -06:00
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LOADADDR(r4,1b)
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2005-10-10 06:36:14 -06:00
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subf r5,r4,r5
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add r3,r3,r5
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mtlr r0
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blr
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/*
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* sub_reloc_offset(x) returns x - reloc_offset().
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*/
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_GLOBAL(sub_reloc_offset)
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mflr r0
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bl 1f
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1: mflr r5
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lis r4,1b@ha
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addi r4,r4,1b@l
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subf r5,r4,r5
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subf r3,r5,r3
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mtlr r0
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blr
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/*
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* reloc_got2 runs through the .got2 section adding an offset
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* to each entry.
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*/
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_GLOBAL(reloc_got2)
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mflr r11
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lis r7,__got2_start@ha
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addi r7,r7,__got2_start@l
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lis r8,__got2_end@ha
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addi r8,r8,__got2_end@l
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subf r8,r7,r8
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srwi. r8,r8,2
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beqlr
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mtctr r8
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bl 1f
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1: mflr r0
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lis r4,1b@ha
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addi r4,r4,1b@l
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subf r0,r4,r0
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add r7,r0,r7
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2: lwz r0,0(r7)
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add r0,r0,r3
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stw r0,0(r7)
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addi r7,r7,4
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bdnz 2b
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mtlr r11
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blr
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/*
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* identify_cpu,
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* called with r3 = data offset and r4 = CPU number
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* doesn't change r3
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*/
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_GLOBAL(identify_cpu)
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addis r8,r3,cpu_specs@ha
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addi r8,r8,cpu_specs@l
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mfpvr r7
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1:
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lwz r5,CPU_SPEC_PVR_MASK(r8)
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and r5,r5,r7
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lwz r6,CPU_SPEC_PVR_VALUE(r8)
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cmplw 0,r6,r5
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beq 1f
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addi r8,r8,CPU_SPEC_ENTRY_SIZE
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b 1b
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1:
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addis r6,r3,cur_cpu_spec@ha
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addi r6,r6,cur_cpu_spec@l
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sub r8,r8,r3
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stw r8,0(r6)
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blr
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/*
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* do_cpu_ftr_fixups - goes through the list of CPU feature fixups
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* and writes nop's over sections of code that don't apply for this cpu.
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* r3 = data offset (not changed)
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*/
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_GLOBAL(do_cpu_ftr_fixups)
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/* Get CPU 0 features */
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addis r6,r3,cur_cpu_spec@ha
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addi r6,r6,cur_cpu_spec@l
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lwz r4,0(r6)
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add r4,r4,r3
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lwz r4,CPU_SPEC_FEATURES(r4)
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/* Get the fixup table */
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addis r6,r3,__start___ftr_fixup@ha
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addi r6,r6,__start___ftr_fixup@l
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addis r7,r3,__stop___ftr_fixup@ha
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addi r7,r7,__stop___ftr_fixup@l
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/* Do the fixup */
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1: cmplw 0,r6,r7
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bgelr
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addi r6,r6,16
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lwz r8,-16(r6) /* mask */
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and r8,r8,r4
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lwz r9,-12(r6) /* value */
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cmplw 0,r8,r9
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beq 1b
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lwz r8,-8(r6) /* section begin */
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lwz r9,-4(r6) /* section end */
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subf. r9,r8,r9
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beq 1b
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/* write nops over the section of code */
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/* todo: if large section, add a branch at the start of it */
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srwi r9,r9,2
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mtctr r9
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add r8,r8,r3
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lis r0,0x60000000@h /* nop */
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3: stw r0,0(r8)
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andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l
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beq 2f
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dcbst 0,r8 /* suboptimal, but simpler */
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sync
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icbi 0,r8
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2: addi r8,r8,4
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bdnz 3b
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sync /* additional sync needed on g4 */
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isync
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b 1b
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/*
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* call_setup_cpu - call the setup_cpu function for this cpu
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* r3 = data offset, r24 = cpu number
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*
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* Setup function is called with:
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* r3 = data offset
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* r4 = ptr to CPU spec (relocated)
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*/
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_GLOBAL(call_setup_cpu)
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addis r4,r3,cur_cpu_spec@ha
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addi r4,r4,cur_cpu_spec@l
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lwz r4,0(r4)
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add r4,r4,r3
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lwz r5,CPU_SPEC_SETUP(r4)
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cmpi 0,r5,0
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add r5,r5,r3
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beqlr
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mtctr r5
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bctr
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#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
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/* This gets called by via-pmu.c to switch the PLL selection
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* on 750fx CPU. This function should really be moved to some
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* other place (as most of the cpufreq code in via-pmu
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*/
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_GLOBAL(low_choose_750fx_pll)
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/* Clear MSR:EE */
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mfmsr r7
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rlwinm r0,r7,0,17,15
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mtmsr r0
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/* If switching to PLL1, disable HID0:BTIC */
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cmplwi cr0,r3,0
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beq 1f
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mfspr r5,SPRN_HID0
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rlwinm r5,r5,0,27,25
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sync
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mtspr SPRN_HID0,r5
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isync
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sync
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1:
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/* Calc new HID1 value */
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mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
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rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
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rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
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or r4,r4,r5
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mtspr SPRN_HID1,r4
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/* Store new HID1 image */
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rlwinm r6,r1,0,0,18
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lwz r6,TI_CPU(r6)
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slwi r6,r6,2
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addis r6,r6,nap_save_hid1@ha
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stw r4,nap_save_hid1@l(r6)
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/* If switching to PLL0, enable HID0:BTIC */
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cmplwi cr0,r3,0
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bne 1f
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mfspr r5,SPRN_HID0
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ori r5,r5,HID0_BTIC
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sync
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mtspr SPRN_HID0,r5
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isync
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sync
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1:
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/* Return */
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mtmsr r7
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blr
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_GLOBAL(low_choose_7447a_dfs)
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/* Clear MSR:EE */
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mfmsr r7
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rlwinm r0,r7,0,17,15
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mtmsr r0
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/* Calc new HID1 value */
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mfspr r4,SPRN_HID1
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insrwi r4,r3,1,9 /* insert parameter into bit 9 */
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sync
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mtspr SPRN_HID1,r4
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sync
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isync
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/* Return */
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mtmsr r7
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blr
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#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
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/*
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* complement mask on the msr then "or" some values on.
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* _nmask_and_or_msr(nmask, value_to_or)
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*/
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_GLOBAL(_nmask_and_or_msr)
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mfmsr r0 /* Get current msr */
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andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
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or r0,r0,r4 /* Or on the bits in r4 (second parm) */
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SYNC /* Some chip revs have problems here... */
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mtmsr r0 /* Update machine state */
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isync
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blr /* Done */
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/*
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* Flush MMU TLB
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*/
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_GLOBAL(_tlbia)
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#if defined(CONFIG_40x)
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sync /* Flush to memory before changing mapping */
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tlbia
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isync /* Flush shadow TLB */
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#elif defined(CONFIG_44x)
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li r3,0
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sync
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/* Load high watermark */
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lis r4,tlb_44x_hwater@ha
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lwz r5,tlb_44x_hwater@l(r4)
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1: tlbwe r3,r3,PPC44x_TLB_PAGEID
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addi r3,r3,1
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cmpw 0,r3,r5
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ble 1b
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isync
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#elif defined(CONFIG_FSL_BOOKE)
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/* Invalidate all entries in TLB0 */
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li r3, 0x04
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tlbivax 0,3
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/* Invalidate all entries in TLB1 */
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li r3, 0x0c
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tlbivax 0,3
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/* Invalidate all entries in TLB2 */
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li r3, 0x14
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tlbivax 0,3
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/* Invalidate all entries in TLB3 */
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li r3, 0x1c
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tlbivax 0,3
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msync
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#ifdef CONFIG_SMP
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tlbsync
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#endif /* CONFIG_SMP */
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#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
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#if defined(CONFIG_SMP)
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rlwinm r8,r1,0,0,18
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lwz r8,TI_CPU(r8)
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oris r8,r8,10
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mfmsr r10
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SYNC
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r0,0,28,26 /* clear DR */
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mtmsr r0
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SYNC_601
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isync
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lis r9,mmu_hash_lock@h
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ori r9,r9,mmu_hash_lock@l
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tophys(r9,r9)
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10: lwarx r7,0,r9
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cmpwi 0,r7,0
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bne- 10b
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stwcx. r8,0,r9
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bne- 10b
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sync
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tlbia
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sync
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TLBSYNC
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|
|
|
li r0,0
|
|
|
|
stw r0,0(r9) /* clear mmu_hash_lock */
|
|
|
|
mtmsr r10
|
|
|
|
SYNC_601
|
|
|
|
isync
|
|
|
|
#else /* CONFIG_SMP */
|
|
|
|
sync
|
|
|
|
tlbia
|
|
|
|
sync
|
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
#endif /* ! defined(CONFIG_40x) */
|
|
|
|
blr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Flush MMU TLB for a particular address
|
|
|
|
*/
|
|
|
|
_GLOBAL(_tlbie)
|
|
|
|
#if defined(CONFIG_40x)
|
|
|
|
tlbsx. r3, 0, r3
|
|
|
|
bne 10f
|
|
|
|
sync
|
|
|
|
/* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear.
|
|
|
|
* Since 25 is the V bit in the TLB_TAG, loading this value will invalidate
|
|
|
|
* the TLB entry. */
|
|
|
|
tlbwe r3, r3, TLB_TAG
|
|
|
|
isync
|
|
|
|
10:
|
|
|
|
#elif defined(CONFIG_44x)
|
|
|
|
mfspr r4,SPRN_MMUCR
|
|
|
|
mfspr r5,SPRN_PID /* Get PID */
|
|
|
|
rlwimi r4,r5,0,24,31 /* Set TID */
|
|
|
|
mtspr SPRN_MMUCR,r4
|
|
|
|
|
|
|
|
tlbsx. r3, 0, r3
|
|
|
|
bne 10f
|
|
|
|
sync
|
|
|
|
/* There are only 64 TLB entries, so r3 < 64,
|
|
|
|
* which means bit 22, is clear. Since 22 is
|
|
|
|
* the V bit in the TLB_PAGEID, loading this
|
|
|
|
* value will invalidate the TLB entry.
|
|
|
|
*/
|
|
|
|
tlbwe r3, r3, PPC44x_TLB_PAGEID
|
|
|
|
isync
|
|
|
|
10:
|
|
|
|
#elif defined(CONFIG_FSL_BOOKE)
|
|
|
|
rlwinm r4, r3, 0, 0, 19
|
|
|
|
ori r5, r4, 0x08 /* TLBSEL = 1 */
|
|
|
|
ori r6, r4, 0x10 /* TLBSEL = 2 */
|
|
|
|
ori r7, r4, 0x18 /* TLBSEL = 3 */
|
|
|
|
tlbivax 0, r4
|
|
|
|
tlbivax 0, r5
|
|
|
|
tlbivax 0, r6
|
|
|
|
tlbivax 0, r7
|
|
|
|
msync
|
|
|
|
#if defined(CONFIG_SMP)
|
|
|
|
tlbsync
|
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
|
|
|
|
#if defined(CONFIG_SMP)
|
|
|
|
rlwinm r8,r1,0,0,18
|
|
|
|
lwz r8,TI_CPU(r8)
|
|
|
|
oris r8,r8,11
|
|
|
|
mfmsr r10
|
|
|
|
SYNC
|
|
|
|
rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
|
|
|
|
rlwinm r0,r0,0,28,26 /* clear DR */
|
|
|
|
mtmsr r0
|
|
|
|
SYNC_601
|
|
|
|
isync
|
|
|
|
lis r9,mmu_hash_lock@h
|
|
|
|
ori r9,r9,mmu_hash_lock@l
|
|
|
|
tophys(r9,r9)
|
|
|
|
10: lwarx r7,0,r9
|
|
|
|
cmpwi 0,r7,0
|
|
|
|
bne- 10b
|
|
|
|
stwcx. r8,0,r9
|
|
|
|
bne- 10b
|
|
|
|
eieio
|
|
|
|
tlbie r3
|
|
|
|
sync
|
|
|
|
TLBSYNC
|
|
|
|
li r0,0
|
|
|
|
stw r0,0(r9) /* clear mmu_hash_lock */
|
|
|
|
mtmsr r10
|
|
|
|
SYNC_601
|
|
|
|
isync
|
|
|
|
#else /* CONFIG_SMP */
|
|
|
|
tlbie r3
|
|
|
|
sync
|
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
#endif /* ! CONFIG_40x */
|
|
|
|
blr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Flush instruction cache.
|
|
|
|
* This is a no-op on the 601.
|
|
|
|
*/
|
|
|
|
_GLOBAL(flush_instruction_cache)
|
|
|
|
#if defined(CONFIG_8xx)
|
|
|
|
isync
|
|
|
|
lis r5, IDC_INVALL@h
|
|
|
|
mtspr SPRN_IC_CST, r5
|
|
|
|
#elif defined(CONFIG_4xx)
|
|
|
|
#ifdef CONFIG_403GCX
|
|
|
|
li r3, 512
|
|
|
|
mtctr r3
|
|
|
|
lis r4, KERNELBASE@h
|
|
|
|
1: iccci 0, r4
|
|
|
|
addi r4, r4, 16
|
|
|
|
bdnz 1b
|
|
|
|
#else
|
|
|
|
lis r3, KERNELBASE@h
|
|
|
|
iccci 0,r3
|
|
|
|
#endif
|
|
|
|
#elif CONFIG_FSL_BOOKE
|
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
mfspr r3,SPRN_L1CSR0
|
|
|
|
ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
|
|
|
|
/* msync; isync recommended here */
|
|
|
|
mtspr SPRN_L1CSR0,r3
|
|
|
|
isync
|
|
|
|
blr
|
|
|
|
END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
|
|
|
|
mfspr r3,SPRN_L1CSR1
|
|
|
|
ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
|
|
|
|
mtspr SPRN_L1CSR1,r3
|
|
|
|
#else
|
|
|
|
mfspr r3,SPRN_PVR
|
|
|
|
rlwinm r3,r3,16,16,31
|
|
|
|
cmpwi 0,r3,1
|
|
|
|
beqlr /* for 601, do nothing */
|
|
|
|
/* 603/604 processor - use invalidate-all bit in HID0 */
|
|
|
|
mfspr r3,SPRN_HID0
|
|
|
|
ori r3,r3,HID0_ICFI
|
|
|
|
mtspr SPRN_HID0,r3
|
|
|
|
#endif /* CONFIG_8xx/4xx */
|
|
|
|
isync
|
|
|
|
blr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Write any modified data cache blocks out to memory
|
|
|
|
* and invalidate the corresponding instruction cache blocks.
|
|
|
|
* This is a no-op on the 601.
|
|
|
|
*
|
|
|
|
* flush_icache_range(unsigned long start, unsigned long stop)
|
|
|
|
*/
|
[PATCH] powerpc: Merge cacheflush.h and cache.h
The ppc32 and ppc64 versions of cacheflush.h were almost identical.
The two versions of cache.h are fairly similar, except for a bunch of
register definitions in the ppc32 version which probably belong better
elsewhere. This patch, therefore, merges both headers. Notable
points:
- there are several functions in cacheflush.h which exist only
on ppc32 or only on ppc64. These are handled by #ifdef for now, but
these should probably be consolidated, along with the actual code
behind them later.
- Confusingly, both ppc32 and ppc64 have a
flush_dcache_range(), but they're subtly different: it uses dcbf on
ppc32 and dcbst on ppc64, ppc64 has a flush_inval_dcache_range() which
uses dcbf. These too should be merged and consolidated later.
- Also flush_dcache_range() was defined in cacheflush.h on
ppc64, and in cache.h on ppc32. In the merged version it's in
cacheflush.h
- On ppc32 flush_icache_range() is a normal function from
misc.S. On ppc64, it was wrapper, testing a feature bit before
calling __flush_icache_range() which does the actual flush. This
patch takes the ppc64 approach, which amounts to no change on ppc32,
since CPU_FTR_COHERENT_ICACHE will never be set there, but does mean
renaming flush_icache_range() to __flush_icache_range() in
arch/ppc/kernel/misc.S and arch/powerpc/kernel/misc_32.S
- The PReP register info from asm-ppc/cache.h has moved to
arch/ppc/platforms/prep_setup.c
- The 8xx register info from asm-ppc/cache.h has moved to a
new asm-powerpc/reg_8xx.h, included from reg.h
- flush_dcache_all() was defined on ppc32 (only), but was
never called (although it was exported). Thus this patch removes it
from cacheflush.h and from ARCH=powerpc (misc_32.S) entirely. It's
left in ARCH=ppc for now, with the prototype moved to ppc_ksyms.c.
Built for Walnut (ARCH=ppc), 32-bit multiplatform (pmac, CHRP and PReP
ARCH=ppc, pmac and CHRP ARCH=powerpc). Built and booted on POWER5
LPAR (ARCH=powerpc and ARCH=ppc64).
Built for 32-bit powermac (ARCH=ppc and ARCH=powerpc). Built and
booted on POWER5 LPAR (ARCH=powerpc and ARCH=ppc64). Built and booted
on G5 (ARCH=powerpc)
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2005-11-09 17:50:16 -07:00
|
|
|
_GLOBAL(__flush_icache_range)
|
2005-10-10 06:36:14 -06:00
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
blr /* for 601, do nothing */
|
|
|
|
END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
|
2005-10-16 19:50:32 -06:00
|
|
|
li r5,L1_CACHE_BYTES-1
|
2005-10-10 06:36:14 -06:00
|
|
|
andc r3,r3,r5
|
|
|
|
subf r4,r3,r4
|
|
|
|
add r4,r4,r5
|
2005-10-16 19:50:32 -06:00
|
|
|
srwi. r4,r4,L1_CACHE_SHIFT
|
2005-10-10 06:36:14 -06:00
|
|
|
beqlr
|
|
|
|
mtctr r4
|
|
|
|
mr r6,r3
|
|
|
|
1: dcbst 0,r3
|
2005-10-16 19:50:32 -06:00
|
|
|
addi r3,r3,L1_CACHE_BYTES
|
2005-10-10 06:36:14 -06:00
|
|
|
bdnz 1b
|
|
|
|
sync /* wait for dcbst's to get to ram */
|
|
|
|
mtctr r4
|
|
|
|
2: icbi 0,r6
|
2005-10-16 19:50:32 -06:00
|
|
|
addi r6,r6,L1_CACHE_BYTES
|
2005-10-10 06:36:14 -06:00
|
|
|
bdnz 2b
|
|
|
|
sync /* additional sync needed on g4 */
|
|
|
|
isync
|
|
|
|
blr
|
|
|
|
/*
|
|
|
|
* Write any modified data cache blocks out to memory.
|
|
|
|
* Does not invalidate the corresponding cache lines (especially for
|
|
|
|
* any corresponding instruction cache).
|
|
|
|
*
|
|
|
|
* clean_dcache_range(unsigned long start, unsigned long stop)
|
|
|
|
*/
|
|
|
|
_GLOBAL(clean_dcache_range)
|
2005-10-16 19:50:32 -06:00
|
|
|
li r5,L1_CACHE_BYTES-1
|
2005-10-10 06:36:14 -06:00
|
|
|
andc r3,r3,r5
|
|
|
|
subf r4,r3,r4
|
|
|
|
add r4,r4,r5
|
2005-10-16 19:50:32 -06:00
|
|
|
srwi. r4,r4,L1_CACHE_SHIFT
|
2005-10-10 06:36:14 -06:00
|
|
|
beqlr
|
|
|
|
mtctr r4
|
|
|
|
|
|
|
|
1: dcbst 0,r3
|
2005-10-16 19:50:32 -06:00
|
|
|
addi r3,r3,L1_CACHE_BYTES
|
2005-10-10 06:36:14 -06:00
|
|
|
bdnz 1b
|
|
|
|
sync /* wait for dcbst's to get to ram */
|
|
|
|
blr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Write any modified data cache blocks out to memory and invalidate them.
|
|
|
|
* Does not invalidate the corresponding instruction cache blocks.
|
|
|
|
*
|
|
|
|
* flush_dcache_range(unsigned long start, unsigned long stop)
|
|
|
|
*/
|
|
|
|
_GLOBAL(flush_dcache_range)
|
2005-10-16 19:50:32 -06:00
|
|
|
li r5,L1_CACHE_BYTES-1
|
2005-10-10 06:36:14 -06:00
|
|
|
andc r3,r3,r5
|
|
|
|
subf r4,r3,r4
|
|
|
|
add r4,r4,r5
|
2005-10-16 19:50:32 -06:00
|
|
|
srwi. r4,r4,L1_CACHE_SHIFT
|
2005-10-10 06:36:14 -06:00
|
|
|
beqlr
|
|
|
|
mtctr r4
|
|
|
|
|
|
|
|
1: dcbf 0,r3
|
2005-10-16 19:50:32 -06:00
|
|
|
addi r3,r3,L1_CACHE_BYTES
|
2005-10-10 06:36:14 -06:00
|
|
|
bdnz 1b
|
|
|
|
sync /* wait for dcbst's to get to ram */
|
|
|
|
blr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Like above, but invalidate the D-cache. This is used by the 8xx
|
|
|
|
* to invalidate the cache so the PPC core doesn't get stale data
|
|
|
|
* from the CPM (no cache snooping here :-).
|
|
|
|
*
|
|
|
|
* invalidate_dcache_range(unsigned long start, unsigned long stop)
|
|
|
|
*/
|
|
|
|
_GLOBAL(invalidate_dcache_range)
|
2005-10-16 19:50:32 -06:00
|
|
|
li r5,L1_CACHE_BYTES-1
|
2005-10-10 06:36:14 -06:00
|
|
|
andc r3,r3,r5
|
|
|
|
subf r4,r3,r4
|
|
|
|
add r4,r4,r5
|
2005-10-16 19:50:32 -06:00
|
|
|
srwi. r4,r4,L1_CACHE_SHIFT
|
2005-10-10 06:36:14 -06:00
|
|
|
beqlr
|
|
|
|
mtctr r4
|
|
|
|
|
|
|
|
1: dcbi 0,r3
|
2005-10-16 19:50:32 -06:00
|
|
|
addi r3,r3,L1_CACHE_BYTES
|
2005-10-10 06:36:14 -06:00
|
|
|
bdnz 1b
|
|
|
|
sync /* wait for dcbi's to get to ram */
|
|
|
|
blr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Flush a particular page from the data cache to RAM.
|
|
|
|
* Note: this is necessary because the instruction cache does *not*
|
|
|
|
* snoop from the data cache.
|
|
|
|
* This is a no-op on the 601 which has a unified cache.
|
|
|
|
*
|
|
|
|
* void __flush_dcache_icache(void *page)
|
|
|
|
*/
|
|
|
|
_GLOBAL(__flush_dcache_icache)
|
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
blr /* for 601, do nothing */
|
|
|
|
END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
|
|
|
|
rlwinm r3,r3,0,0,19 /* Get page base address */
|
2005-10-16 19:50:32 -06:00
|
|
|
li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
|
2005-10-10 06:36:14 -06:00
|
|
|
mtctr r4
|
|
|
|
mr r6,r3
|
|
|
|
0: dcbst 0,r3 /* Write line to ram */
|
2005-10-16 19:50:32 -06:00
|
|
|
addi r3,r3,L1_CACHE_BYTES
|
2005-10-10 06:36:14 -06:00
|
|
|
bdnz 0b
|
|
|
|
sync
|
|
|
|
mtctr r4
|
|
|
|
1: icbi 0,r6
|
2005-10-16 19:50:32 -06:00
|
|
|
addi r6,r6,L1_CACHE_BYTES
|
2005-10-10 06:36:14 -06:00
|
|
|
bdnz 1b
|
|
|
|
sync
|
|
|
|
isync
|
|
|
|
blr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Flush a particular page from the data cache to RAM, identified
|
|
|
|
* by its physical address. We turn off the MMU so we can just use
|
|
|
|
* the physical address (this may be a highmem page without a kernel
|
|
|
|
* mapping).
|
|
|
|
*
|
|
|
|
* void __flush_dcache_icache_phys(unsigned long physaddr)
|
|
|
|
*/
|
|
|
|
_GLOBAL(__flush_dcache_icache_phys)
|
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
blr /* for 601, do nothing */
|
|
|
|
END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE)
|
|
|
|
mfmsr r10
|
|
|
|
rlwinm r0,r10,0,28,26 /* clear DR */
|
|
|
|
mtmsr r0
|
|
|
|
isync
|
|
|
|
rlwinm r3,r3,0,0,19 /* Get page base address */
|
2005-10-16 19:50:32 -06:00
|
|
|
li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
|
2005-10-10 06:36:14 -06:00
|
|
|
mtctr r4
|
|
|
|
mr r6,r3
|
|
|
|
0: dcbst 0,r3 /* Write line to ram */
|
2005-10-16 19:50:32 -06:00
|
|
|
addi r3,r3,L1_CACHE_BYTES
|
2005-10-10 06:36:14 -06:00
|
|
|
bdnz 0b
|
|
|
|
sync
|
|
|
|
mtctr r4
|
|
|
|
1: icbi 0,r6
|
2005-10-16 19:50:32 -06:00
|
|
|
addi r6,r6,L1_CACHE_BYTES
|
2005-10-10 06:36:14 -06:00
|
|
|
bdnz 1b
|
|
|
|
sync
|
|
|
|
mtmsr r10 /* restore DR */
|
|
|
|
isync
|
|
|
|
blr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear pages using the dcbz instruction, which doesn't cause any
|
|
|
|
* memory traffic (except to write out any cache lines which get
|
|
|
|
* displaced). This only works on cacheable memory.
|
|
|
|
*
|
|
|
|
* void clear_pages(void *page, int order) ;
|
|
|
|
*/
|
|
|
|
_GLOBAL(clear_pages)
|
2005-10-16 19:50:32 -06:00
|
|
|
li r0,4096/L1_CACHE_BYTES
|
2005-10-10 06:36:14 -06:00
|
|
|
slw r0,r0,r4
|
|
|
|
mtctr r0
|
|
|
|
#ifdef CONFIG_8xx
|
|
|
|
li r4, 0
|
|
|
|
1: stw r4, 0(r3)
|
|
|
|
stw r4, 4(r3)
|
|
|
|
stw r4, 8(r3)
|
|
|
|
stw r4, 12(r3)
|
|
|
|
#else
|
|
|
|
1: dcbz 0,r3
|
|
|
|
#endif
|
2005-10-16 19:50:32 -06:00
|
|
|
addi r3,r3,L1_CACHE_BYTES
|
2005-10-10 06:36:14 -06:00
|
|
|
bdnz 1b
|
|
|
|
blr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Copy a whole page. We use the dcbz instruction on the destination
|
|
|
|
* to reduce memory traffic (it eliminates the unnecessary reads of
|
|
|
|
* the destination into cache). This requires that the destination
|
|
|
|
* is cacheable.
|
|
|
|
*/
|
|
|
|
#define COPY_16_BYTES \
|
|
|
|
lwz r6,4(r4); \
|
|
|
|
lwz r7,8(r4); \
|
|
|
|
lwz r8,12(r4); \
|
|
|
|
lwzu r9,16(r4); \
|
|
|
|
stw r6,4(r3); \
|
|
|
|
stw r7,8(r3); \
|
|
|
|
stw r8,12(r3); \
|
|
|
|
stwu r9,16(r3)
|
|
|
|
|
|
|
|
_GLOBAL(copy_page)
|
|
|
|
addi r3,r3,-4
|
|
|
|
addi r4,r4,-4
|
|
|
|
|
|
|
|
#ifdef CONFIG_8xx
|
|
|
|
/* don't use prefetch on 8xx */
|
2005-10-16 19:50:32 -06:00
|
|
|
li r0,4096/L1_CACHE_BYTES
|
2005-10-10 06:36:14 -06:00
|
|
|
mtctr r0
|
|
|
|
1: COPY_16_BYTES
|
|
|
|
bdnz 1b
|
|
|
|
blr
|
|
|
|
|
|
|
|
#else /* not 8xx, we can prefetch */
|
|
|
|
li r5,4
|
|
|
|
|
|
|
|
#if MAX_COPY_PREFETCH > 1
|
|
|
|
li r0,MAX_COPY_PREFETCH
|
|
|
|
li r11,4
|
|
|
|
mtctr r0
|
|
|
|
11: dcbt r11,r4
|
2005-10-16 19:50:32 -06:00
|
|
|
addi r11,r11,L1_CACHE_BYTES
|
2005-10-10 06:36:14 -06:00
|
|
|
bdnz 11b
|
|
|
|
#else /* MAX_COPY_PREFETCH == 1 */
|
|
|
|
dcbt r5,r4
|
2005-10-16 19:50:32 -06:00
|
|
|
li r11,L1_CACHE_BYTES+4
|
2005-10-10 06:36:14 -06:00
|
|
|
#endif /* MAX_COPY_PREFETCH */
|
2005-10-16 19:50:32 -06:00
|
|
|
li r0,4096/L1_CACHE_BYTES - MAX_COPY_PREFETCH
|
2005-10-10 06:36:14 -06:00
|
|
|
crclr 4*cr0+eq
|
|
|
|
2:
|
|
|
|
mtctr r0
|
|
|
|
1:
|
|
|
|
dcbt r11,r4
|
|
|
|
dcbz r5,r3
|
|
|
|
COPY_16_BYTES
|
2005-10-16 19:50:32 -06:00
|
|
|
#if L1_CACHE_BYTES >= 32
|
2005-10-10 06:36:14 -06:00
|
|
|
COPY_16_BYTES
|
2005-10-16 19:50:32 -06:00
|
|
|
#if L1_CACHE_BYTES >= 64
|
2005-10-10 06:36:14 -06:00
|
|
|
COPY_16_BYTES
|
|
|
|
COPY_16_BYTES
|
2005-10-16 19:50:32 -06:00
|
|
|
#if L1_CACHE_BYTES >= 128
|
2005-10-10 06:36:14 -06:00
|
|
|
COPY_16_BYTES
|
|
|
|
COPY_16_BYTES
|
|
|
|
COPY_16_BYTES
|
|
|
|
COPY_16_BYTES
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
bdnz 1b
|
|
|
|
beqlr
|
|
|
|
crnot 4*cr0+eq,4*cr0+eq
|
|
|
|
li r0,MAX_COPY_PREFETCH
|
|
|
|
li r11,4
|
|
|
|
b 2b
|
|
|
|
#endif /* CONFIG_8xx */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* void atomic_clear_mask(atomic_t mask, atomic_t *addr)
|
|
|
|
* void atomic_set_mask(atomic_t mask, atomic_t *addr);
|
|
|
|
*/
|
|
|
|
_GLOBAL(atomic_clear_mask)
|
|
|
|
10: lwarx r5,0,r4
|
|
|
|
andc r5,r5,r3
|
|
|
|
PPC405_ERR77(0,r4)
|
|
|
|
stwcx. r5,0,r4
|
|
|
|
bne- 10b
|
|
|
|
blr
|
|
|
|
_GLOBAL(atomic_set_mask)
|
|
|
|
10: lwarx r5,0,r4
|
|
|
|
or r5,r5,r3
|
|
|
|
PPC405_ERR77(0,r4)
|
|
|
|
stwcx. r5,0,r4
|
|
|
|
bne- 10b
|
|
|
|
blr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* I/O string operations
|
|
|
|
*
|
|
|
|
* insb(port, buf, len)
|
|
|
|
* outsb(port, buf, len)
|
|
|
|
* insw(port, buf, len)
|
|
|
|
* outsw(port, buf, len)
|
|
|
|
* insl(port, buf, len)
|
|
|
|
* outsl(port, buf, len)
|
|
|
|
* insw_ns(port, buf, len)
|
|
|
|
* outsw_ns(port, buf, len)
|
|
|
|
* insl_ns(port, buf, len)
|
|
|
|
* outsl_ns(port, buf, len)
|
|
|
|
*
|
|
|
|
* The *_ns versions don't do byte-swapping.
|
|
|
|
*/
|
|
|
|
_GLOBAL(_insb)
|
|
|
|
cmpwi 0,r5,0
|
|
|
|
mtctr r5
|
|
|
|
subi r4,r4,1
|
|
|
|
blelr-
|
|
|
|
00: lbz r5,0(r3)
|
|
|
|
eieio
|
|
|
|
stbu r5,1(r4)
|
|
|
|
bdnz 00b
|
|
|
|
blr
|
|
|
|
|
|
|
|
_GLOBAL(_outsb)
|
|
|
|
cmpwi 0,r5,0
|
|
|
|
mtctr r5
|
|
|
|
subi r4,r4,1
|
|
|
|
blelr-
|
|
|
|
00: lbzu r5,1(r4)
|
|
|
|
stb r5,0(r3)
|
|
|
|
eieio
|
|
|
|
bdnz 00b
|
|
|
|
blr
|
|
|
|
|
|
|
|
_GLOBAL(_insw)
|
|
|
|
cmpwi 0,r5,0
|
|
|
|
mtctr r5
|
|
|
|
subi r4,r4,2
|
|
|
|
blelr-
|
|
|
|
00: lhbrx r5,0,r3
|
|
|
|
eieio
|
|
|
|
sthu r5,2(r4)
|
|
|
|
bdnz 00b
|
|
|
|
blr
|
|
|
|
|
|
|
|
_GLOBAL(_outsw)
|
|
|
|
cmpwi 0,r5,0
|
|
|
|
mtctr r5
|
|
|
|
subi r4,r4,2
|
|
|
|
blelr-
|
|
|
|
00: lhzu r5,2(r4)
|
|
|
|
eieio
|
|
|
|
sthbrx r5,0,r3
|
|
|
|
bdnz 00b
|
|
|
|
blr
|
|
|
|
|
|
|
|
_GLOBAL(_insl)
|
|
|
|
cmpwi 0,r5,0
|
|
|
|
mtctr r5
|
|
|
|
subi r4,r4,4
|
|
|
|
blelr-
|
|
|
|
00: lwbrx r5,0,r3
|
|
|
|
eieio
|
|
|
|
stwu r5,4(r4)
|
|
|
|
bdnz 00b
|
|
|
|
blr
|
|
|
|
|
|
|
|
_GLOBAL(_outsl)
|
|
|
|
cmpwi 0,r5,0
|
|
|
|
mtctr r5
|
|
|
|
subi r4,r4,4
|
|
|
|
blelr-
|
|
|
|
00: lwzu r5,4(r4)
|
|
|
|
stwbrx r5,0,r3
|
|
|
|
eieio
|
|
|
|
bdnz 00b
|
|
|
|
blr
|
|
|
|
|
|
|
|
_GLOBAL(__ide_mm_insw)
|
|
|
|
_GLOBAL(_insw_ns)
|
|
|
|
cmpwi 0,r5,0
|
|
|
|
mtctr r5
|
|
|
|
subi r4,r4,2
|
|
|
|
blelr-
|
|
|
|
00: lhz r5,0(r3)
|
|
|
|
eieio
|
|
|
|
sthu r5,2(r4)
|
|
|
|
bdnz 00b
|
|
|
|
blr
|
|
|
|
|
|
|
|
_GLOBAL(__ide_mm_outsw)
|
|
|
|
_GLOBAL(_outsw_ns)
|
|
|
|
cmpwi 0,r5,0
|
|
|
|
mtctr r5
|
|
|
|
subi r4,r4,2
|
|
|
|
blelr-
|
|
|
|
00: lhzu r5,2(r4)
|
|
|
|
sth r5,0(r3)
|
|
|
|
eieio
|
|
|
|
bdnz 00b
|
|
|
|
blr
|
|
|
|
|
|
|
|
_GLOBAL(__ide_mm_insl)
|
|
|
|
_GLOBAL(_insl_ns)
|
|
|
|
cmpwi 0,r5,0
|
|
|
|
mtctr r5
|
|
|
|
subi r4,r4,4
|
|
|
|
blelr-
|
|
|
|
00: lwz r5,0(r3)
|
|
|
|
eieio
|
|
|
|
stwu r5,4(r4)
|
|
|
|
bdnz 00b
|
|
|
|
blr
|
|
|
|
|
|
|
|
_GLOBAL(__ide_mm_outsl)
|
|
|
|
_GLOBAL(_outsl_ns)
|
|
|
|
cmpwi 0,r5,0
|
|
|
|
mtctr r5
|
|
|
|
subi r4,r4,4
|
|
|
|
blelr-
|
|
|
|
00: lwzu r5,4(r4)
|
|
|
|
stw r5,0(r3)
|
|
|
|
eieio
|
|
|
|
bdnz 00b
|
|
|
|
blr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Extended precision shifts.
|
|
|
|
*
|
|
|
|
* Updated to be valid for shift counts from 0 to 63 inclusive.
|
|
|
|
* -- Gabriel
|
|
|
|
*
|
|
|
|
* R3/R4 has 64 bit value
|
|
|
|
* R5 has shift count
|
|
|
|
* result in R3/R4
|
|
|
|
*
|
|
|
|
* ashrdi3: arithmetic right shift (sign propagation)
|
|
|
|
* lshrdi3: logical right shift
|
|
|
|
* ashldi3: left shift
|
|
|
|
*/
|
|
|
|
_GLOBAL(__ashrdi3)
|
|
|
|
subfic r6,r5,32
|
|
|
|
srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
|
|
|
|
addi r7,r5,32 # could be xori, or addi with -32
|
|
|
|
slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
|
|
|
|
rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
|
|
|
|
sraw r7,r3,r7 # t2 = MSW >> (count-32)
|
|
|
|
or r4,r4,r6 # LSW |= t1
|
|
|
|
slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
|
|
|
|
sraw r3,r3,r5 # MSW = MSW >> count
|
|
|
|
or r4,r4,r7 # LSW |= t2
|
|
|
|
blr
|
|
|
|
|
|
|
|
_GLOBAL(__ashldi3)
|
|
|
|
subfic r6,r5,32
|
|
|
|
slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
|
|
|
|
addi r7,r5,32 # could be xori, or addi with -32
|
|
|
|
srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
|
|
|
|
slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
|
|
|
|
or r3,r3,r6 # MSW |= t1
|
|
|
|
slw r4,r4,r5 # LSW = LSW << count
|
|
|
|
or r3,r3,r7 # MSW |= t2
|
|
|
|
blr
|
|
|
|
|
|
|
|
_GLOBAL(__lshrdi3)
|
|
|
|
subfic r6,r5,32
|
|
|
|
srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
|
|
|
|
addi r7,r5,32 # could be xori, or addi with -32
|
|
|
|
slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
|
|
|
|
srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
|
|
|
|
or r4,r4,r6 # LSW |= t1
|
|
|
|
srw r3,r3,r5 # MSW = MSW >> count
|
|
|
|
or r4,r4,r7 # LSW |= t2
|
|
|
|
blr
|
|
|
|
|
|
|
|
_GLOBAL(abs)
|
|
|
|
srawi r4,r3,31
|
|
|
|
xor r3,r3,r4
|
|
|
|
sub r3,r3,r4
|
|
|
|
blr
|
|
|
|
|
|
|
|
_GLOBAL(_get_SP)
|
|
|
|
mr r3,r1 /* Close enough */
|
|
|
|
blr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Create a kernel thread
|
|
|
|
* kernel_thread(fn, arg, flags)
|
|
|
|
*/
|
|
|
|
_GLOBAL(kernel_thread)
|
|
|
|
stwu r1,-16(r1)
|
|
|
|
stw r30,8(r1)
|
|
|
|
stw r31,12(r1)
|
|
|
|
mr r30,r3 /* function */
|
|
|
|
mr r31,r4 /* argument */
|
|
|
|
ori r3,r5,CLONE_VM /* flags */
|
|
|
|
oris r3,r3,CLONE_UNTRACED>>16
|
|
|
|
li r4,0 /* new sp (unused) */
|
|
|
|
li r0,__NR_clone
|
|
|
|
sc
|
|
|
|
cmpwi 0,r3,0 /* parent or child? */
|
|
|
|
bne 1f /* return if parent */
|
|
|
|
li r0,0 /* make top-level stack frame */
|
|
|
|
stwu r0,-16(r1)
|
|
|
|
mtlr r30 /* fn addr in lr */
|
|
|
|
mr r3,r31 /* load arg and call fn */
|
|
|
|
PPC440EP_ERR42
|
|
|
|
blrl
|
|
|
|
li r0,__NR_exit /* exit if function returns */
|
|
|
|
li r3,0
|
|
|
|
sc
|
|
|
|
1: lwz r30,8(r1)
|
|
|
|
lwz r31,12(r1)
|
|
|
|
addi r1,r1,16
|
|
|
|
blr
|
|
|
|
|
|
|
|
_GLOBAL(execve)
|
|
|
|
li r0,__NR_execve
|
|
|
|
sc
|
|
|
|
bnslr
|
|
|
|
neg r3,r3
|
|
|
|
blr
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This routine is just here to keep GCC happy - sigh...
|
|
|
|
*/
|
|
|
|
_GLOBAL(__main)
|
|
|
|
blr
|