2012-06-13 11:01:28 -06:00
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/*
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* Device Tree Include file for Marvell Armada 370 family SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* Contains definitions specific to the Armada 370 SoC that are not
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* common to all Armada SoCs.
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*/
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/include/ "armada-370-xp.dtsi"
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/ {
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model = "Marvell Armada 370 family SoC";
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compatible = "marvell,armada370", "marvell,armada-370-xp";
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2012-09-19 14:53:01 -06:00
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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};
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2012-06-13 11:01:28 -06:00
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soc {
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2013-04-12 08:29:07 -06:00
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mpic: interrupt-controller@d0020000 {
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reg = <0xd0020a00 0x1d0>,
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<0xd0021870 0x58>;
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};
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2012-06-13 11:01:28 -06:00
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system-controller@d0018200 {
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compatible = "marvell,armada-370-xp-system-controller";
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reg = <0xd0018200 0x100>;
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};
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2012-09-13 09:41:49 -06:00
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2013-04-12 08:29:07 -06:00
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L2: l2-cache {
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compatible = "marvell,aurora-outer-cache";
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reg = <0xd0008000 0x1000>;
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cache-id-part = <0x100>;
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wt-override;
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};
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2012-09-13 09:41:49 -06:00
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pinctrl {
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compatible = "marvell,mv88f6710-pinctrl";
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reg = <0xd0018000 0x38>;
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2012-12-21 07:49:05 -07:00
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sdio_pins1: sdio-pins1 {
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marvell,pins = "mpp9", "mpp11", "mpp12",
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"mpp13", "mpp14", "mpp15";
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marvell,function = "sd0";
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};
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sdio_pins2: sdio-pins2 {
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marvell,pins = "mpp47", "mpp48", "mpp49",
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"mpp50", "mpp51", "mpp52";
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marvell,function = "sd0";
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};
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2013-03-26 17:32:31 -06:00
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sdio_pins3: sdio-pins3 {
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marvell,pins = "mpp48", "mpp49", "mpp50",
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"mpp51", "mpp52", "mpp53";
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marvell,function = "sd0";
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};
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2012-09-19 14:53:01 -06:00
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};
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gpio0: gpio@d0018100 {
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compatible = "marvell,orion-gpio";
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reg = <0xd0018100 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupts-cells = <2>;
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interrupts = <82>, <83>, <84>, <85>;
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};
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gpio1: gpio@d0018140 {
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compatible = "marvell,orion-gpio";
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reg = <0xd0018140 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupts-cells = <2>;
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interrupts = <87>, <88>, <89>, <90>;
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};
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gpio2: gpio@d0018180 {
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compatible = "marvell,orion-gpio";
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reg = <0xd0018180 0x40>;
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ngpios = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupts-cells = <2>;
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interrupts = <91>;
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2012-09-13 09:41:49 -06:00
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};
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2012-11-17 07:22:24 -07:00
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coreclk: mvebu-sar@d0018230 {
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compatible = "marvell,armada-370-core-clock";
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reg = <0xd0018230 0x08>;
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#clock-cells = <1>;
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};
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gateclk: clock-gating-control@d0018220 {
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compatible = "marvell,armada-370-gating-clock";
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reg = <0xd0018220 0x4>;
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clocks = <&coreclk 0>;
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#clock-cells = <1>;
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};
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2012-11-20 08:03:12 -07:00
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xor@d0060800 {
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compatible = "marvell,orion-xor";
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reg = <0xd0060800 0x100
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0xd0060A00 0x100>;
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status = "okay";
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2012-11-17 07:22:24 -07:00
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2012-11-20 08:03:12 -07:00
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xor00 {
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interrupts = <51>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <52>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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xor@d0060900 {
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compatible = "marvell,orion-xor";
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reg = <0xd0060900 0x100
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0xd0060b00 0x100>;
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status = "okay";
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xor10 {
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interrupts = <94>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor11 {
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interrupts = <95>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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2013-01-23 08:26:30 -07:00
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usb@d0050000 {
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clocks = <&coreclk 0>;
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};
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usb@d0051000 {
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clocks = <&coreclk 0>;
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};
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2013-03-26 04:16:27 -06:00
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thermal@d0018300 {
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compatible = "marvell,armada370-thermal";
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reg = <0xd0018300 0x4
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0xd0018304 0x4>;
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status = "okay";
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};
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2013-04-09 15:06:33 -06:00
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pcie-controller {
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compatible = "marvell,armada-370-pcie";
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status = "disabled";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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reg = <0xd0040000 0x2000>, <0xd0080000 0x2000>;
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reg-names = "pcie0.0", "pcie1.0";
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ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
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0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
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0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
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0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
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pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 58>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 5>;
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status = "disabled";
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};
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pcie@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 62>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 9>;
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status = "disabled";
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};
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};
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2012-06-13 11:01:28 -06:00
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};
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};
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