2005-04-16 16:20:36 -06:00
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/*
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* cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
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* M (part of the Centrino chipset).
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*
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2006-06-21 14:15:48 -06:00
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* Since the original Pentium M, most new Intel CPUs support Enhanced
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* SpeedStep.
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*
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2005-04-16 16:20:36 -06:00
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* Despite the "SpeedStep" in the name, this is almost entirely unlike
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* traditional SpeedStep.
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*
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* Modelled on speedstep.c
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*
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* Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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2005-10-30 16:03:48 -07:00
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#include <linux/sched.h> /* current */
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2005-04-16 16:20:36 -06:00
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#include <linux/delay.h>
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#include <linux/compiler.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/gfp.h>
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2005-04-16 16:20:36 -06:00
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#include <asm/msr.h>
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#include <asm/processor.h>
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#include <asm/cpufeature.h>
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2012-01-25 16:09:12 -07:00
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#include <asm/cpu_device_id.h>
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2005-04-16 16:20:36 -06:00
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#define PFX "speedstep-centrino: "
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2014-04-21 23:12:05 -06:00
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#define MAINTAINER "linux-pm@vger.kernel.org"
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2005-04-16 16:20:36 -06:00
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2006-11-10 12:20:47 -07:00
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#define INTEL_MSR_RANGE (0xffff)
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2005-04-16 16:20:36 -06:00
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struct cpu_id
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{
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__u8 x86; /* CPU family */
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__u8 x86_model; /* model */
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__u8 x86_mask; /* stepping */
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};
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enum {
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CPU_BANIAS,
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CPU_DOTHAN_A1,
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CPU_DOTHAN_A2,
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CPU_DOTHAN_B0,
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2005-05-31 20:03:43 -06:00
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CPU_MP4HT_D0,
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CPU_MP4HT_E0,
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2005-04-16 16:20:36 -06:00
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};
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static const struct cpu_id cpu_ids[] = {
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[CPU_BANIAS] = { 6, 9, 5 },
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[CPU_DOTHAN_A1] = { 6, 13, 1 },
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[CPU_DOTHAN_A2] = { 6, 13, 2 },
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[CPU_DOTHAN_B0] = { 6, 13, 6 },
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2005-05-31 20:03:43 -06:00
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[CPU_MP4HT_D0] = {15, 3, 4 },
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[CPU_MP4HT_E0] = {15, 4, 1 },
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2005-04-16 16:20:36 -06:00
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};
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2005-11-07 01:58:31 -07:00
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#define N_IDS ARRAY_SIZE(cpu_ids)
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2005-04-16 16:20:36 -06:00
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struct cpu_model
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{
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const struct cpu_id *cpu_id;
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const char *model_name;
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unsigned max_freq; /* max clock in kHz */
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struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
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};
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2008-07-18 19:11:34 -06:00
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static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
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const struct cpu_id *x);
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2005-04-16 16:20:36 -06:00
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/* Operating points for current CPU */
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2008-07-18 19:11:34 -06:00
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static DEFINE_PER_CPU(struct cpu_model *, centrino_model);
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static DEFINE_PER_CPU(const struct cpu_id *, centrino_cpu);
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2005-04-16 16:20:36 -06:00
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static struct cpufreq_driver centrino_driver;
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#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
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/* Computes the correct form for IA32_PERF_CTL MSR for a particular
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frequency/voltage operating point; frequency in MHz, volts in mV.
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2013-03-30 04:55:15 -06:00
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This is stored as "driver_data" in the structure. */
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2005-04-16 16:20:36 -06:00
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#define OP(mhz, mv) \
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{ \
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.frequency = (mhz) * 1000, \
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2013-03-30 04:55:15 -06:00
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.driver_data = (((mhz)/100) << 8) | ((mv - 700) / 16) \
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2005-04-16 16:20:36 -06:00
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}
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/*
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* These voltage tables were derived from the Intel Pentium M
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* datasheet, document 25261202.pdf, Table 5. I have verified they
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* are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
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* M.
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*/
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/* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
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static struct cpufreq_frequency_table banias_900[] =
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{
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OP(600, 844),
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OP(800, 988),
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OP(900, 1004),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
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static struct cpufreq_frequency_table banias_1000[] =
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{
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OP(600, 844),
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OP(800, 972),
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OP(900, 988),
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OP(1000, 1004),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
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static struct cpufreq_frequency_table banias_1100[] =
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{
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OP( 600, 956),
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OP( 800, 1020),
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OP( 900, 1100),
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OP(1000, 1164),
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OP(1100, 1180),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
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static struct cpufreq_frequency_table banias_1200[] =
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{
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OP( 600, 956),
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OP( 800, 1004),
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OP( 900, 1020),
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OP(1000, 1100),
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OP(1100, 1164),
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OP(1200, 1180),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.30GHz (Banias) */
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static struct cpufreq_frequency_table banias_1300[] =
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{
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OP( 600, 956),
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OP( 800, 1260),
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OP(1000, 1292),
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OP(1200, 1356),
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OP(1300, 1388),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.40GHz (Banias) */
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static struct cpufreq_frequency_table banias_1400[] =
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{
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OP( 600, 956),
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OP( 800, 1180),
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OP(1000, 1308),
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OP(1200, 1436),
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OP(1400, 1484),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.50GHz (Banias) */
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static struct cpufreq_frequency_table banias_1500[] =
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{
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OP( 600, 956),
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OP( 800, 1116),
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OP(1000, 1228),
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OP(1200, 1356),
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OP(1400, 1452),
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OP(1500, 1484),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.60GHz (Banias) */
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static struct cpufreq_frequency_table banias_1600[] =
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{
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OP( 600, 956),
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OP( 800, 1036),
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OP(1000, 1164),
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OP(1200, 1276),
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OP(1400, 1420),
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OP(1600, 1484),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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/* Intel Pentium M processor 1.70GHz (Banias) */
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static struct cpufreq_frequency_table banias_1700[] =
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{
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OP( 600, 956),
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OP( 800, 1004),
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OP(1000, 1116),
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OP(1200, 1228),
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OP(1400, 1308),
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OP(1700, 1484),
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{ .frequency = CPUFREQ_TABLE_END }
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};
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#undef OP
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#define _BANIAS(cpuid, max, name) \
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{ .cpu_id = cpuid, \
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.model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
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.max_freq = (max)*1000, \
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.op_points = banias_##max, \
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}
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#define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
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/* CPU models, their operating frequency range, and freq/voltage
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operating points */
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static struct cpu_model models[] =
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{
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_BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
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BANIAS(1000),
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BANIAS(1100),
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BANIAS(1200),
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BANIAS(1300),
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BANIAS(1400),
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BANIAS(1500),
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BANIAS(1600),
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BANIAS(1700),
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/* NULL model_name is a wildcard */
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{ &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
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{ &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
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{ &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
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2005-05-31 20:03:43 -06:00
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{ &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
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{ &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
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2005-04-16 16:20:36 -06:00
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{ NULL, }
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};
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#undef _BANIAS
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#undef BANIAS
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static int centrino_cpu_init_table(struct cpufreq_policy *policy)
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{
|
2007-10-19 12:35:04 -06:00
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struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
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2005-04-16 16:20:36 -06:00
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struct cpu_model *model;
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for(model = models; model->cpu_id != NULL; model++)
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if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
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(model->model_name == NULL ||
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strcmp(cpu->x86_model_id, model->model_name) == 0))
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break;
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if (model->cpu_id == NULL) {
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/* No match at all */
|
2011-03-27 07:04:46 -06:00
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pr_debug("no support for CPU model \"%s\": "
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2005-04-16 16:20:36 -06:00
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"send /proc/cpuinfo to " MAINTAINER "\n",
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cpu->x86_model_id);
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return -ENOENT;
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}
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if (model->op_points == NULL) {
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/* Matched a non-match */
|
2011-03-27 07:04:46 -06:00
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pr_debug("no table support for CPU model \"%s\"\n",
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2005-04-16 16:20:36 -06:00
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cpu->x86_model_id);
|
2011-03-27 07:04:46 -06:00
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pr_debug("try using the acpi-cpufreq driver\n");
|
2005-04-16 16:20:36 -06:00
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return -ENOENT;
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}
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|
2008-07-18 19:11:34 -06:00
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per_cpu(centrino_model, policy->cpu) = model;
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2005-04-16 16:20:36 -06:00
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|
2011-03-27 07:04:46 -06:00
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pr_debug("found \"%s\": max frequency: %dkHz\n",
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2005-04-16 16:20:36 -06:00
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model->model_name, model->max_freq);
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return 0;
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}
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#else
|
2008-07-18 19:11:34 -06:00
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static inline int centrino_cpu_init_table(struct cpufreq_policy *policy)
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|
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{
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return -ENODEV;
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}
|
2005-04-16 16:20:36 -06:00
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#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
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2008-07-18 19:11:34 -06:00
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|
static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
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|
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const struct cpu_id *x)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
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if ((c->x86 == x->x86) &&
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(c->x86_model == x->x86_model) &&
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(c->x86_mask == x->x86_mask))
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return 1;
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return 0;
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}
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|
/* To be called only after centrino_model is initialized */
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|
|
static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
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|
|
{
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|
int i;
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/*
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|
* Extract clock in kHz from PERF_CTL value
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* for centrino, as some DSDTs are buggy.
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|
|
* Ideally, this can be done using the acpi_data structure.
|
|
|
|
*/
|
2008-07-18 19:11:34 -06:00
|
|
|
if ((per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_BANIAS]) ||
|
|
|
|
(per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_A1]) ||
|
|
|
|
(per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_B0])) {
|
2005-04-16 16:20:36 -06:00
|
|
|
msr = (msr >> 8) & 0xff;
|
|
|
|
return msr * 100000;
|
|
|
|
}
|
|
|
|
|
2008-07-18 19:11:34 -06:00
|
|
|
if ((!per_cpu(centrino_model, cpu)) ||
|
|
|
|
(!per_cpu(centrino_model, cpu)->op_points))
|
2005-04-16 16:20:36 -06:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
msr &= 0xffff;
|
2008-07-18 19:11:34 -06:00
|
|
|
for (i = 0;
|
|
|
|
per_cpu(centrino_model, cpu)->op_points[i].frequency
|
|
|
|
!= CPUFREQ_TABLE_END;
|
|
|
|
i++) {
|
2013-03-30 04:55:15 -06:00
|
|
|
if (msr == per_cpu(centrino_model, cpu)->op_points[i].driver_data)
|
2008-07-18 19:11:34 -06:00
|
|
|
return per_cpu(centrino_model, cpu)->
|
|
|
|
op_points[i].frequency;
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
if (failsafe)
|
2008-07-18 19:11:34 -06:00
|
|
|
return per_cpu(centrino_model, cpu)->op_points[i-1].frequency;
|
2005-04-16 16:20:36 -06:00
|
|
|
else
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return the current CPU frequency in kHz */
|
|
|
|
static unsigned int get_cur_freq(unsigned int cpu)
|
|
|
|
{
|
|
|
|
unsigned l, h;
|
|
|
|
unsigned clock_freq;
|
|
|
|
|
2009-06-11 07:29:58 -06:00
|
|
|
rdmsr_on_cpu(cpu, MSR_IA32_PERF_STATUS, &l, &h);
|
2005-04-16 16:20:36 -06:00
|
|
|
clock_freq = extract_clock(l, cpu, 0);
|
|
|
|
|
|
|
|
if (unlikely(clock_freq == 0)) {
|
|
|
|
/*
|
|
|
|
* On some CPUs, we can see transient MSR values (which are
|
|
|
|
* not present in _PSS), while CPU is doing some automatic
|
|
|
|
* P-state transition (like TM2). Get the last freq set
|
|
|
|
* in PERF_CTL.
|
|
|
|
*/
|
2009-06-11 07:29:58 -06:00
|
|
|
rdmsr_on_cpu(cpu, MSR_IA32_PERF_CTL, &l, &h);
|
2005-04-16 16:20:36 -06:00
|
|
|
clock_freq = extract_clock(l, cpu, 1);
|
|
|
|
}
|
|
|
|
return clock_freq;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int centrino_cpu_init(struct cpufreq_policy *policy)
|
|
|
|
{
|
2007-10-19 12:35:04 -06:00
|
|
|
struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
|
2005-04-16 16:20:36 -06:00
|
|
|
unsigned l, h;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Only Intel makes Enhanced Speedstep-capable CPUs */
|
2008-07-18 19:11:34 -06:00
|
|
|
if (cpu->x86_vendor != X86_VENDOR_INTEL ||
|
|
|
|
!cpu_has(cpu, X86_FEATURE_EST))
|
2005-04-16 16:20:36 -06:00
|
|
|
return -ENODEV;
|
|
|
|
|
2006-02-27 22:37:44 -07:00
|
|
|
if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
|
2005-04-16 16:20:36 -06:00
|
|
|
centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
|
|
|
|
|
2007-07-08 15:39:14 -06:00
|
|
|
if (policy->cpu != 0)
|
|
|
|
return -ENODEV;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2007-07-08 15:39:14 -06:00
|
|
|
for (i = 0; i < N_IDS; i++)
|
|
|
|
if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
|
|
|
|
break;
|
2005-08-29 14:54:55 -06:00
|
|
|
|
2007-07-08 15:39:14 -06:00
|
|
|
if (i != N_IDS)
|
2008-07-18 19:11:34 -06:00
|
|
|
per_cpu(centrino_cpu, policy->cpu) = &cpu_ids[i];
|
2005-08-29 14:54:55 -06:00
|
|
|
|
2008-07-18 19:11:34 -06:00
|
|
|
if (!per_cpu(centrino_cpu, policy->cpu)) {
|
2011-03-27 07:04:46 -06:00
|
|
|
pr_debug("found unsupported CPU with "
|
2007-07-08 15:39:14 -06:00
|
|
|
"Enhanced SpeedStep: send /proc/cpuinfo to "
|
|
|
|
MAINTAINER "\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2013-10-15 11:42:52 -06:00
|
|
|
if (centrino_cpu_init_table(policy))
|
2007-07-08 15:39:14 -06:00
|
|
|
return -ENODEV;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/* Check to see if Enhanced SpeedStep is enabled, and try to
|
|
|
|
enable it if not. */
|
|
|
|
rdmsr(MSR_IA32_MISC_ENABLE, l, h);
|
|
|
|
|
2009-02-20 03:56:38 -07:00
|
|
|
if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
|
|
|
|
l |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
|
2011-03-27 07:04:46 -06:00
|
|
|
pr_debug("trying to enable Enhanced SpeedStep (%x)\n", l);
|
2005-04-16 16:20:36 -06:00
|
|
|
wrmsr(MSR_IA32_MISC_ENABLE, l, h);
|
|
|
|
|
|
|
|
/* check to see if it stuck */
|
|
|
|
rdmsr(MSR_IA32_MISC_ENABLE, l, h);
|
2009-02-20 03:56:38 -07:00
|
|
|
if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
|
2016-04-05 14:28:24 -06:00
|
|
|
pr_info(PFX "couldn't enable Enhanced SpeedStep\n");
|
2005-04-16 16:20:36 -06:00
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-07-18 19:11:34 -06:00
|
|
|
policy->cpuinfo.transition_latency = 10000;
|
|
|
|
/* 10uS transition latency */
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2013-09-16 07:26:38 -06:00
|
|
|
return cpufreq_table_validate_and_show(policy,
|
2008-07-18 19:11:34 -06:00
|
|
|
per_cpu(centrino_model, policy->cpu)->op_points);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static int centrino_cpu_exit(struct cpufreq_policy *policy)
|
|
|
|
{
|
|
|
|
unsigned int cpu = policy->cpu;
|
|
|
|
|
2008-07-18 19:11:34 -06:00
|
|
|
if (!per_cpu(centrino_model, cpu))
|
2005-04-16 16:20:36 -06:00
|
|
|
return -ENODEV;
|
|
|
|
|
2008-07-18 19:11:34 -06:00
|
|
|
per_cpu(centrino_model, cpu) = NULL;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* centrino_setpolicy - set a new CPUFreq policy
|
|
|
|
* @policy: new policy
|
2013-10-25 08:15:48 -06:00
|
|
|
* @index: index of target frequency
|
2005-04-16 16:20:36 -06:00
|
|
|
*
|
|
|
|
* Sets a new CPUFreq policy.
|
|
|
|
*/
|
2013-10-25 08:15:48 -06:00
|
|
|
static int centrino_target(struct cpufreq_policy *policy, unsigned int index)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
2005-12-14 13:05:00 -07:00
|
|
|
unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu;
|
|
|
|
int retval = 0;
|
2013-08-14 08:08:24 -06:00
|
|
|
unsigned int j, first_cpu;
|
2013-10-25 08:15:48 -06:00
|
|
|
struct cpufreq_frequency_table *op_points;
|
2009-06-11 07:29:58 -06:00
|
|
|
cpumask_var_t covered_cpus;
|
2008-07-15 15:14:37 -06:00
|
|
|
|
2009-06-11 07:29:58 -06:00
|
|
|
if (unlikely(!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL)))
|
2009-01-04 06:18:05 -07:00
|
|
|
return -ENOMEM;
|
2008-07-15 15:14:37 -06:00
|
|
|
|
2008-07-18 19:11:34 -06:00
|
|
|
if (unlikely(per_cpu(centrino_model, cpu) == NULL)) {
|
2008-07-15 15:14:37 -06:00
|
|
|
retval = -ENODEV;
|
|
|
|
goto out;
|
|
|
|
}
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2005-12-14 13:05:00 -07:00
|
|
|
first_cpu = 1;
|
2013-10-25 08:15:48 -06:00
|
|
|
op_points = &per_cpu(centrino_model, cpu)->op_points[index];
|
2009-01-04 06:18:06 -07:00
|
|
|
for_each_cpu(j, policy->cpus) {
|
2009-06-11 07:29:58 -06:00
|
|
|
int good_cpu;
|
2008-11-21 03:37:16 -07:00
|
|
|
|
2005-12-14 13:05:00 -07:00
|
|
|
/*
|
|
|
|
* Support for SMP systems.
|
|
|
|
* Make sure we are running on CPU that wants to change freq
|
|
|
|
*/
|
|
|
|
if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
|
2009-06-11 07:29:58 -06:00
|
|
|
good_cpu = cpumask_any_and(policy->cpus,
|
|
|
|
cpu_online_mask);
|
2005-12-14 13:05:00 -07:00
|
|
|
else
|
2009-06-11 07:29:58 -06:00
|
|
|
good_cpu = j;
|
2005-12-14 13:05:00 -07:00
|
|
|
|
2009-06-11 07:29:58 -06:00
|
|
|
if (good_cpu >= nr_cpu_ids) {
|
2011-03-27 07:04:46 -06:00
|
|
|
pr_debug("couldn't limit to CPUs in this domain\n");
|
2005-12-14 13:05:00 -07:00
|
|
|
retval = -EAGAIN;
|
|
|
|
if (first_cpu) {
|
|
|
|
/* We haven't started the transition yet. */
|
2009-06-11 07:29:58 -06:00
|
|
|
goto out;
|
2005-12-14 13:05:00 -07:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2013-10-25 08:15:48 -06:00
|
|
|
msr = op_points->driver_data;
|
2005-12-14 13:05:00 -07:00
|
|
|
|
|
|
|
if (first_cpu) {
|
2009-06-11 07:29:58 -06:00
|
|
|
rdmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, &oldmsr, &h);
|
2005-12-14 13:05:00 -07:00
|
|
|
if (msr == (oldmsr & 0xffff)) {
|
2011-03-27 07:04:46 -06:00
|
|
|
pr_debug("no change needed - msr was and needs "
|
2005-12-14 13:05:00 -07:00
|
|
|
"to be %x\n", oldmsr);
|
|
|
|
retval = 0;
|
2009-06-11 07:29:58 -06:00
|
|
|
goto out;
|
2005-12-14 13:05:00 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
first_cpu = 0;
|
|
|
|
/* all but 16 LSB are reserved, treat them with care */
|
|
|
|
oldmsr &= ~0xffff;
|
|
|
|
msr &= 0xffff;
|
|
|
|
oldmsr |= msr;
|
|
|
|
}
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2009-06-11 07:29:58 -06:00
|
|
|
wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr, h);
|
|
|
|
if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
|
2005-12-14 13:05:00 -07:00
|
|
|
break;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2009-06-11 07:29:58 -06:00
|
|
|
cpumask_set_cpu(j, covered_cpus);
|
2005-12-14 13:05:00 -07:00
|
|
|
}
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2005-12-14 13:05:00 -07:00
|
|
|
if (unlikely(retval)) {
|
|
|
|
/*
|
|
|
|
* We have failed halfway through the frequency change.
|
|
|
|
* We have sent callbacks to policy->cpus and
|
|
|
|
* MSRs have already been written on coverd_cpus.
|
|
|
|
* Best effort undo..
|
|
|
|
*/
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2009-06-11 07:29:58 -06:00
|
|
|
for_each_cpu(j, covered_cpus)
|
|
|
|
wrmsr_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr, h);
|
2005-12-14 13:05:00 -07:00
|
|
|
}
|
2008-07-15 15:14:37 -06:00
|
|
|
retval = 0;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2008-07-15 15:14:37 -06:00
|
|
|
out:
|
2009-01-04 06:18:05 -07:00
|
|
|
free_cpumask_var(covered_cpus);
|
2008-07-15 15:14:37 -06:00
|
|
|
return retval;
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct cpufreq_driver centrino_driver = {
|
|
|
|
.name = "centrino", /* should be speedstep-centrino,
|
|
|
|
but there's a 16 char limit */
|
|
|
|
.init = centrino_cpu_init,
|
|
|
|
.exit = centrino_cpu_exit,
|
2013-10-03 08:58:28 -06:00
|
|
|
.verify = cpufreq_generic_frequency_table_verify,
|
2013-10-25 08:15:48 -06:00
|
|
|
.target_index = centrino_target,
|
2005-04-16 16:20:36 -06:00
|
|
|
.get = get_cur_freq,
|
2013-10-03 08:58:28 -06:00
|
|
|
.attr = cpufreq_generic_attr,
|
2005-04-16 16:20:36 -06:00
|
|
|
};
|
|
|
|
|
2012-01-25 16:09:12 -07:00
|
|
|
/*
|
|
|
|
* This doesn't replace the detailed checks above because
|
|
|
|
* the generic CPU IDs don't have a way to match for steppings
|
|
|
|
* or ASCII model IDs.
|
|
|
|
*/
|
|
|
|
static const struct x86_cpu_id centrino_ids[] = {
|
|
|
|
{ X86_VENDOR_INTEL, 6, 9, X86_FEATURE_EST },
|
|
|
|
{ X86_VENDOR_INTEL, 6, 13, X86_FEATURE_EST },
|
|
|
|
{ X86_VENDOR_INTEL, 6, 13, X86_FEATURE_EST },
|
|
|
|
{ X86_VENDOR_INTEL, 6, 13, X86_FEATURE_EST },
|
|
|
|
{ X86_VENDOR_INTEL, 15, 3, X86_FEATURE_EST },
|
|
|
|
{ X86_VENDOR_INTEL, 15, 4, X86_FEATURE_EST },
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
#if 0
|
|
|
|
/* Autoload or not? Do not for now. */
|
|
|
|
MODULE_DEVICE_TABLE(x86cpu, centrino_ids);
|
|
|
|
#endif
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/**
|
|
|
|
* centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
|
|
|
|
*
|
|
|
|
* Initializes the Enhanced SpeedStep support. Returns -ENODEV on
|
|
|
|
* unsupported devices, -ENOENT if there's no voltage table for this
|
|
|
|
* particular CPU model, -EINVAL on problems during initiatization,
|
|
|
|
* and zero on success.
|
|
|
|
*
|
|
|
|
* This is quite picky. Not only does the CPU have to advertise the
|
|
|
|
* "est" flag in the cpuid capability flags, we look for a specific
|
|
|
|
* CPU model and stepping, and we need to have the exact model name in
|
|
|
|
* our voltage tables. That is, be paranoid about not releasing
|
|
|
|
* someone's valuable magic smoke.
|
|
|
|
*/
|
|
|
|
static int __init centrino_init(void)
|
|
|
|
{
|
2012-01-25 16:09:12 -07:00
|
|
|
if (!x86_match_cpu(centrino_ids))
|
2005-04-16 16:20:36 -06:00
|
|
|
return -ENODEV;
|
|
|
|
return cpufreq_register_driver(¢rino_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit centrino_exit(void)
|
|
|
|
{
|
|
|
|
cpufreq_unregister_driver(¢rino_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
|
|
|
|
MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
|
|
|
|
MODULE_LICENSE ("GPL");
|
|
|
|
|
|
|
|
late_initcall(centrino_init);
|
|
|
|
module_exit(centrino_exit);
|