pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
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/*
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* PCIe driver for Marvell Armada 370 and Armada XP SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/clk.h>
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2013-08-13 06:25:23 -06:00
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#include <linux/delay.h>
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#include <linux/gpio.h>
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pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
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#include <linux/module.h>
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#include <linux/mbus.h>
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2013-08-09 14:27:14 -06:00
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#include <linux/msi.h>
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pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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2013-08-13 06:25:23 -06:00
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#include <linux/of_gpio.h>
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#include <linux/of_pci.h>
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pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
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#include <linux/of_platform.h>
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/*
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* PCIe unit register offsets.
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*/
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#define PCIE_DEV_ID_OFF 0x0000
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#define PCIE_CMD_OFF 0x0004
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#define PCIE_DEV_REV_OFF 0x0008
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#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
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#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
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#define PCIE_HEADER_LOG_4_OFF 0x0128
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#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
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#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
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#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
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#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
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#define PCIE_WIN5_CTRL_OFF 0x1880
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#define PCIE_WIN5_BASE_OFF 0x1884
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#define PCIE_WIN5_REMAP_OFF 0x188c
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#define PCIE_CONF_ADDR_OFF 0x18f8
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#define PCIE_CONF_ADDR_EN 0x80000000
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#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
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#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
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#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
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#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
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#define PCIE_CONF_ADDR(bus, devfn, where) \
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(PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
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PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
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PCIE_CONF_ADDR_EN)
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#define PCIE_CONF_DATA_OFF 0x18fc
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#define PCIE_MASK_OFF 0x1910
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#define PCIE_MASK_ENABLE_INTS 0x0f000000
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#define PCIE_CTRL_OFF 0x1a00
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#define PCIE_CTRL_X1_MODE 0x0001
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#define PCIE_STAT_OFF 0x1a04
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#define PCIE_STAT_BUS 0xff00
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pci: mvebu: no longer fake the slot location of downstream devices
By default, the Marvell hardware, for each PCIe interface, exhibits
the following devices:
* On slot 0, a "Marvell Memory controller", identical on all PCIe
interfaces, and which isn't useful when the Marvell SoC is the PCIe
root complex (i.e, the normal case when we run Linux on the Marvell
SoC).
* On slot 1, the real PCIe card connected into the PCIe slot of the
board.
So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge
emulation is that when the Linux PCI core was trying to access the
device in slot 0, we were in fact forwarding the configuration
transaction to the device in slot 1. For all other slots, we were
telling the Linux PCI core that there was no device connected.
However, new versions of bootloaders from Marvell change the default
PCIe configuration, and make the real device appear in slot 0, and the
"Marvell Memory controller" in slot 1.
Therefore, this commit modifies the Marvell PCIe driver to adjust the
PCIe hardware configuration to make sure that this behavior (real
device in slot 0, "Marvell Memory controller" in slot 1) is the one
we'll see regardless of what the bootloader has done. It allows to
remove the little hack that was forwarding configuration transactions
on slot 0 to slot 1, which is nice.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 08:32:51 -06:00
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#define PCIE_STAT_DEV 0x1f0000
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pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
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#define PCIE_STAT_LINK_DOWN BIT(0)
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#define PCIE_DEBUG_CTRL 0x1a60
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#define PCIE_DEBUG_SOFT_RESET BIT(20)
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/* PCI configuration space of a PCI-to-PCI bridge */
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struct mvebu_sw_pci_bridge {
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u16 vendor;
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u16 device;
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u16 command;
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u16 class;
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u8 interface;
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u8 revision;
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u8 bist;
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u8 header_type;
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u8 latency_timer;
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u8 cache_line_size;
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u32 bar[2];
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u8 primary_bus;
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u8 secondary_bus;
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u8 subordinate_bus;
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u8 secondary_latency_timer;
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u8 iobase;
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u8 iolimit;
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u16 secondary_status;
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u16 membase;
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u16 memlimit;
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u16 iobaseupper;
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u16 iolimitupper;
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u8 cappointer;
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u8 reserved1;
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u16 reserved2;
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u32 romaddr;
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u8 intline;
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u8 intpin;
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u16 bridgectrl;
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};
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struct mvebu_pcie_port;
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/* Structure representing all PCIe interfaces */
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struct mvebu_pcie {
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struct platform_device *pdev;
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struct mvebu_pcie_port *ports;
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2013-08-09 14:27:14 -06:00
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struct msi_chip *msi;
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pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
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struct resource io;
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2014-02-12 15:57:08 -07:00
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char io_name[30];
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pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
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struct resource realio;
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2014-02-12 15:57:08 -07:00
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char mem_name[30];
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pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
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struct resource mem;
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struct resource busn;
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int nports;
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};
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/* Structure representing one PCIe interface */
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struct mvebu_pcie_port {
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char *name;
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void __iomem *base;
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spinlock_t conf_lock;
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u32 port;
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u32 lane;
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int devfn;
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2013-07-26 07:17:48 -06:00
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unsigned int mem_target;
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unsigned int mem_attr;
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unsigned int io_target;
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unsigned int io_attr;
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pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
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struct clk *clk;
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2013-08-13 06:25:23 -06:00
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int reset_gpio;
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int reset_active_low;
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char *reset_name;
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pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
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struct mvebu_sw_pci_bridge bridge;
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struct device_node *dn;
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struct mvebu_pcie *pcie;
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phys_addr_t memwin_base;
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size_t memwin_size;
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phys_addr_t iowin_base;
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size_t iowin_size;
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};
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2013-10-04 03:58:15 -06:00
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static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
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{
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writel(val, port->base + reg);
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}
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static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
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{
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return readl(port->base + reg);
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}
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2013-11-26 11:02:55 -07:00
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static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)
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{
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return port->io_target != -1 && port->io_attr != -1;
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}
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pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
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static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
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{
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2013-10-04 03:58:15 -06:00
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return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
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pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
|
|
|
|
{
|
|
|
|
u32 stat;
|
|
|
|
|
2013-10-04 03:58:15 -06:00
|
|
|
stat = mvebu_readl(port, PCIE_STAT_OFF);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
stat &= ~PCIE_STAT_BUS;
|
|
|
|
stat |= nr << 8;
|
2013-10-04 03:58:15 -06:00
|
|
|
mvebu_writel(port, stat, PCIE_STAT_OFF);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
}
|
|
|
|
|
pci: mvebu: no longer fake the slot location of downstream devices
By default, the Marvell hardware, for each PCIe interface, exhibits
the following devices:
* On slot 0, a "Marvell Memory controller", identical on all PCIe
interfaces, and which isn't useful when the Marvell SoC is the PCIe
root complex (i.e, the normal case when we run Linux on the Marvell
SoC).
* On slot 1, the real PCIe card connected into the PCIe slot of the
board.
So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge
emulation is that when the Linux PCI core was trying to access the
device in slot 0, we were in fact forwarding the configuration
transaction to the device in slot 1. For all other slots, we were
telling the Linux PCI core that there was no device connected.
However, new versions of bootloaders from Marvell change the default
PCIe configuration, and make the real device appear in slot 0, and the
"Marvell Memory controller" in slot 1.
Therefore, this commit modifies the Marvell PCIe driver to adjust the
PCIe hardware configuration to make sure that this behavior (real
device in slot 0, "Marvell Memory controller" in slot 1) is the one
we'll see regardless of what the bootloader has done. It allows to
remove the little hack that was forwarding configuration transactions
on slot 0 to slot 1, which is nice.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 08:32:51 -06:00
|
|
|
static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
|
|
|
|
{
|
|
|
|
u32 stat;
|
|
|
|
|
2013-10-04 03:58:15 -06:00
|
|
|
stat = mvebu_readl(port, PCIE_STAT_OFF);
|
pci: mvebu: no longer fake the slot location of downstream devices
By default, the Marvell hardware, for each PCIe interface, exhibits
the following devices:
* On slot 0, a "Marvell Memory controller", identical on all PCIe
interfaces, and which isn't useful when the Marvell SoC is the PCIe
root complex (i.e, the normal case when we run Linux on the Marvell
SoC).
* On slot 1, the real PCIe card connected into the PCIe slot of the
board.
So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge
emulation is that when the Linux PCI core was trying to access the
device in slot 0, we were in fact forwarding the configuration
transaction to the device in slot 1. For all other slots, we were
telling the Linux PCI core that there was no device connected.
However, new versions of bootloaders from Marvell change the default
PCIe configuration, and make the real device appear in slot 0, and the
"Marvell Memory controller" in slot 1.
Therefore, this commit modifies the Marvell PCIe driver to adjust the
PCIe hardware configuration to make sure that this behavior (real
device in slot 0, "Marvell Memory controller" in slot 1) is the one
we'll see regardless of what the bootloader has done. It allows to
remove the little hack that was forwarding configuration transactions
on slot 0 to slot 1, which is nice.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 08:32:51 -06:00
|
|
|
stat &= ~PCIE_STAT_DEV;
|
|
|
|
stat |= nr << 16;
|
2013-10-04 03:58:15 -06:00
|
|
|
mvebu_writel(port, stat, PCIE_STAT_OFF);
|
pci: mvebu: no longer fake the slot location of downstream devices
By default, the Marvell hardware, for each PCIe interface, exhibits
the following devices:
* On slot 0, a "Marvell Memory controller", identical on all PCIe
interfaces, and which isn't useful when the Marvell SoC is the PCIe
root complex (i.e, the normal case when we run Linux on the Marvell
SoC).
* On slot 1, the real PCIe card connected into the PCIe slot of the
board.
So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge
emulation is that when the Linux PCI core was trying to access the
device in slot 0, we were in fact forwarding the configuration
transaction to the device in slot 1. For all other slots, we were
telling the Linux PCI core that there was no device connected.
However, new versions of bootloaders from Marvell change the default
PCIe configuration, and make the real device appear in slot 0, and the
"Marvell Memory controller" in slot 1.
Therefore, this commit modifies the Marvell PCIe driver to adjust the
PCIe hardware configuration to make sure that this behavior (real
device in slot 0, "Marvell Memory controller" in slot 1) is the one
we'll see regardless of what the bootloader has done. It allows to
remove the little hack that was forwarding configuration transactions
on slot 0 to slot 1, which is nice.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 08:32:51 -06:00
|
|
|
}
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
/*
|
|
|
|
* Setup PCIE BARs and Address Decode Wins:
|
|
|
|
* BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
|
|
|
|
* WIN[0-3] -> DRAM bank[0-3]
|
|
|
|
*/
|
2013-08-13 06:25:22 -06:00
|
|
|
static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
{
|
|
|
|
const struct mbus_dram_target_info *dram;
|
|
|
|
u32 size;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
dram = mv_mbus_dram_info();
|
|
|
|
|
|
|
|
/* First, disable and clear BARs and windows. */
|
|
|
|
for (i = 1; i < 3; i++) {
|
2013-10-04 03:58:15 -06:00
|
|
|
mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
|
|
|
|
mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
|
|
|
|
mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < 5; i++) {
|
2013-10-04 03:58:15 -06:00
|
|
|
mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
|
|
|
|
mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
|
|
|
|
mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
}
|
|
|
|
|
2013-10-04 03:58:15 -06:00
|
|
|
mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
|
|
|
|
mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
|
|
|
|
mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
|
|
|
/* Setup windows for DDR banks. Count total DDR size on the fly. */
|
|
|
|
size = 0;
|
|
|
|
for (i = 0; i < dram->num_cs; i++) {
|
|
|
|
const struct mbus_dram_window *cs = dram->cs + i;
|
|
|
|
|
2013-10-04 03:58:15 -06:00
|
|
|
mvebu_writel(port, cs->base & 0xffff0000,
|
|
|
|
PCIE_WIN04_BASE_OFF(i));
|
|
|
|
mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
|
|
|
|
mvebu_writel(port,
|
|
|
|
((cs->size - 1) & 0xffff0000) |
|
|
|
|
(cs->mbus_attr << 8) |
|
|
|
|
(dram->mbus_dram_target_id << 4) | 1,
|
|
|
|
PCIE_WIN04_CTRL_OFF(i));
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
|
|
|
size += cs->size;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Round up 'size' to the nearest power of two. */
|
|
|
|
if ((size & (size - 1)) != 0)
|
|
|
|
size = 1 << fls(size);
|
|
|
|
|
|
|
|
/* Setup BAR[1] to all DRAM banks. */
|
2013-10-04 03:58:15 -06:00
|
|
|
mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
|
|
|
|
mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
|
|
|
|
mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
|
|
|
|
PCIE_BAR_CTRL_OFF(1));
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
}
|
|
|
|
|
2013-08-13 06:25:22 -06:00
|
|
|
static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
{
|
2013-10-04 03:58:15 -06:00
|
|
|
u32 cmd, mask;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
|
|
|
/* Point PCIe unit MBUS decode windows to DRAM space. */
|
|
|
|
mvebu_pcie_setup_wins(port);
|
|
|
|
|
|
|
|
/* Master + slave enable. */
|
2013-10-04 03:58:15 -06:00
|
|
|
cmd = mvebu_readl(port, PCIE_CMD_OFF);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
cmd |= PCI_COMMAND_IO;
|
|
|
|
cmd |= PCI_COMMAND_MEMORY;
|
|
|
|
cmd |= PCI_COMMAND_MASTER;
|
2013-10-04 03:58:15 -06:00
|
|
|
mvebu_writel(port, cmd, PCIE_CMD_OFF);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
|
|
|
/* Enable interrupt lines A-D. */
|
2013-10-04 03:58:15 -06:00
|
|
|
mask = mvebu_readl(port, PCIE_MASK_OFF);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
mask |= PCIE_MASK_ENABLE_INTS;
|
2013-10-04 03:58:15 -06:00
|
|
|
mvebu_writel(port, mask, PCIE_MASK_OFF);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
|
|
|
|
struct pci_bus *bus,
|
|
|
|
u32 devfn, int where, int size, u32 *val)
|
|
|
|
{
|
2013-10-04 03:58:15 -06:00
|
|
|
mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
|
|
|
|
PCIE_CONF_ADDR_OFF);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
2013-10-04 03:58:15 -06:00
|
|
|
*val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
|
|
|
if (size == 1)
|
|
|
|
*val = (*val >> (8 * (where & 3))) & 0xff;
|
|
|
|
else if (size == 2)
|
|
|
|
*val = (*val >> (8 * (where & 3))) & 0xffff;
|
|
|
|
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
|
|
|
|
struct pci_bus *bus,
|
|
|
|
u32 devfn, int where, int size, u32 val)
|
|
|
|
{
|
2013-10-04 03:58:15 -06:00
|
|
|
u32 _val, shift = 8 * (where & 3);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
2013-10-04 03:58:15 -06:00
|
|
|
mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
|
|
|
|
PCIE_CONF_ADDR_OFF);
|
|
|
|
_val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
|
|
|
if (size == 4)
|
2013-10-04 03:58:15 -06:00
|
|
|
_val = val;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
else if (size == 2)
|
2013-10-04 03:58:15 -06:00
|
|
|
_val = (_val & ~(0xffff << shift)) | ((val & 0xffff) << shift);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
else if (size == 1)
|
2013-10-04 03:58:15 -06:00
|
|
|
_val = (_val & ~(0xff << shift)) | ((val & 0xff) << shift);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
else
|
2013-10-04 03:58:15 -06:00
|
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
2013-10-04 03:58:15 -06:00
|
|
|
mvebu_writel(port, _val, PCIE_CONF_DATA_OFF);
|
|
|
|
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
}
|
|
|
|
|
2014-04-18 06:19:53 -06:00
|
|
|
/*
|
|
|
|
* Remove windows, starting from the largest ones to the smallest
|
|
|
|
* ones.
|
|
|
|
*/
|
|
|
|
static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,
|
|
|
|
phys_addr_t base, size_t size)
|
|
|
|
{
|
|
|
|
while (size) {
|
|
|
|
size_t sz = 1 << (fls(size) - 1);
|
|
|
|
|
|
|
|
mvebu_mbus_del_window(base, sz);
|
|
|
|
base += sz;
|
|
|
|
size -= sz;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* MBus windows can only have a power of two size, but PCI BARs do not
|
|
|
|
* have this constraint. Therefore, we have to split the PCI BAR into
|
|
|
|
* areas each having a power of two size. We start from the largest
|
|
|
|
* one (i.e highest order bit set in the size).
|
|
|
|
*/
|
|
|
|
static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
|
|
|
|
unsigned int target, unsigned int attribute,
|
|
|
|
phys_addr_t base, size_t size,
|
|
|
|
phys_addr_t remap)
|
|
|
|
{
|
|
|
|
size_t size_mapped = 0;
|
|
|
|
|
|
|
|
while (size) {
|
|
|
|
size_t sz = 1 << (fls(size) - 1);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base,
|
|
|
|
sz, remap);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&port->pcie->pdev->dev,
|
|
|
|
"Could not create MBus window at 0x%x, size 0x%x: %d\n",
|
|
|
|
base, sz, ret);
|
|
|
|
mvebu_pcie_del_windows(port, base - size_mapped,
|
|
|
|
size_mapped);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
size -= sz;
|
|
|
|
size_mapped += sz;
|
|
|
|
base += sz;
|
|
|
|
if (remap != MVEBU_MBUS_NO_REMAP)
|
|
|
|
remap += sz;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
|
|
|
|
{
|
|
|
|
phys_addr_t iobase;
|
|
|
|
|
|
|
|
/* Are the new iobase/iolimit values invalid? */
|
|
|
|
if (port->bridge.iolimit < port->bridge.iobase ||
|
2013-11-26 11:02:54 -07:00
|
|
|
port->bridge.iolimitupper < port->bridge.iobaseupper ||
|
|
|
|
!(port->bridge.command & PCI_COMMAND_IO)) {
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
|
|
|
/* If a window was configured, remove it */
|
|
|
|
if (port->iowin_base) {
|
2014-04-18 06:19:53 -06:00
|
|
|
mvebu_pcie_del_windows(port, port->iowin_base,
|
|
|
|
port->iowin_size);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
port->iowin_base = 0;
|
|
|
|
port->iowin_size = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-11-26 11:02:55 -07:00
|
|
|
if (!mvebu_has_ioport(port)) {
|
|
|
|
dev_WARN(&port->pcie->pdev->dev,
|
|
|
|
"Attempt to set IO when IO is disabled\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
/*
|
|
|
|
* We read the PCI-to-PCI bridge emulated registers, and
|
|
|
|
* calculate the base address and size of the address decoding
|
|
|
|
* window to setup, according to the PCI-to-PCI bridge
|
|
|
|
* specifications. iobase is the bus address, port->iowin_base
|
|
|
|
* is the CPU address.
|
|
|
|
*/
|
|
|
|
iobase = ((port->bridge.iobase & 0xF0) << 8) |
|
|
|
|
(port->bridge.iobaseupper << 16);
|
|
|
|
port->iowin_base = port->pcie->io.start + iobase;
|
|
|
|
port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
|
|
|
|
(port->bridge.iolimitupper << 16)) -
|
2014-04-18 06:19:50 -06:00
|
|
|
iobase) + 1;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
2014-04-18 06:19:53 -06:00
|
|
|
mvebu_pcie_add_windows(port, port->io_target, port->io_attr,
|
|
|
|
port->iowin_base, port->iowin_size,
|
|
|
|
iobase);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
|
|
|
|
{
|
|
|
|
/* Are the new membase/memlimit values invalid? */
|
2013-11-26 11:02:54 -07:00
|
|
|
if (port->bridge.memlimit < port->bridge.membase ||
|
|
|
|
!(port->bridge.command & PCI_COMMAND_MEMORY)) {
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
|
|
|
/* If a window was configured, remove it */
|
|
|
|
if (port->memwin_base) {
|
2014-04-18 06:19:53 -06:00
|
|
|
mvebu_pcie_del_windows(port, port->memwin_base,
|
|
|
|
port->memwin_size);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
port->memwin_base = 0;
|
|
|
|
port->memwin_size = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We read the PCI-to-PCI bridge emulated registers, and
|
|
|
|
* calculate the base address and size of the address decoding
|
|
|
|
* window to setup, according to the PCI-to-PCI bridge
|
|
|
|
* specifications.
|
|
|
|
*/
|
|
|
|
port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
|
|
|
|
port->memwin_size =
|
|
|
|
(((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
|
2014-04-18 06:19:50 -06:00
|
|
|
port->memwin_base + 1;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
2014-04-18 06:19:53 -06:00
|
|
|
mvebu_pcie_add_windows(port, port->mem_target, port->mem_attr,
|
|
|
|
port->memwin_base, port->memwin_size,
|
|
|
|
MVEBU_MBUS_NO_REMAP);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize the configuration space of the PCI-to-PCI bridge
|
|
|
|
* associated with the given PCIe interface.
|
|
|
|
*/
|
|
|
|
static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
|
|
|
|
{
|
|
|
|
struct mvebu_sw_pci_bridge *bridge = &port->bridge;
|
|
|
|
|
|
|
|
memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
|
|
|
|
|
|
|
|
bridge->class = PCI_CLASS_BRIDGE_PCI;
|
|
|
|
bridge->vendor = PCI_VENDOR_ID_MARVELL;
|
2014-02-05 03:55:49 -07:00
|
|
|
bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
|
|
|
|
bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
|
|
|
|
bridge->cache_line_size = 0x10;
|
|
|
|
|
|
|
|
/* We support 32 bits I/O addressing */
|
|
|
|
bridge->iobase = PCI_IO_RANGE_TYPE_32;
|
|
|
|
bridge->iolimit = PCI_IO_RANGE_TYPE_32;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Read the configuration space of the PCI-to-PCI bridge associated to
|
|
|
|
* the given PCIe interface.
|
|
|
|
*/
|
|
|
|
static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
|
|
|
|
unsigned int where, int size, u32 *value)
|
|
|
|
{
|
|
|
|
struct mvebu_sw_pci_bridge *bridge = &port->bridge;
|
|
|
|
|
|
|
|
switch (where & ~3) {
|
|
|
|
case PCI_VENDOR_ID:
|
|
|
|
*value = bridge->device << 16 | bridge->vendor;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_COMMAND:
|
pci: mvebu: fix the emulation of the status register
The status register of the PCI configuration space of PCI-to-PCI
bridges contain some read-only bits, and so write-1-to-clear bits. So,
the Linux PCI core sometimes writes 0xffff to this status register,
and in the current PCI-to-PCI bridge emulation code of the Marvell
driver, we do take all those 1s being written. Even the read-only bits
are being overwritten.
For now, all the read-only bits should be emulated to have the zero
value.
The other bits, that are write-1-to-clear bits are used to report
various kind of errors, and are never set by the emulated bridge, so
there is no need to support this write-1-to-clear bits mechanism.
As a conclusion, the easiest solution is to simply emulate this status
register by returning zero when read, and ignore the writes to it.
This has two visible effects:
* The devsel is no longer 'unknown' in, i.e
Flags: bus master, 66MHz, user-definable features, ?? devsel, latency 0
becomes:
Flags: bus master, 66MHz, user-definable features, fast devsel, latency 0
in lspci -v.
This was caused by a value of 11b being read for devsel, which is
an invalid value. This 11b value being read was due to a previous
write of 0xffff into the status register.
* The capability list is no longer broken, because we indicate to the
Linux PCI core that we don't have a Capabilities Pointer in the PCI
configuration space of this bridge. The following message is
therefore no longer visible in lspci -v:
Capabilities: [fc] <chain broken>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 08:32:53 -06:00
|
|
|
*value = bridge->command;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_CLASS_REVISION:
|
|
|
|
*value = bridge->class << 16 | bridge->interface << 8 |
|
|
|
|
bridge->revision;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_CACHE_LINE_SIZE:
|
|
|
|
*value = bridge->bist << 24 | bridge->header_type << 16 |
|
|
|
|
bridge->latency_timer << 8 | bridge->cache_line_size;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
|
|
|
|
*value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_PRIMARY_BUS:
|
|
|
|
*value = (bridge->secondary_latency_timer << 24 |
|
|
|
|
bridge->subordinate_bus << 16 |
|
|
|
|
bridge->secondary_bus << 8 |
|
|
|
|
bridge->primary_bus);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_IO_BASE:
|
2013-11-26 11:02:55 -07:00
|
|
|
if (!mvebu_has_ioport(port))
|
|
|
|
*value = bridge->secondary_status << 16;
|
|
|
|
else
|
|
|
|
*value = (bridge->secondary_status << 16 |
|
|
|
|
bridge->iolimit << 8 |
|
|
|
|
bridge->iobase);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_MEMORY_BASE:
|
|
|
|
*value = (bridge->memlimit << 16 | bridge->membase);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_PREF_MEMORY_BASE:
|
2013-08-01 07:44:19 -06:00
|
|
|
*value = 0;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_IO_BASE_UPPER16:
|
|
|
|
*value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_ROM_ADDRESS1:
|
|
|
|
*value = 0;
|
|
|
|
break;
|
|
|
|
|
2013-11-26 11:27:28 -07:00
|
|
|
case PCI_INTERRUPT_LINE:
|
|
|
|
/* LINE PIN MIN_GNT MAX_LAT */
|
|
|
|
*value = 0;
|
|
|
|
break;
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
default:
|
|
|
|
*value = 0xffffffff;
|
|
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (size == 2)
|
|
|
|
*value = (*value >> (8 * (where & 3))) & 0xffff;
|
|
|
|
else if (size == 1)
|
|
|
|
*value = (*value >> (8 * (where & 3))) & 0xff;
|
|
|
|
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Write to the PCI-to-PCI bridge configuration space */
|
|
|
|
static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
|
|
|
|
unsigned int where, int size, u32 value)
|
|
|
|
{
|
|
|
|
struct mvebu_sw_pci_bridge *bridge = &port->bridge;
|
|
|
|
u32 mask, reg;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
if (size == 4)
|
|
|
|
mask = 0x0;
|
|
|
|
else if (size == 2)
|
|
|
|
mask = ~(0xffff << ((where & 3) * 8));
|
|
|
|
else if (size == 1)
|
|
|
|
mask = ~(0xff << ((where & 3) * 8));
|
|
|
|
else
|
|
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
|
|
|
|
|
|
err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
value = (reg & mask) | value << ((where & 3) * 8);
|
|
|
|
|
|
|
|
switch (where & ~3) {
|
|
|
|
case PCI_COMMAND:
|
2013-11-26 11:02:54 -07:00
|
|
|
{
|
|
|
|
u32 old = bridge->command;
|
|
|
|
|
2013-11-26 11:02:55 -07:00
|
|
|
if (!mvebu_has_ioport(port))
|
|
|
|
value &= ~PCI_COMMAND_IO;
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
bridge->command = value & 0xffff;
|
2013-11-26 11:02:54 -07:00
|
|
|
if ((old ^ bridge->command) & PCI_COMMAND_IO)
|
|
|
|
mvebu_pcie_handle_iobase_change(port);
|
|
|
|
if ((old ^ bridge->command) & PCI_COMMAND_MEMORY)
|
|
|
|
mvebu_pcie_handle_membase_change(port);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
break;
|
2013-11-26 11:02:54 -07:00
|
|
|
}
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
|
|
|
case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
|
|
|
|
bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_IO_BASE:
|
|
|
|
/*
|
|
|
|
* We also keep bit 1 set, it is a read-only bit that
|
|
|
|
* indicates we support 32 bits addressing for the
|
|
|
|
* I/O
|
|
|
|
*/
|
|
|
|
bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
|
|
|
|
bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
|
|
|
|
mvebu_pcie_handle_iobase_change(port);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_MEMORY_BASE:
|
|
|
|
bridge->membase = value & 0xffff;
|
|
|
|
bridge->memlimit = value >> 16;
|
|
|
|
mvebu_pcie_handle_membase_change(port);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_IO_BASE_UPPER16:
|
|
|
|
bridge->iobaseupper = value & 0xffff;
|
|
|
|
bridge->iolimitupper = value >> 16;
|
|
|
|
mvebu_pcie_handle_iobase_change(port);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PCI_PRIMARY_BUS:
|
|
|
|
bridge->primary_bus = value & 0xff;
|
|
|
|
bridge->secondary_bus = (value >> 8) & 0xff;
|
|
|
|
bridge->subordinate_bus = (value >> 16) & 0xff;
|
|
|
|
bridge->secondary_latency_timer = (value >> 24) & 0xff;
|
|
|
|
mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return PCIBIOS_SUCCESSFUL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
|
|
|
|
{
|
|
|
|
return sys->private_data;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct mvebu_pcie_port *
|
|
|
|
mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
|
|
|
|
int devfn)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < pcie->nports; i++) {
|
|
|
|
struct mvebu_pcie_port *port = &pcie->ports[i];
|
|
|
|
if (bus->number == 0 && port->devfn == devfn)
|
|
|
|
return port;
|
|
|
|
if (bus->number != 0 &&
|
pci: mvebu: allow the enumeration of devices beyond physical bridges
Until now, the Marvell PCIe driver was only allowing the enumeration
of the devices in the secondary bus of the emulated PCI-to-PCI
bridge. This works fine when a PCIe device is directly connected into
a PCIe slot of the Marvell board.
However, when the device connected in the PCIe slot is a physical PCIe
bridge, beyond which a real PCIe device is connected, it no longer
worked, as the driver was preventing the Linux PCI core from seeing
such devices.
This commit fixes that by ensuring that configuration transactions on
subordinate busses are properly forwarded on the right PCIe interface.
Thanks to this patch, a PCIe card beyond a PCIe bridge, itself beyond
the emulated PCI-to-PCI bridge is properly detected, with the
following layout:
-[0000:00]-+-01.0-[01]----00.0
+-09.0-[02-07]----00.0-[03-07]--+-01.0-[04]--
| +-05.0-[05]--
| +-07.0-[06]--
| \-09.0-[07]----00.0
\-0a.0-[08]----00.0
Where the PCIe interface that sits beyond the emulated PCI-to-PCI
bridge at 09.0 allows to access the secondary bus 02, on which there
is a PCIe bridge that allows to access the 3 to 7 busses, that are
subordinates to this bridge. And on one of this bus (bus 7), there is
one real PCIe device connected.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 08:32:52 -06:00
|
|
|
bus->number >= port->bridge.secondary_bus &&
|
|
|
|
bus->number <= port->bridge.subordinate_bus)
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
return port;
|
|
|
|
}
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* PCI configuration space write function */
|
|
|
|
static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
|
|
|
|
int where, int size, u32 val)
|
|
|
|
{
|
|
|
|
struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
|
|
|
|
struct mvebu_pcie_port *port;
|
|
|
|
unsigned long flags;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
port = mvebu_pcie_find_port(pcie, bus, devfn);
|
|
|
|
if (!port)
|
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
|
|
|
|
/* Access the emulated PCI-to-PCI bridge */
|
|
|
|
if (bus->number == 0)
|
|
|
|
return mvebu_sw_pci_bridge_write(port, where, size, val);
|
|
|
|
|
2013-10-01 11:58:00 -06:00
|
|
|
if (!mvebu_pcie_link_up(port))
|
pci: mvebu: allow the enumeration of devices beyond physical bridges
Until now, the Marvell PCIe driver was only allowing the enumeration
of the devices in the secondary bus of the emulated PCI-to-PCI
bridge. This works fine when a PCIe device is directly connected into
a PCIe slot of the Marvell board.
However, when the device connected in the PCIe slot is a physical PCIe
bridge, beyond which a real PCIe device is connected, it no longer
worked, as the driver was preventing the Linux PCI core from seeing
such devices.
This commit fixes that by ensuring that configuration transactions on
subordinate busses are properly forwarded on the right PCIe interface.
Thanks to this patch, a PCIe card beyond a PCIe bridge, itself beyond
the emulated PCI-to-PCI bridge is properly detected, with the
following layout:
-[0000:00]-+-01.0-[01]----00.0
+-09.0-[02-07]----00.0-[03-07]--+-01.0-[04]--
| +-05.0-[05]--
| +-07.0-[06]--
| \-09.0-[07]----00.0
\-0a.0-[08]----00.0
Where the PCIe interface that sits beyond the emulated PCI-to-PCI
bridge at 09.0 allows to access the secondary bus 02, on which there
is a PCIe bridge that allows to access the 3 to 7 busses, that are
subordinates to this bridge. And on one of this bus (bus 7), there is
one real PCIe device connected.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 08:32:52 -06:00
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* On the secondary bus, we don't want to expose any other
|
|
|
|
* device than the device physically connected in the PCIe
|
|
|
|
* slot, visible in slot 0. In slot 1, there's a special
|
|
|
|
* Marvell device that only makes sense when the Armada is
|
|
|
|
* used as a PCIe endpoint.
|
|
|
|
*/
|
|
|
|
if (bus->number == port->bridge.secondary_bus &&
|
|
|
|
PCI_SLOT(devfn) != 0)
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
|
|
|
|
/* Access the real PCIe interface */
|
|
|
|
spin_lock_irqsave(&port->conf_lock, flags);
|
pci: mvebu: no longer fake the slot location of downstream devices
By default, the Marvell hardware, for each PCIe interface, exhibits
the following devices:
* On slot 0, a "Marvell Memory controller", identical on all PCIe
interfaces, and which isn't useful when the Marvell SoC is the PCIe
root complex (i.e, the normal case when we run Linux on the Marvell
SoC).
* On slot 1, the real PCIe card connected into the PCIe slot of the
board.
So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge
emulation is that when the Linux PCI core was trying to access the
device in slot 0, we were in fact forwarding the configuration
transaction to the device in slot 1. For all other slots, we were
telling the Linux PCI core that there was no device connected.
However, new versions of bootloaders from Marvell change the default
PCIe configuration, and make the real device appear in slot 0, and the
"Marvell Memory controller" in slot 1.
Therefore, this commit modifies the Marvell PCIe driver to adjust the
PCIe hardware configuration to make sure that this behavior (real
device in slot 0, "Marvell Memory controller" in slot 1) is the one
we'll see regardless of what the bootloader has done. It allows to
remove the little hack that was forwarding configuration transactions
on slot 0 to slot 1, which is nice.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 08:32:51 -06:00
|
|
|
ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
where, size, val);
|
|
|
|
spin_unlock_irqrestore(&port->conf_lock, flags);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* PCI configuration space read function */
|
|
|
|
static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
|
|
|
|
int size, u32 *val)
|
|
|
|
{
|
|
|
|
struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
|
|
|
|
struct mvebu_pcie_port *port;
|
|
|
|
unsigned long flags;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
port = mvebu_pcie_find_port(pcie, bus, devfn);
|
|
|
|
if (!port) {
|
|
|
|
*val = 0xffffffff;
|
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Access the emulated PCI-to-PCI bridge */
|
|
|
|
if (bus->number == 0)
|
|
|
|
return mvebu_sw_pci_bridge_read(port, where, size, val);
|
|
|
|
|
2013-10-01 11:58:00 -06:00
|
|
|
if (!mvebu_pcie_link_up(port)) {
|
pci: mvebu: allow the enumeration of devices beyond physical bridges
Until now, the Marvell PCIe driver was only allowing the enumeration
of the devices in the secondary bus of the emulated PCI-to-PCI
bridge. This works fine when a PCIe device is directly connected into
a PCIe slot of the Marvell board.
However, when the device connected in the PCIe slot is a physical PCIe
bridge, beyond which a real PCIe device is connected, it no longer
worked, as the driver was preventing the Linux PCI core from seeing
such devices.
This commit fixes that by ensuring that configuration transactions on
subordinate busses are properly forwarded on the right PCIe interface.
Thanks to this patch, a PCIe card beyond a PCIe bridge, itself beyond
the emulated PCI-to-PCI bridge is properly detected, with the
following layout:
-[0000:00]-+-01.0-[01]----00.0
+-09.0-[02-07]----00.0-[03-07]--+-01.0-[04]--
| +-05.0-[05]--
| +-07.0-[06]--
| \-09.0-[07]----00.0
\-0a.0-[08]----00.0
Where the PCIe interface that sits beyond the emulated PCI-to-PCI
bridge at 09.0 allows to access the secondary bus 02, on which there
is a PCIe bridge that allows to access the 3 to 7 busses, that are
subordinates to this bridge. And on one of this bus (bus 7), there is
one real PCIe device connected.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 08:32:52 -06:00
|
|
|
*val = 0xffffffff;
|
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* On the secondary bus, we don't want to expose any other
|
|
|
|
* device than the device physically connected in the PCIe
|
|
|
|
* slot, visible in slot 0. In slot 1, there's a special
|
|
|
|
* Marvell device that only makes sense when the Armada is
|
|
|
|
* used as a PCIe endpoint.
|
|
|
|
*/
|
|
|
|
if (bus->number == port->bridge.secondary_bus &&
|
|
|
|
PCI_SLOT(devfn) != 0) {
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
*val = 0xffffffff;
|
|
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Access the real PCIe interface */
|
|
|
|
spin_lock_irqsave(&port->conf_lock, flags);
|
pci: mvebu: no longer fake the slot location of downstream devices
By default, the Marvell hardware, for each PCIe interface, exhibits
the following devices:
* On slot 0, a "Marvell Memory controller", identical on all PCIe
interfaces, and which isn't useful when the Marvell SoC is the PCIe
root complex (i.e, the normal case when we run Linux on the Marvell
SoC).
* On slot 1, the real PCIe card connected into the PCIe slot of the
board.
So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge
emulation is that when the Linux PCI core was trying to access the
device in slot 0, we were in fact forwarding the configuration
transaction to the device in slot 1. For all other slots, we were
telling the Linux PCI core that there was no device connected.
However, new versions of bootloaders from Marvell change the default
PCIe configuration, and make the real device appear in slot 0, and the
"Marvell Memory controller" in slot 1.
Therefore, this commit modifies the Marvell PCIe driver to adjust the
PCIe hardware configuration to make sure that this behavior (real
device in slot 0, "Marvell Memory controller" in slot 1) is the one
we'll see regardless of what the bootloader has done. It allows to
remove the little hack that was forwarding configuration transactions
on slot 0 to slot 1, which is nice.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 08:32:51 -06:00
|
|
|
ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
where, size, val);
|
|
|
|
spin_unlock_irqrestore(&port->conf_lock, flags);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct pci_ops mvebu_pcie_ops = {
|
|
|
|
.read = mvebu_pcie_rd_conf,
|
|
|
|
.write = mvebu_pcie_wr_conf,
|
|
|
|
};
|
|
|
|
|
2013-08-13 06:25:22 -06:00
|
|
|
static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
{
|
|
|
|
struct mvebu_pcie *pcie = sys_to_pcie(sys);
|
|
|
|
int i;
|
2014-02-12 15:57:08 -07:00
|
|
|
int domain = 0;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
2014-02-12 15:57:08 -07:00
|
|
|
#ifdef CONFIG_PCI_DOMAINS
|
|
|
|
domain = sys->domain;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
snprintf(pcie->mem_name, sizeof(pcie->mem_name), "PCI MEM %04x",
|
|
|
|
domain);
|
|
|
|
pcie->mem.name = pcie->mem_name;
|
|
|
|
|
|
|
|
snprintf(pcie->io_name, sizeof(pcie->io_name), "PCI I/O %04x", domain);
|
|
|
|
pcie->realio.name = pcie->io_name;
|
|
|
|
|
|
|
|
if (request_resource(&iomem_resource, &pcie->mem))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (resource_size(&pcie->realio) != 0) {
|
|
|
|
if (request_resource(&ioport_resource, &pcie->realio)) {
|
|
|
|
release_resource(&pcie->mem);
|
|
|
|
return 0;
|
|
|
|
}
|
2013-11-26 11:02:55 -07:00
|
|
|
pci_add_resource_offset(&sys->resources, &pcie->realio,
|
|
|
|
sys->io_offset);
|
2014-02-12 15:57:08 -07:00
|
|
|
}
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
|
|
|
|
pci_add_resource(&sys->resources, &pcie->busn);
|
|
|
|
|
|
|
|
for (i = 0; i < pcie->nports; i++) {
|
|
|
|
struct mvebu_pcie_port *port = &pcie->ports[i];
|
2013-07-26 07:17:49 -06:00
|
|
|
if (!port->base)
|
|
|
|
continue;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
mvebu_pcie_setup_hw(port);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
|
|
|
|
{
|
|
|
|
struct mvebu_pcie *pcie = sys_to_pcie(sys);
|
|
|
|
struct pci_bus *bus;
|
|
|
|
|
|
|
|
bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
|
|
|
|
&mvebu_pcie_ops, sys, &sys->resources);
|
|
|
|
if (!bus)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
pci_scan_child_bus(bus);
|
|
|
|
|
|
|
|
return bus;
|
|
|
|
}
|
|
|
|
|
2013-09-16 23:26:46 -06:00
|
|
|
static void mvebu_pcie_add_bus(struct pci_bus *bus)
|
2013-08-09 14:27:14 -06:00
|
|
|
{
|
|
|
|
struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
|
|
|
|
bus->msi = pcie->msi;
|
|
|
|
}
|
|
|
|
|
2013-09-16 23:26:46 -06:00
|
|
|
static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
|
|
|
|
const struct resource *res,
|
|
|
|
resource_size_t start,
|
|
|
|
resource_size_t size,
|
|
|
|
resource_size_t align)
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
{
|
|
|
|
if (dev->bus->number != 0)
|
|
|
|
return start;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* On the PCI-to-PCI bridge side, the I/O windows must have at
|
2014-04-18 06:19:53 -06:00
|
|
|
* least a 64 KB size and the memory windows must have at
|
|
|
|
* least a 1 MB size. Moreover, MBus windows need to have a
|
|
|
|
* base address aligned on their size, and their size must be
|
|
|
|
* a power of two. This means that if the BAR doesn't have a
|
|
|
|
* power of two size, several MBus windows will actually be
|
|
|
|
* created. We need to ensure that the biggest MBus window
|
|
|
|
* (which will be the first one) is aligned on its size, which
|
|
|
|
* explains the rounddown_pow_of_two() being done here.
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
*/
|
|
|
|
if (res->flags & IORESOURCE_IO)
|
2014-04-18 06:19:53 -06:00
|
|
|
return round_up(start, max_t(resource_size_t, SZ_64K,
|
|
|
|
rounddown_pow_of_two(size)));
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
else if (res->flags & IORESOURCE_MEM)
|
2014-04-18 06:19:53 -06:00
|
|
|
return round_up(start, max_t(resource_size_t, SZ_1M,
|
|
|
|
rounddown_pow_of_two(size)));
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
else
|
|
|
|
return start;
|
|
|
|
}
|
|
|
|
|
2013-08-13 06:25:22 -06:00
|
|
|
static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
{
|
|
|
|
struct hw_pci hw;
|
|
|
|
|
|
|
|
memset(&hw, 0, sizeof(hw));
|
|
|
|
|
|
|
|
hw.nr_controllers = 1;
|
|
|
|
hw.private_data = (void **)&pcie;
|
|
|
|
hw.setup = mvebu_pcie_setup;
|
|
|
|
hw.scan = mvebu_pcie_scan_bus;
|
2013-09-19 15:44:55 -06:00
|
|
|
hw.map_irq = of_irq_parse_and_map_pci;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
hw.ops = &mvebu_pcie_ops;
|
|
|
|
hw.align_resource = mvebu_pcie_align_resource;
|
2013-08-09 14:27:14 -06:00
|
|
|
hw.add_bus = mvebu_pcie_add_bus;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
|
|
|
pci_common_init(&hw);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Looks up the list of register addresses encoded into the reg =
|
|
|
|
* <...> property for one that matches the given port/lane. Once
|
|
|
|
* found, maps it.
|
|
|
|
*/
|
2013-08-13 06:25:22 -06:00
|
|
|
static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
|
|
|
|
struct device_node *np, struct mvebu_pcie_port *port)
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
{
|
|
|
|
struct resource regs;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
ret = of_address_to_resource(np, 0, ®s);
|
|
|
|
if (ret)
|
2013-06-17 03:16:13 -06:00
|
|
|
return ERR_PTR(ret);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
2013-06-17 03:16:13 -06:00
|
|
|
return devm_ioremap_resource(&pdev->dev, ®s);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
}
|
|
|
|
|
2013-07-26 07:17:48 -06:00
|
|
|
#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
|
|
|
|
#define DT_TYPE_IO 0x1
|
|
|
|
#define DT_TYPE_MEM32 0x2
|
|
|
|
#define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
|
|
|
|
#define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
|
|
|
|
|
|
|
|
static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
|
2013-11-26 11:02:55 -07:00
|
|
|
unsigned long type,
|
|
|
|
unsigned int *tgt,
|
|
|
|
unsigned int *attr)
|
2013-07-26 07:17:48 -06:00
|
|
|
{
|
|
|
|
const int na = 3, ns = 2;
|
|
|
|
const __be32 *range;
|
|
|
|
int rlen, nranges, rangesz, pna, i;
|
|
|
|
|
2013-11-26 11:02:55 -07:00
|
|
|
*tgt = -1;
|
|
|
|
*attr = -1;
|
|
|
|
|
2013-07-26 07:17:48 -06:00
|
|
|
range = of_get_property(np, "ranges", &rlen);
|
|
|
|
if (!range)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
pna = of_n_addr_cells(np);
|
|
|
|
rangesz = pna + na + ns;
|
|
|
|
nranges = rlen / sizeof(__be32) / rangesz;
|
|
|
|
|
|
|
|
for (i = 0; i < nranges; i++) {
|
|
|
|
u32 flags = of_read_number(range, 1);
|
2014-02-14 11:46:15 -07:00
|
|
|
u32 slot = of_read_number(range + 1, 1);
|
2013-07-26 07:17:48 -06:00
|
|
|
u64 cpuaddr = of_read_number(range + na, pna);
|
|
|
|
unsigned long rtype;
|
|
|
|
|
|
|
|
if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
|
|
|
|
rtype = IORESOURCE_IO;
|
|
|
|
else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
|
|
|
|
rtype = IORESOURCE_MEM;
|
|
|
|
|
|
|
|
if (slot == PCI_SLOT(devfn) && type == rtype) {
|
|
|
|
*tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
|
|
|
|
*attr = DT_CPUADDR_TO_ATTR(cpuaddr);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
range += rangesz;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -ENOENT;
|
|
|
|
}
|
|
|
|
|
2013-08-13 06:25:22 -06:00
|
|
|
static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
|
2013-08-09 14:27:14 -06:00
|
|
|
{
|
|
|
|
struct device_node *msi_node;
|
|
|
|
|
|
|
|
msi_node = of_parse_phandle(pcie->pdev->dev.of_node,
|
|
|
|
"msi-parent", 0);
|
|
|
|
if (!msi_node)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pcie->msi = of_pci_find_msi_chip_by_node(msi_node);
|
|
|
|
|
|
|
|
if (pcie->msi)
|
|
|
|
pcie->msi->dev = &pcie->pdev->dev;
|
|
|
|
}
|
|
|
|
|
2013-08-13 06:25:22 -06:00
|
|
|
static int mvebu_pcie_probe(struct platform_device *pdev)
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
{
|
|
|
|
struct mvebu_pcie *pcie;
|
|
|
|
struct device_node *np = pdev->dev.of_node;
|
|
|
|
struct device_node *child;
|
|
|
|
int i, ret;
|
|
|
|
|
|
|
|
pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!pcie)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
pcie->pdev = pdev;
|
2013-08-13 06:25:22 -06:00
|
|
|
platform_set_drvdata(pdev, pcie);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
2013-07-26 07:17:48 -06:00
|
|
|
/* Get the PCIe memory and I/O aperture */
|
|
|
|
mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
|
|
|
|
if (resource_size(&pcie->mem) == 0) {
|
|
|
|
dev_err(&pdev->dev, "invalid memory aperture size\n");
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
return -EINVAL;
|
2013-07-26 07:17:48 -06:00
|
|
|
}
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
2013-07-26 07:17:48 -06:00
|
|
|
mvebu_mbus_get_pcie_io_aperture(&pcie->io);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
2013-11-26 11:02:55 -07:00
|
|
|
if (resource_size(&pcie->io) != 0) {
|
|
|
|
pcie->realio.flags = pcie->io.flags;
|
|
|
|
pcie->realio.start = PCIBIOS_MIN_IO;
|
|
|
|
pcie->realio.end = min_t(resource_size_t,
|
|
|
|
IO_SPACE_LIMIT,
|
|
|
|
resource_size(&pcie->io));
|
|
|
|
} else
|
|
|
|
pcie->realio = pcie->io;
|
2013-07-26 07:17:48 -06:00
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
/* Get the bus range */
|
|
|
|
ret = of_pci_parse_bus_range(np, &pcie->busn);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
|
|
|
|
ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2013-08-13 06:25:21 -06:00
|
|
|
i = 0;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
for_each_child_of_node(pdev->dev.of_node, child) {
|
|
|
|
if (!of_device_is_available(child))
|
|
|
|
continue;
|
2013-08-13 06:25:21 -06:00
|
|
|
i++;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
}
|
|
|
|
|
2013-08-13 06:25:21 -06:00
|
|
|
pcie->ports = devm_kzalloc(&pdev->dev, i *
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
sizeof(struct mvebu_pcie_port),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!pcie->ports)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
i = 0;
|
|
|
|
for_each_child_of_node(pdev->dev.of_node, child) {
|
|
|
|
struct mvebu_pcie_port *port = &pcie->ports[i];
|
2013-08-13 06:25:23 -06:00
|
|
|
enum of_gpio_flags flags;
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
|
|
|
if (!of_device_is_available(child))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
port->pcie = pcie;
|
|
|
|
|
|
|
|
if (of_property_read_u32(child, "marvell,pcie-port",
|
|
|
|
&port->port)) {
|
|
|
|
dev_warn(&pdev->dev,
|
|
|
|
"ignoring PCIe DT node, missing pcie-port property\n");
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (of_property_read_u32(child, "marvell,pcie-lane",
|
|
|
|
&port->lane))
|
|
|
|
port->lane = 0;
|
|
|
|
|
|
|
|
port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
|
|
|
|
port->port, port->lane);
|
|
|
|
|
|
|
|
port->devfn = of_pci_get_devfn(child);
|
|
|
|
if (port->devfn < 0)
|
|
|
|
continue;
|
|
|
|
|
2013-07-26 07:17:48 -06:00
|
|
|
ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM,
|
|
|
|
&port->mem_target, &port->mem_attr);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n",
|
|
|
|
port->port, port->lane);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2013-11-26 11:02:55 -07:00
|
|
|
if (resource_size(&pcie->io) != 0)
|
|
|
|
mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
|
|
|
|
&port->io_target, &port->io_attr);
|
|
|
|
else {
|
|
|
|
port->io_target = -1;
|
|
|
|
port->io_attr = -1;
|
2013-07-26 07:17:48 -06:00
|
|
|
}
|
|
|
|
|
2013-08-13 06:25:23 -06:00
|
|
|
port->reset_gpio = of_get_named_gpio_flags(child,
|
|
|
|
"reset-gpios", 0, &flags);
|
|
|
|
if (gpio_is_valid(port->reset_gpio)) {
|
|
|
|
u32 reset_udelay = 20000;
|
|
|
|
|
|
|
|
port->reset_active_low = flags & OF_GPIO_ACTIVE_LOW;
|
|
|
|
port->reset_name = kasprintf(GFP_KERNEL,
|
|
|
|
"pcie%d.%d-reset", port->port, port->lane);
|
|
|
|
of_property_read_u32(child, "reset-delay-us",
|
|
|
|
&reset_udelay);
|
|
|
|
|
|
|
|
ret = devm_gpio_request_one(&pdev->dev,
|
|
|
|
port->reset_gpio, GPIOF_DIR_OUT, port->reset_name);
|
|
|
|
if (ret) {
|
|
|
|
if (ret == -EPROBE_DEFER)
|
|
|
|
return ret;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
gpio_set_value(port->reset_gpio,
|
|
|
|
(port->reset_active_low) ? 1 : 0);
|
|
|
|
msleep(reset_udelay/1000);
|
|
|
|
}
|
|
|
|
|
2013-08-13 06:25:20 -06:00
|
|
|
port->clk = of_clk_get_by_name(child, NULL);
|
|
|
|
if (IS_ERR(port->clk)) {
|
|
|
|
dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
|
|
|
|
port->port, port->lane);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = clk_prepare_enable(port->clk);
|
|
|
|
if (ret)
|
|
|
|
continue;
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
port->base = mvebu_pcie_map_registers(pdev, child, port);
|
2013-06-17 03:16:13 -06:00
|
|
|
if (IS_ERR(port->base)) {
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
|
|
|
|
port->port, port->lane);
|
2013-06-17 03:16:13 -06:00
|
|
|
port->base = NULL;
|
2013-08-13 06:25:20 -06:00
|
|
|
clk_disable_unprepare(port->clk);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
pci: mvebu: no longer fake the slot location of downstream devices
By default, the Marvell hardware, for each PCIe interface, exhibits
the following devices:
* On slot 0, a "Marvell Memory controller", identical on all PCIe
interfaces, and which isn't useful when the Marvell SoC is the PCIe
root complex (i.e, the normal case when we run Linux on the Marvell
SoC).
* On slot 1, the real PCIe card connected into the PCIe slot of the
board.
So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge
emulation is that when the Linux PCI core was trying to access the
device in slot 0, we were in fact forwarding the configuration
transaction to the device in slot 1. For all other slots, we were
telling the Linux PCI core that there was no device connected.
However, new versions of bootloaders from Marvell change the default
PCIe configuration, and make the real device appear in slot 0, and the
"Marvell Memory controller" in slot 1.
Therefore, this commit modifies the Marvell PCIe driver to adjust the
PCIe hardware configuration to make sure that this behavior (real
device in slot 0, "Marvell Memory controller" in slot 1) is the one
we'll see regardless of what the bootloader has done. It allows to
remove the little hack that was forwarding configuration transactions
on slot 0 to slot 1, which is nice.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-23 08:32:51 -06:00
|
|
|
mvebu_pcie_set_local_dev_nr(port, 1);
|
|
|
|
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
port->dn = child;
|
|
|
|
spin_lock_init(&port->conf_lock);
|
|
|
|
mvebu_sw_pci_bridge_init(port);
|
|
|
|
i++;
|
|
|
|
}
|
|
|
|
|
2013-08-13 06:25:21 -06:00
|
|
|
pcie->nports = i;
|
2013-12-26 08:52:41 -07:00
|
|
|
|
|
|
|
for (i = 0; i < (IO_SPACE_LIMIT - SZ_64K); i += SZ_64K)
|
|
|
|
pci_ioremap_io(i, pcie->io.start + i);
|
|
|
|
|
2013-08-09 14:27:14 -06:00
|
|
|
mvebu_pcie_msi_enable(pcie);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
mvebu_pcie_enable(pcie);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id mvebu_pcie_of_match_table[] = {
|
|
|
|
{ .compatible = "marvell,armada-xp-pcie", },
|
|
|
|
{ .compatible = "marvell,armada-370-pcie", },
|
2013-08-13 06:25:24 -06:00
|
|
|
{ .compatible = "marvell,dove-pcie", },
|
2013-05-15 07:36:54 -06:00
|
|
|
{ .compatible = "marvell,kirkwood-pcie", },
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
{},
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
|
|
|
|
|
|
|
|
static struct platform_driver mvebu_pcie_driver = {
|
|
|
|
.driver = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.name = "mvebu-pcie",
|
2013-12-19 02:04:59 -07:00
|
|
|
.of_match_table = mvebu_pcie_of_match_table,
|
2013-08-13 06:25:22 -06:00
|
|
|
/* driver unloading/unbinding currently not supported */
|
|
|
|
.suppress_bind_attrs = true,
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
},
|
2013-08-13 06:25:22 -06:00
|
|
|
.probe = mvebu_pcie_probe,
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
};
|
2013-08-13 06:25:22 -06:00
|
|
|
module_platform_driver(mvebu_pcie_driver);
|
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-05-16 09:55:22 -06:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
|
|
|
|
MODULE_DESCRIPTION("Marvell EBU PCIe driver");
|
|
|
|
MODULE_LICENSE("GPLv2");
|