2005-04-16 16:20:36 -06:00
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/*
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* linux/arch/arm/mach-versatile/core.c
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*
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* Copyright (C) 1999 - 2003 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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2005-10-29 12:07:23 -06:00
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#include <linux/platform_device.h>
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2005-04-16 16:20:36 -06:00
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#include <linux/interrupt.h>
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2011-07-26 03:19:06 -06:00
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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2006-01-07 06:52:45 -07:00
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#include <linux/amba/bus.h>
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#include <linux/amba/clcd.h>
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2009-07-05 15:43:01 -06:00
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#include <linux/amba/pl061.h>
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2009-09-22 07:29:36 -06:00
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#include <linux/amba/mmci.h>
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2010-07-14 16:59:27 -06:00
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#include <linux/amba/pl022.h>
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2008-09-06 05:10:45 -06:00
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#include <linux/io.h>
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2013-01-07 08:45:59 -07:00
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#include <linux/irqchip/arm-vic.h>
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2012-10-31 15:04:31 -06:00
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#include <linux/irqchip/versatile-fpga.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/gfp.h>
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2010-11-17 02:04:33 -07:00
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#include <linux/clkdev.h>
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2011-05-18 03:51:50 -06:00
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#include <linux/mtd/physmap.h>
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2013-01-28 13:58:22 -07:00
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#include <linux/bitops.h>
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2013-07-08 17:01:40 -06:00
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#include <linux/reboot.h>
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2005-04-16 16:20:36 -06:00
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#include <asm/irq.h>
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2005-06-29 08:15:54 -06:00
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#include <asm/hardware/arm_timer.h>
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2010-01-16 13:16:10 -07:00
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#include <asm/hardware/icst.h>
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2006-07-10 09:33:54 -06:00
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#include <asm/mach-types.h>
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2005-04-16 16:20:36 -06:00
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#include <asm/mach/arch.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include <asm/mach/map.h>
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2010-01-14 12:59:37 -07:00
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#include <mach/hardware.h>
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#include <mach/platform.h>
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2010-10-06 09:18:08 -06:00
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#include <asm/hardware/timer-sp.h>
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2005-04-16 16:20:36 -06:00
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2011-01-18 13:12:10 -07:00
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#include <plat/clcd.h>
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2010-12-15 14:56:47 -07:00
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#include <plat/sched_clock.h>
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2005-04-16 16:20:36 -06:00
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#include "core.h"
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/*
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* All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
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* is the (PA >> 12).
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*
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* Setup a VA for the Versatile Vectored Interrupt Controller.
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*/
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2005-09-28 17:09:02 -06:00
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#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
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#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
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2005-04-16 16:20:36 -06:00
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2013-01-28 13:58:22 -07:00
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/* These PIC IRQs are valid in each configuration */
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#define PIC_VALID_ALL BIT(SIC_INT_KMI0) | BIT(SIC_INT_KMI1) | \
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BIT(SIC_INT_SCI3) | BIT(SIC_INT_UART3) | \
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BIT(SIC_INT_CLCD) | BIT(SIC_INT_TOUCH) | \
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BIT(SIC_INT_KEYPAD) | BIT(SIC_INT_DoC) | \
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BIT(SIC_INT_USB) | BIT(SIC_INT_PCI0) | \
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BIT(SIC_INT_PCI1) | BIT(SIC_INT_PCI2) | \
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BIT(SIC_INT_PCI3)
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2005-04-16 16:20:36 -06:00
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#if 1
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#define IRQ_MMCI0A IRQ_VICSOURCE22
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#define IRQ_AACI IRQ_VICSOURCE24
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#define IRQ_ETH IRQ_VICSOURCE25
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#define PIC_MASK 0xFFD00000
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2013-01-28 13:58:22 -07:00
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#define PIC_VALID PIC_VALID_ALL
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2005-04-16 16:20:36 -06:00
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#else
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#define IRQ_MMCI0A IRQ_SIC_MMCI0A
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#define IRQ_AACI IRQ_SIC_AACI
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#define IRQ_ETH IRQ_SIC_ETH
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#define PIC_MASK 0
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2013-01-28 13:58:22 -07:00
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#define PIC_VALID PIC_VALID_ALL | BIT(SIC_INT_MMCI0A) | \
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BIT(SIC_INT_MMCI1A) | BIT(SIC_INT_AACI) | \
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BIT(SIC_INT_ETH)
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2005-04-16 16:20:36 -06:00
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#endif
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2011-07-26 03:19:06 -06:00
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/* Lookup table for finding a DT node that represents the vic instance */
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static const struct of_device_id vic_of_match[] __initconst = {
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{ .compatible = "arm,versatile-vic", },
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{}
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};
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static const struct of_device_id sic_of_match[] __initconst = {
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{ .compatible = "arm,versatile-sic", },
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{}
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};
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2005-04-16 16:20:36 -06:00
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void __init versatile_init_irq(void)
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{
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2012-02-14 14:06:57 -07:00
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struct device_node *np;
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np = of_find_matching_node_by_address(NULL, vic_of_match,
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VERSATILE_VIC_BASE);
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2013-11-21 15:11:29 -07:00
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__vic_init(VA_VIC_BASE, 0, IRQ_VIC_START, ~0, 0, np);
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2005-04-16 16:20:36 -06:00
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writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
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2012-04-28 07:33:47 -06:00
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np = of_find_matching_node_by_address(NULL, sic_of_match,
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VERSATILE_SIC_BASE);
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fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
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2013-01-28 13:58:22 -07:00
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IRQ_VICSOURCE31, PIC_VALID, np);
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2005-04-16 16:20:36 -06:00
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/*
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* Interrupts on secondary controller from 0 to 8 are routed to
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* source 31 on PIC.
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* Interrupts from 21 to 31 are routed directly to the VIC on
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* the corresponding number on primary controller. This is controlled
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* by setting PIC_ENABLEx.
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*/
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writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
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}
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2013-02-14 05:50:57 -07:00
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static struct map_desc versatile_io_desc[] __initdata __maybe_unused = {
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2005-10-28 08:19:06 -06:00
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{
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.virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
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.pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
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.pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
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.pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
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.pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
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.length = SZ_4K * 9,
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.type = MT_DEVICE
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},
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2005-04-16 16:20:36 -06:00
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#ifdef CONFIG_MACH_VERSATILE_AB
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2005-10-28 08:19:06 -06:00
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{
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.virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
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.pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
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.length = SZ_64M,
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.type = MT_DEVICE
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},
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2005-04-16 16:20:36 -06:00
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#endif
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#ifdef CONFIG_DEBUG_LL
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2005-10-28 08:19:06 -06:00
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{
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.virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
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.pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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},
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2005-04-16 16:20:36 -06:00
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#endif
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2005-06-20 11:51:06 -06:00
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#ifdef CONFIG_PCI
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2005-10-28 08:19:06 -06:00
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{
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.virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
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.pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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2006-10-11 10:22:34 -06:00
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.virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
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2005-10-28 08:19:06 -06:00
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.pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
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.length = VERSATILE_PCI_BASE_SIZE,
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.type = MT_DEVICE
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}, {
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2006-10-11 10:22:34 -06:00
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.virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
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2005-10-28 08:19:06 -06:00
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.pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
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.length = VERSATILE_PCI_CFG_BASE_SIZE,
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.type = MT_DEVICE
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},
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2005-06-20 11:51:06 -06:00
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#endif
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2005-04-16 16:20:36 -06:00
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};
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void __init versatile_map_io(void)
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{
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iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
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}
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2005-09-28 17:09:02 -06:00
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#define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
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2005-04-16 16:20:36 -06:00
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2011-05-18 03:51:55 -06:00
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static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
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2005-04-16 16:20:36 -06:00
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{
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u32 val;
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val = __raw_readl(VERSATILE_FLASHCTRL);
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if (on)
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val |= VERSATILE_FLASHPROG_FLVPPEN;
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else
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val &= ~VERSATILE_FLASHPROG_FLVPPEN;
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__raw_writel(val, VERSATILE_FLASHCTRL);
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}
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2011-05-18 03:51:50 -06:00
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static struct physmap_flash_data versatile_flash_data = {
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2005-04-16 16:20:36 -06:00
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.width = 4,
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.set_vpp = versatile_flash_set_vpp,
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};
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static struct resource versatile_flash_resource = {
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.start = VERSATILE_FLASH_BASE,
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2006-08-13 07:17:12 -06:00
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.end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
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2005-04-16 16:20:36 -06:00
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device versatile_flash_device = {
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2011-05-18 03:51:50 -06:00
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.name = "physmap-flash",
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2005-04-16 16:20:36 -06:00
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.id = 0,
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.dev = {
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.platform_data = &versatile_flash_data,
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},
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.num_resources = 1,
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.resource = &versatile_flash_resource,
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};
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static struct resource smc91x_resources[] = {
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[0] = {
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.start = VERSATILE_ETH_BASE,
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.end = VERSATILE_ETH_BASE + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_ETH,
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.end = IRQ_ETH,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device smc91x_device = {
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.name = "smc91x",
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.id = 0,
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.num_resources = ARRAY_SIZE(smc91x_resources),
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.resource = smc91x_resources,
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};
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2006-12-10 13:21:32 -07:00
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static struct resource versatile_i2c_resource = {
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.start = VERSATILE_I2C_BASE,
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.end = VERSATILE_I2C_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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};
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|
|
|
|
static struct platform_device versatile_i2c_device = {
|
|
|
|
.name = "versatile-i2c",
|
2009-02-12 07:58:20 -07:00
|
|
|
.id = 0,
|
2006-12-10 13:21:32 -07:00
|
|
|
.num_resources = 1,
|
|
|
|
.resource = &versatile_i2c_resource,
|
|
|
|
};
|
|
|
|
|
2009-02-12 07:58:20 -07:00
|
|
|
static struct i2c_board_info versatile_i2c_board_info[] = {
|
|
|
|
{
|
2009-07-18 08:51:55 -06:00
|
|
|
I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
|
2009-02-12 07:58:20 -07:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init versatile_i2c_init(void)
|
|
|
|
{
|
|
|
|
return i2c_register_board_info(0, versatile_i2c_board_info,
|
|
|
|
ARRAY_SIZE(versatile_i2c_board_info));
|
|
|
|
}
|
|
|
|
arch_initcall(versatile_i2c_init);
|
|
|
|
|
2005-09-28 17:09:02 -06:00
|
|
|
#define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
unsigned int mmc_status(struct device *dev)
|
|
|
|
{
|
|
|
|
struct amba_device *adev = container_of(dev, struct amba_device, dev);
|
|
|
|
u32 mask;
|
|
|
|
|
|
|
|
if (adev->res.start == VERSATILE_MMCI0_BASE)
|
|
|
|
mask = 1;
|
|
|
|
else
|
|
|
|
mask = 2;
|
|
|
|
|
|
|
|
return readl(VERSATILE_SYSMCI) & mask;
|
|
|
|
}
|
|
|
|
|
2009-09-22 07:29:36 -06:00
|
|
|
static struct mmci_platform_data mmc0_plat_data = {
|
2005-04-16 16:20:36 -06:00
|
|
|
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
|
|
|
|
.status = mmc_status,
|
2009-07-09 08:15:12 -06:00
|
|
|
.gpio_wp = -1,
|
|
|
|
.gpio_cd = -1,
|
2005-04-16 16:20:36 -06:00
|
|
|
};
|
|
|
|
|
2011-03-30 00:02:29 -06:00
|
|
|
static struct resource char_lcd_resources[] = {
|
2010-07-17 05:34:25 -06:00
|
|
|
{
|
|
|
|
.start = VERSATILE_CHAR_LCD_BASE,
|
|
|
|
.end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device char_lcd_device = {
|
|
|
|
.name = "arm-charlcd",
|
|
|
|
.id = -1,
|
|
|
|
.num_resources = ARRAY_SIZE(char_lcd_resources),
|
|
|
|
.resource = char_lcd_resources,
|
|
|
|
};
|
|
|
|
|
2014-02-27 06:29:22 -07:00
|
|
|
static struct resource leds_resources[] = {
|
|
|
|
{
|
|
|
|
.start = VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET,
|
|
|
|
.end = VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET + 4,
|
|
|
|
.flags = IORESOURCE_MEM,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device leds_device = {
|
|
|
|
.name = "versatile-leds",
|
|
|
|
.id = -1,
|
|
|
|
.num_resources = ARRAY_SIZE(leds_resources),
|
|
|
|
.resource = leds_resources,
|
|
|
|
};
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/*
|
|
|
|
* Clock handling
|
|
|
|
*/
|
2010-01-16 09:27:28 -07:00
|
|
|
static const struct icst_params versatile_oscvco_params = {
|
2010-01-16 10:28:44 -07:00
|
|
|
.ref = 24000000,
|
2010-01-16 11:08:47 -07:00
|
|
|
.vco_max = ICST307_VCO_MAX,
|
2010-01-16 12:49:39 -07:00
|
|
|
.vco_min = ICST307_VCO_MIN,
|
2005-04-16 16:20:36 -06:00
|
|
|
.vd_min = 4 + 8,
|
|
|
|
.vd_max = 511 + 8,
|
|
|
|
.rd_min = 1 + 2,
|
|
|
|
.rd_max = 127 + 2,
|
2010-01-16 12:46:19 -07:00
|
|
|
.s2div = icst307_s2div,
|
|
|
|
.idx2s = icst307_idx2s,
|
2005-04-16 16:20:36 -06:00
|
|
|
};
|
|
|
|
|
2010-01-16 09:27:28 -07:00
|
|
|
static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
2010-01-14 13:09:34 -07:00
|
|
|
void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
|
2005-04-16 16:20:36 -06:00
|
|
|
u32 val;
|
|
|
|
|
2010-01-14 13:09:34 -07:00
|
|
|
val = readl(clk->vcoreg) & ~0x7ffff;
|
2005-04-16 16:20:36 -06:00
|
|
|
val |= vco.v | (vco.r << 9) | (vco.s << 16);
|
|
|
|
|
|
|
|
writel(0xa05f, sys_lock);
|
2010-01-14 13:09:34 -07:00
|
|
|
writel(val, clk->vcoreg);
|
2005-04-16 16:20:36 -06:00
|
|
|
writel(0, sys_lock);
|
|
|
|
}
|
|
|
|
|
2010-03-01 09:18:39 -07:00
|
|
|
static const struct clk_ops osc4_clk_ops = {
|
|
|
|
.round = icst_clk_round,
|
|
|
|
.set = icst_clk_set,
|
|
|
|
.setvco = versatile_oscvco_set,
|
|
|
|
};
|
|
|
|
|
2008-11-08 13:13:53 -07:00
|
|
|
static struct clk osc4_clk = {
|
2010-03-01 09:18:39 -07:00
|
|
|
.ops = &osc4_clk_ops,
|
2005-04-16 16:20:36 -06:00
|
|
|
.params = &versatile_oscvco_params,
|
2008-11-08 13:13:53 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* These are fixed clocks.
|
|
|
|
*/
|
|
|
|
static struct clk ref24_clk = {
|
|
|
|
.rate = 24000000,
|
|
|
|
};
|
|
|
|
|
2011-05-12 06:31:48 -06:00
|
|
|
static struct clk sp804_clk = {
|
|
|
|
.rate = 1000000,
|
|
|
|
};
|
|
|
|
|
2010-07-15 04:01:17 -06:00
|
|
|
static struct clk dummy_apb_pclk;
|
|
|
|
|
2009-05-18 10:29:30 -06:00
|
|
|
static struct clk_lookup lookups[] = {
|
2010-07-15 04:01:17 -06:00
|
|
|
{ /* AMBA bus clock */
|
|
|
|
.con_id = "apb_pclk",
|
|
|
|
.clk = &dummy_apb_pclk,
|
|
|
|
}, { /* UART0 */
|
2008-11-08 13:13:53 -07:00
|
|
|
.dev_id = "dev:f1",
|
|
|
|
.clk = &ref24_clk,
|
|
|
|
}, { /* UART1 */
|
|
|
|
.dev_id = "dev:f2",
|
|
|
|
.clk = &ref24_clk,
|
|
|
|
}, { /* UART2 */
|
|
|
|
.dev_id = "dev:f3",
|
|
|
|
.clk = &ref24_clk,
|
|
|
|
}, { /* UART3 */
|
|
|
|
.dev_id = "fpga:09",
|
|
|
|
.clk = &ref24_clk,
|
|
|
|
}, { /* KMI0 */
|
|
|
|
.dev_id = "fpga:06",
|
|
|
|
.clk = &ref24_clk,
|
|
|
|
}, { /* KMI1 */
|
|
|
|
.dev_id = "fpga:07",
|
|
|
|
.clk = &ref24_clk,
|
|
|
|
}, { /* MMC0 */
|
|
|
|
.dev_id = "fpga:05",
|
|
|
|
.clk = &ref24_clk,
|
|
|
|
}, { /* MMC1 */
|
|
|
|
.dev_id = "fpga:0b",
|
|
|
|
.clk = &ref24_clk,
|
2010-07-14 16:59:27 -06:00
|
|
|
}, { /* SSP */
|
|
|
|
.dev_id = "dev:f4",
|
|
|
|
.clk = &ref24_clk,
|
2008-11-08 13:13:53 -07:00
|
|
|
}, { /* CLCD */
|
|
|
|
.dev_id = "dev:20",
|
|
|
|
.clk = &osc4_clk,
|
2011-05-12 06:31:48 -06:00
|
|
|
}, { /* SP804 timers */
|
|
|
|
.dev_id = "sp804",
|
|
|
|
.clk = &sp804_clk,
|
|
|
|
},
|
2005-04-16 16:20:36 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* CLCD support.
|
|
|
|
*/
|
|
|
|
#define SYS_CLCD_MODE_MASK (3 << 0)
|
|
|
|
#define SYS_CLCD_MODE_888 (0 << 0)
|
|
|
|
#define SYS_CLCD_MODE_5551 (1 << 0)
|
|
|
|
#define SYS_CLCD_MODE_565_RLSB (2 << 0)
|
|
|
|
#define SYS_CLCD_MODE_565_BLSB (3 << 0)
|
|
|
|
#define SYS_CLCD_NLCDIOON (1 << 2)
|
|
|
|
#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
|
|
|
|
#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
|
|
|
|
#define SYS_CLCD_ID_MASK (0x1f << 8)
|
|
|
|
#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
|
|
|
|
#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
|
|
|
|
#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
|
|
|
|
#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
|
|
|
|
#define SYS_CLCD_ID_VGA (0x1f << 8)
|
|
|
|
|
2011-01-18 13:12:10 -07:00
|
|
|
static bool is_sanyo_2_5_lcd;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable all display connectors on the interface module.
|
|
|
|
*/
|
|
|
|
static void versatile_clcd_disable(struct clcd_fb *fb)
|
|
|
|
{
|
2005-09-28 17:09:02 -06:00
|
|
|
void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
|
2005-04-16 16:20:36 -06:00
|
|
|
u32 val;
|
|
|
|
|
|
|
|
val = readl(sys_clcd);
|
|
|
|
val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
|
|
|
|
writel(val, sys_clcd);
|
|
|
|
|
|
|
|
#ifdef CONFIG_MACH_VERSATILE_AB
|
|
|
|
/*
|
|
|
|
* If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
|
|
|
|
*/
|
2011-01-18 13:12:10 -07:00
|
|
|
if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
|
2005-09-28 17:09:02 -06:00
|
|
|
void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
|
2005-04-16 16:20:36 -06:00
|
|
|
unsigned long ctrl;
|
|
|
|
|
|
|
|
ctrl = readl(versatile_ib2_ctrl);
|
|
|
|
ctrl &= ~0x01;
|
|
|
|
writel(ctrl, versatile_ib2_ctrl);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable the relevant connector on the interface module.
|
|
|
|
*/
|
|
|
|
static void versatile_clcd_enable(struct clcd_fb *fb)
|
|
|
|
{
|
2011-01-19 16:29:12 -07:00
|
|
|
struct fb_var_screeninfo *var = &fb->fb.var;
|
2005-09-28 17:09:02 -06:00
|
|
|
void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
|
2005-04-16 16:20:36 -06:00
|
|
|
u32 val;
|
|
|
|
|
|
|
|
val = readl(sys_clcd);
|
|
|
|
val &= ~SYS_CLCD_MODE_MASK;
|
|
|
|
|
2011-01-19 16:29:12 -07:00
|
|
|
switch (var->green.length) {
|
2005-04-16 16:20:36 -06:00
|
|
|
case 5:
|
|
|
|
val |= SYS_CLCD_MODE_5551;
|
|
|
|
break;
|
|
|
|
case 6:
|
2011-01-19 16:29:12 -07:00
|
|
|
if (var->red.offset == 0)
|
|
|
|
val |= SYS_CLCD_MODE_565_RLSB;
|
|
|
|
else
|
|
|
|
val |= SYS_CLCD_MODE_565_BLSB;
|
2005-04-16 16:20:36 -06:00
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
val |= SYS_CLCD_MODE_888;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set the MUX
|
|
|
|
*/
|
|
|
|
writel(val, sys_clcd);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* And now enable the PSUs
|
|
|
|
*/
|
|
|
|
val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
|
|
|
|
writel(val, sys_clcd);
|
|
|
|
|
|
|
|
#ifdef CONFIG_MACH_VERSATILE_AB
|
|
|
|
/*
|
|
|
|
* If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
|
|
|
|
*/
|
2011-01-18 13:12:10 -07:00
|
|
|
if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
|
2005-09-28 17:09:02 -06:00
|
|
|
void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
|
2005-04-16 16:20:36 -06:00
|
|
|
unsigned long ctrl;
|
|
|
|
|
|
|
|
ctrl = readl(versatile_ib2_ctrl);
|
|
|
|
ctrl |= 0x01;
|
|
|
|
writel(ctrl, versatile_ib2_ctrl);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2011-01-18 13:12:10 -07:00
|
|
|
/*
|
|
|
|
* Detect which LCD panel is connected, and return the appropriate
|
|
|
|
* clcd_panel structure. Note: we do not have any information on
|
|
|
|
* the required timings for the 8.4in panel, so we presently assume
|
|
|
|
* VGA timings.
|
|
|
|
*/
|
2005-04-16 16:20:36 -06:00
|
|
|
static int versatile_clcd_setup(struct clcd_fb *fb)
|
|
|
|
{
|
2011-01-18 13:12:10 -07:00
|
|
|
void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
|
|
|
|
const char *panel_name;
|
|
|
|
u32 val;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2011-01-18 13:12:10 -07:00
|
|
|
is_sanyo_2_5_lcd = false;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2011-01-18 13:12:10 -07:00
|
|
|
val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
|
|
|
|
if (val == SYS_CLCD_ID_SANYO_3_8)
|
|
|
|
panel_name = "Sanyo TM38QV67A02A";
|
|
|
|
else if (val == SYS_CLCD_ID_SANYO_2_5) {
|
|
|
|
panel_name = "Sanyo QVGA Portrait";
|
|
|
|
is_sanyo_2_5_lcd = true;
|
|
|
|
} else if (val == SYS_CLCD_ID_EPSON_2_2)
|
|
|
|
panel_name = "Epson L2F50113T00";
|
|
|
|
else if (val == SYS_CLCD_ID_VGA)
|
|
|
|
panel_name = "VGA";
|
|
|
|
else {
|
|
|
|
printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
|
|
|
|
val);
|
|
|
|
panel_name = "VGA";
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
2011-01-18 13:12:10 -07:00
|
|
|
fb->panel = versatile_clcd_get_panel(panel_name);
|
|
|
|
if (!fb->panel)
|
|
|
|
return -EINVAL;
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2011-01-18 13:12:10 -07:00
|
|
|
return versatile_clcd_setup_dma(fb, SZ_1M);
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|
|
|
|
|
2011-01-19 16:29:12 -07:00
|
|
|
static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
|
|
|
|
{
|
|
|
|
clcdfb_decode(fb, regs);
|
|
|
|
|
|
|
|
/* Always clear BGR for RGB565: we do the routing externally */
|
|
|
|
if (fb->fb.var.green.length == 6)
|
|
|
|
regs->cntl &= ~CNTL_BGR;
|
|
|
|
}
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
static struct clcd_board clcd_plat_data = {
|
|
|
|
.name = "Versatile",
|
2011-01-18 13:12:10 -07:00
|
|
|
.caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
|
2005-04-16 16:20:36 -06:00
|
|
|
.check = clcdfb_check,
|
2011-01-19 16:29:12 -07:00
|
|
|
.decode = versatile_clcd_decode,
|
2005-04-16 16:20:36 -06:00
|
|
|
.disable = versatile_clcd_disable,
|
|
|
|
.enable = versatile_clcd_enable,
|
|
|
|
.setup = versatile_clcd_setup,
|
2011-01-18 13:12:10 -07:00
|
|
|
.mmap = versatile_clcd_mmap_dma,
|
|
|
|
.remove = versatile_clcd_remove_dma,
|
2005-04-16 16:20:36 -06:00
|
|
|
};
|
|
|
|
|
2009-07-05 15:43:01 -06:00
|
|
|
static struct pl061_platform_data gpio0_plat_data = {
|
|
|
|
.gpio_base = 0,
|
|
|
|
.irq_base = IRQ_GPIO0_START,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct pl061_platform_data gpio1_plat_data = {
|
|
|
|
.gpio_base = 8,
|
|
|
|
.irq_base = IRQ_GPIO1_START,
|
|
|
|
};
|
|
|
|
|
2013-11-27 05:04:23 -07:00
|
|
|
static struct pl061_platform_data gpio2_plat_data = {
|
|
|
|
.gpio_base = 16,
|
|
|
|
.irq_base = IRQ_GPIO2_START,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct pl061_platform_data gpio3_plat_data = {
|
|
|
|
.gpio_base = 24,
|
|
|
|
.irq_base = IRQ_GPIO3_START,
|
|
|
|
};
|
|
|
|
|
2010-07-14 16:59:27 -06:00
|
|
|
static struct pl022_ssp_controller ssp0_plat_data = {
|
|
|
|
.bus_id = 0,
|
|
|
|
.enable_dma = 0,
|
|
|
|
.num_chipselect = 1,
|
|
|
|
};
|
|
|
|
|
2011-12-18 04:40:46 -07:00
|
|
|
#define AACI_IRQ { IRQ_AACI }
|
2005-04-16 16:20:36 -06:00
|
|
|
#define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
|
2011-12-18 04:40:46 -07:00
|
|
|
#define KMI0_IRQ { IRQ_SIC_KMI0 }
|
|
|
|
#define KMI1_IRQ { IRQ_SIC_KMI1 }
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* These devices are connected directly to the multi-layer AHB switch
|
|
|
|
*/
|
2011-12-18 04:40:46 -07:00
|
|
|
#define SMC_IRQ { }
|
|
|
|
#define MPMC_IRQ { }
|
|
|
|
#define CLCD_IRQ { IRQ_CLCDINT }
|
|
|
|
#define DMAC_IRQ { IRQ_DMAINT }
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* These devices are connected via the core APB bridge
|
|
|
|
*/
|
2011-12-18 04:40:46 -07:00
|
|
|
#define SCTL_IRQ { }
|
|
|
|
#define WATCHDOG_IRQ { IRQ_WDOGINT }
|
|
|
|
#define GPIO0_IRQ { IRQ_GPIOINT0 }
|
|
|
|
#define GPIO1_IRQ { IRQ_GPIOINT1 }
|
2013-11-27 05:04:23 -07:00
|
|
|
#define GPIO2_IRQ { IRQ_GPIOINT2 }
|
|
|
|
#define GPIO3_IRQ { IRQ_GPIOINT3 }
|
2011-12-18 04:40:46 -07:00
|
|
|
#define RTC_IRQ { IRQ_RTCINT }
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* These devices are connected via the DMA APB bridge
|
|
|
|
*/
|
2011-12-18 04:40:46 -07:00
|
|
|
#define SCI_IRQ { IRQ_SCIINT }
|
|
|
|
#define UART0_IRQ { IRQ_UARTINT0 }
|
|
|
|
#define UART1_IRQ { IRQ_UARTINT1 }
|
|
|
|
#define UART2_IRQ { IRQ_UARTINT2 }
|
|
|
|
#define SSP_IRQ { IRQ_SSPINT }
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/* FPGA Primecells */
|
2011-12-18 05:21:09 -07:00
|
|
|
APB_DEVICE(aaci, "fpga:04", AACI, NULL);
|
|
|
|
APB_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
|
|
|
|
APB_DEVICE(kmi0, "fpga:06", KMI0, NULL);
|
|
|
|
APB_DEVICE(kmi1, "fpga:07", KMI1, NULL);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
/* DevChip Primecells */
|
2011-12-18 05:21:09 -07:00
|
|
|
AHB_DEVICE(smc, "dev:00", SMC, NULL);
|
|
|
|
AHB_DEVICE(mpmc, "dev:10", MPMC, NULL);
|
|
|
|
AHB_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
|
|
|
|
AHB_DEVICE(dmac, "dev:30", DMAC, NULL);
|
|
|
|
APB_DEVICE(sctl, "dev:e0", SCTL, NULL);
|
|
|
|
APB_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
|
|
|
|
APB_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
|
|
|
|
APB_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
|
2013-11-27 05:04:23 -07:00
|
|
|
APB_DEVICE(gpio2, "dev:e6", GPIO2, &gpio2_plat_data);
|
|
|
|
APB_DEVICE(gpio3, "dev:e7", GPIO3, &gpio3_plat_data);
|
2011-12-18 05:21:09 -07:00
|
|
|
APB_DEVICE(rtc, "dev:e8", RTC, NULL);
|
|
|
|
APB_DEVICE(sci0, "dev:f0", SCI, NULL);
|
|
|
|
APB_DEVICE(uart0, "dev:f1", UART0, NULL);
|
|
|
|
APB_DEVICE(uart1, "dev:f2", UART1, NULL);
|
|
|
|
APB_DEVICE(uart2, "dev:f3", UART2, NULL);
|
|
|
|
APB_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
static struct amba_device *amba_devs[] __initdata = {
|
|
|
|
&dmac_device,
|
|
|
|
&uart0_device,
|
|
|
|
&uart1_device,
|
|
|
|
&uart2_device,
|
|
|
|
&smc_device,
|
|
|
|
&mpmc_device,
|
|
|
|
&clcd_device,
|
|
|
|
&sctl_device,
|
|
|
|
&wdog_device,
|
|
|
|
&gpio0_device,
|
|
|
|
&gpio1_device,
|
2013-11-27 05:04:23 -07:00
|
|
|
&gpio2_device,
|
|
|
|
&gpio3_device,
|
2005-04-16 16:20:36 -06:00
|
|
|
&rtc_device,
|
|
|
|
&sci0_device,
|
|
|
|
&ssp0_device,
|
|
|
|
&aaci_device,
|
|
|
|
&mmc0_device,
|
|
|
|
&kmi0_device,
|
|
|
|
&kmi1_device,
|
|
|
|
};
|
|
|
|
|
2011-07-26 03:19:06 -06:00
|
|
|
#ifdef CONFIG_OF
|
|
|
|
/*
|
|
|
|
* Lookup table for attaching a specific name and platform_data pointer to
|
|
|
|
* devices as they get created by of_platform_populate(). Ideally this table
|
|
|
|
* would not exist, but the current clock implementation depends on some devices
|
|
|
|
* having a specific name.
|
|
|
|
*/
|
|
|
|
struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
|
2012-04-18 15:27:28 -06:00
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data),
|
2011-07-26 03:19:06 -06:00
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL),
|
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
|
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
|
2012-04-18 15:27:28 -06:00
|
|
|
/* FIXME: this is buggy, the platform data is needed for this MMC instance too */
|
2011-07-26 03:19:06 -06:00
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
|
|
|
|
|
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
|
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
|
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
|
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
|
2012-04-18 15:27:28 -06:00
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", &ssp0_plat_data),
|
2011-07-26 03:19:06 -06:00
|
|
|
|
|
|
|
#if 0
|
|
|
|
/*
|
|
|
|
* These entries are unnecessary because no clocks referencing
|
|
|
|
* them. I've left them in for now as place holders in case
|
|
|
|
* any of them need to be added back, but they should be
|
|
|
|
* removed before actually committing this patch. --gcl
|
|
|
|
*/
|
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_AACI_BASE, "fpga:04", NULL),
|
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI1_BASE, "fpga:0a", NULL),
|
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_SMC_BASE, "dev:00", NULL),
|
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_MPMC_BASE, "dev:10", NULL),
|
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_DMAC_BASE, "dev:30", NULL),
|
|
|
|
|
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCTL_BASE, "dev:e0", NULL),
|
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_WATCHDOG_BASE, "dev:e1", NULL),
|
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO0_BASE, "dev:e4", NULL),
|
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO1_BASE, "dev:e5", NULL),
|
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO2_BASE, "dev:e6", NULL),
|
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO3_BASE, "dev:e7", NULL),
|
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_RTC_BASE, "dev:e8", NULL),
|
|
|
|
OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI_BASE, "dev:f0", NULL),
|
|
|
|
#endif
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
#ifdef CONFIG_LEDS
|
2005-09-28 17:09:02 -06:00
|
|
|
#define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
static void versatile_leds_event(led_event_t ledevt)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
local_irq_save(flags);
|
|
|
|
val = readl(VA_LEDS_BASE);
|
|
|
|
|
|
|
|
switch (ledevt) {
|
|
|
|
case led_idle_start:
|
|
|
|
val = val & ~VERSATILE_SYS_LED0;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case led_idle_end:
|
|
|
|
val = val | VERSATILE_SYS_LED0;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case led_timer:
|
|
|
|
val = val ^ VERSATILE_SYS_LED1;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case led_halted:
|
|
|
|
val = 0;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
writel(val, VA_LEDS_BASE);
|
|
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_LEDS */
|
|
|
|
|
2013-07-08 17:01:40 -06:00
|
|
|
void versatile_restart(enum reboot_mode mode, const char *cmd)
|
2011-11-03 05:43:08 -06:00
|
|
|
{
|
|
|
|
void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
val = __raw_readl(sys + VERSATILE_SYS_RESETCTL_OFFSET);
|
|
|
|
val |= 0x105;
|
|
|
|
|
|
|
|
__raw_writel(0xa05f, sys + VERSATILE_SYS_LOCK_OFFSET);
|
|
|
|
__raw_writel(val, sys + VERSATILE_SYS_RESETCTL_OFFSET);
|
|
|
|
__raw_writel(0, sys + VERSATILE_SYS_LOCK_OFFSET);
|
|
|
|
}
|
|
|
|
|
2011-01-11 05:55:38 -07:00
|
|
|
/* Early initializations */
|
|
|
|
void __init versatile_init_early(void)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
2013-03-13 16:07:44 -06:00
|
|
|
u32 val;
|
2011-01-11 05:55:38 -07:00
|
|
|
void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
|
2010-01-14 13:09:34 -07:00
|
|
|
|
2011-01-11 05:55:38 -07:00
|
|
|
osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
|
2010-01-12 05:28:00 -07:00
|
|
|
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
2005-04-16 16:20:36 -06:00
|
|
|
|
2011-01-11 05:55:38 -07:00
|
|
|
versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
|
2013-03-13 16:07:44 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* set clock frequency:
|
|
|
|
* VERSATILE_REFCLK is 32KHz
|
|
|
|
* VERSATILE_TIMCLK is 1MHz
|
|
|
|
*/
|
|
|
|
val = readl(__io_address(VERSATILE_SCTL_BASE));
|
|
|
|
writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
|
|
|
|
(VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
|
|
|
|
(VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
|
|
|
|
(VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
|
|
|
|
__io_address(VERSATILE_SCTL_BASE));
|
2011-01-11 05:55:38 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
void __init versatile_init(void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
platform_device_register(&versatile_flash_device);
|
2006-12-10 13:21:32 -07:00
|
|
|
platform_device_register(&versatile_i2c_device);
|
2005-04-16 16:20:36 -06:00
|
|
|
platform_device_register(&smc91x_device);
|
2010-07-17 05:34:25 -06:00
|
|
|
platform_device_register(&char_lcd_device);
|
2014-02-27 06:29:22 -07:00
|
|
|
platform_device_register(&leds_device);
|
2005-04-16 16:20:36 -06:00
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
|
|
|
|
struct amba_device *d = amba_devs[i];
|
|
|
|
amba_device_register(d, &iomem_resource);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Where is the timer (VA)?
|
|
|
|
*/
|
2005-09-28 17:09:02 -06:00
|
|
|
#define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
|
|
|
|
#define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
|
|
|
|
#define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
|
|
|
|
#define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
|
2007-03-08 12:25:13 -07:00
|
|
|
|
2005-04-16 16:20:36 -06:00
|
|
|
/*
|
|
|
|
* Set up timer interrupt, and return the current time in seconds.
|
|
|
|
*/
|
2012-11-08 12:40:59 -07:00
|
|
|
void __init versatile_timer_init(void)
|
2005-04-16 16:20:36 -06:00
|
|
|
{
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialise to a known state (all timers off)
|
|
|
|
*/
|
2005-06-29 08:15:54 -06:00
|
|
|
writel(0, TIMER0_VA_BASE + TIMER_CTRL);
|
|
|
|
writel(0, TIMER1_VA_BASE + TIMER_CTRL);
|
|
|
|
writel(0, TIMER2_VA_BASE + TIMER_CTRL);
|
|
|
|
writel(0, TIMER3_VA_BASE + TIMER_CTRL);
|
|
|
|
|
2011-05-12 05:08:23 -06:00
|
|
|
sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
|
2011-05-12 08:31:13 -06:00
|
|
|
sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
|
2005-04-16 16:20:36 -06:00
|
|
|
}
|