2010-02-28 10:26:25 -07:00
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/*
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* Versatile Express Core Tile Cortex A9x4 Support
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*/
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#include <linux/init.h>
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2010-03-29 11:52:45 -06:00
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#include <linux/gfp.h>
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2010-02-28 10:26:25 -07:00
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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2010-04-15 03:16:26 -06:00
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#include <linux/platform_device.h>
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2010-02-28 10:26:25 -07:00
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#include <linux/amba/bus.h>
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#include <linux/amba/clcd.h>
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2010-11-17 02:04:33 -07:00
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#include <linux/clkdev.h>
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2012-10-09 05:56:36 -06:00
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#include <linux/vexpress.h>
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2012-12-27 12:10:24 -07:00
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#include <linux/irqchip/arm-gic.h>
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2010-02-28 10:26:25 -07:00
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#include <asm/hardware/arm_timer.h>
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#include <asm/hardware/cache-l2x0.h>
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2011-02-28 09:01:04 -07:00
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#include <asm/smp_scu.h>
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2010-07-09 06:52:09 -06:00
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#include <asm/smp_twd.h>
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2010-02-28 10:26:25 -07:00
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#include <mach/ct-ca9x4.h>
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2010-10-06 09:18:08 -06:00
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#include <asm/hardware/timer-sp.h>
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2010-02-28 10:26:25 -07:00
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include "core.h"
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#include <mach/motherboard.h>
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2012-05-07 10:54:40 -06:00
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#include <mach/irqs.h>
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2010-02-28 10:26:25 -07:00
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2011-01-18 13:13:51 -07:00
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#include <plat/clcd.h>
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2010-02-28 10:26:25 -07:00
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static struct map_desc ct_ca9x4_io_desc[] __initdata = {
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{
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2012-01-25 08:37:29 -07:00
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.virtual = V2T_PERIPH,
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.pfn = __phys_to_pfn(CT_CA9X4_MPIC),
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.length = SZ_8K,
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.type = MT_DEVICE,
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2010-02-28 10:26:25 -07:00
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},
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};
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static void __init ct_ca9x4_map_io(void)
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{
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2012-01-25 08:37:29 -07:00
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iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
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2010-02-28 10:26:25 -07:00
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}
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2014-03-19 05:15:38 -06:00
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static void __init ca9x4_l2_init(void)
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{
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#ifdef CONFIG_CACHE_L2X0
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void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
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if (l2x0_base) {
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/* set RAM latencies to 1 cycle for this core tile. */
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writel(0, l2x0_base + L310_TAG_LATENCY_CTRL);
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writel(0, l2x0_base + L310_DATA_LATENCY_CTRL);
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l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
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} else {
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pr_err("L2C: unable to map L2 cache controller\n");
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}
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#endif
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}
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2011-08-04 04:57:04 -06:00
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#ifdef CONFIG_HAVE_ARM_TWD
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static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);
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static void __init ca9x4_twd_init(void)
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{
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int err = twd_local_timer_register(&twd_local_timer);
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if (err)
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pr_err("twd_local_timer_register failed %d\n", err);
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}
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#else
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#define ca9x4_twd_init() do {} while(0)
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#endif
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2010-02-28 10:26:25 -07:00
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static void __init ct_ca9x4_init_irq(void)
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{
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2012-01-25 08:37:29 -07:00
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gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
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ioremap(A9_MPCORE_GIC_CPU, SZ_256));
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2011-08-04 04:57:04 -06:00
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ca9x4_twd_init();
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2014-03-19 05:15:38 -06:00
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ca9x4_l2_init();
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2010-02-28 10:26:25 -07:00
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}
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static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
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{
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unsigned long framesize = 1024 * 768 * 2;
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2011-01-18 13:13:51 -07:00
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fb->panel = versatile_clcd_get_panel("XVGA");
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if (!fb->panel)
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return -EINVAL;
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2010-02-28 10:26:25 -07:00
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2011-01-18 13:13:51 -07:00
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return versatile_clcd_setup_dma(fb, framesize);
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2010-02-28 10:26:25 -07:00
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}
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static struct clcd_board ct_ca9x4_clcd_data = {
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.name = "CT-CA9X4",
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2011-01-18 13:13:51 -07:00
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.caps = CLCD_CAP_5551 | CLCD_CAP_565,
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2010-02-28 10:26:25 -07:00
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.check = clcdfb_check,
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.decode = clcdfb_decode,
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.setup = ct_ca9x4_clcd_setup,
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2011-01-18 13:13:51 -07:00
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.mmap = versatile_clcd_mmap_dma,
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.remove = versatile_clcd_remove_dma,
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2010-02-28 10:26:25 -07:00
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};
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2011-12-18 05:07:09 -07:00
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static AMBA_AHB_DEVICE(clcd, "ct:clcd", 0, CT_CA9X4_CLCDC, IRQ_CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
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static AMBA_APB_DEVICE(dmc, "ct:dmc", 0, CT_CA9X4_DMC, IRQ_CT_CA9X4_DMC, NULL);
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static AMBA_APB_DEVICE(smc, "ct:smc", 0, CT_CA9X4_SMC, IRQ_CT_CA9X4_SMC, NULL);
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static AMBA_APB_DEVICE(gpio, "ct:gpio", 0, CT_CA9X4_GPIO, IRQ_CT_CA9X4_GPIO, NULL);
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2010-02-28 10:26:25 -07:00
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static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
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&clcd_device,
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&dmc_device,
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&smc_device,
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&gpio_device,
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};
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2010-04-15 03:16:26 -06:00
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static struct resource pmu_resources[] = {
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[0] = {
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.start = IRQ_CT_CA9X4_PMU_CPU0,
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.end = IRQ_CT_CA9X4_PMU_CPU0,
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.flags = IORESOURCE_IRQ,
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},
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[1] = {
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.start = IRQ_CT_CA9X4_PMU_CPU1,
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.end = IRQ_CT_CA9X4_PMU_CPU1,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = IRQ_CT_CA9X4_PMU_CPU2,
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.end = IRQ_CT_CA9X4_PMU_CPU2,
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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.start = IRQ_CT_CA9X4_PMU_CPU3,
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.end = IRQ_CT_CA9X4_PMU_CPU3,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device pmu_device = {
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.name = "arm-pmu",
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2012-07-19 02:50:21 -06:00
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.id = -1,
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2010-04-15 03:16:26 -06:00
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.num_resources = ARRAY_SIZE(pmu_resources),
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.resource = pmu_resources,
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};
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mfd: vexpress: Convert custom func API to regmap
Components of the Versatile Express platform (configuration
microcontrollers on motherboard and daughterboards in particular)
talk to each other over a custom configuration bus. They
provide miscellaneous functions (from clock generator control
to energy sensors) which are represented as platform devices
(and Device Tree nodes). The transactions on the bus can
be generated by different "bridges" in the system, some
of which are universal for the whole platform (for the price
of high transfer latencies), others restricted to a subsystem
(but much faster).
Until now drivers for such functions were using custom "func"
API, which is being replaced in this patch by regmap calls.
This required:
* a rework (and move to drivers/bus directory, as suggested
by Samuel and Arnd) of the config bus core, which is much
simpler now and uses device model infrastructure (class)
to keep track of the bridges; non-DT case (soon to be
retired anyway) is simply covered by a special device
registration function
* the new config-bus driver also takes over device population,
so there is no need for special matching table for
of_platform_populate nor "simple-bus" hack in the arm64
model dtsi file (relevant bindings documentation has
been updated); this allows all the vexpress devices
fit into normal device model, making it possible
to remove plenty of early inits and other hacks in
the near future
* adaptation of the syscfg bridge implementation in the
sysreg driver, again making it much simpler; there is
a special case of the "energy" function spanning two
registers, where they should be both defined in the tree
now, but backward compatibility is maintained in the code
* modification of the relevant drivers:
* hwmon - just a straight-forward API change
* power/reset driver - API change
* regulator - API change plus error handling
simplification
* osc clock driver - this one required larger rework
in order to turn in into a standard platform driver
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Mark Brown <broonie@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Mike Turquette <mturquette@linaro.org>
2014-04-30 09:46:29 -06:00
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static struct clk_lookup osc1_lookup = {
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.dev_id = "ct:clcd",
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};
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2012-10-09 05:56:36 -06:00
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static struct platform_device osc1_device = {
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.name = "vexpress-osc",
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.id = 1,
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.num_resources = 1,
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.resource = (struct resource []) {
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VEXPRESS_RES_FUNC(0xf, 1),
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},
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mfd: vexpress: Convert custom func API to regmap
Components of the Versatile Express platform (configuration
microcontrollers on motherboard and daughterboards in particular)
talk to each other over a custom configuration bus. They
provide miscellaneous functions (from clock generator control
to energy sensors) which are represented as platform devices
(and Device Tree nodes). The transactions on the bus can
be generated by different "bridges" in the system, some
of which are universal for the whole platform (for the price
of high transfer latencies), others restricted to a subsystem
(but much faster).
Until now drivers for such functions were using custom "func"
API, which is being replaced in this patch by regmap calls.
This required:
* a rework (and move to drivers/bus directory, as suggested
by Samuel and Arnd) of the config bus core, which is much
simpler now and uses device model infrastructure (class)
to keep track of the bridges; non-DT case (soon to be
retired anyway) is simply covered by a special device
registration function
* the new config-bus driver also takes over device population,
so there is no need for special matching table for
of_platform_populate nor "simple-bus" hack in the arm64
model dtsi file (relevant bindings documentation has
been updated); this allows all the vexpress devices
fit into normal device model, making it possible
to remove plenty of early inits and other hacks in
the near future
* adaptation of the syscfg bridge implementation in the
sysreg driver, again making it much simpler; there is
a special case of the "energy" function spanning two
registers, where they should be both defined in the tree
now, but backward compatibility is maintained in the code
* modification of the relevant drivers:
* hwmon - just a straight-forward API change
* power/reset driver - API change
* regulator - API change plus error handling
simplification
* osc clock driver - this one required larger rework
in order to turn in into a standard platform driver
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Mark Brown <broonie@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Mike Turquette <mturquette@linaro.org>
2014-04-30 09:46:29 -06:00
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.dev.platform_data = &osc1_lookup,
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2012-10-09 05:56:36 -06:00
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};
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2010-10-05 04:29:28 -06:00
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static void __init ct_ca9x4_init(void)
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2010-02-28 10:26:25 -07:00
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
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amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
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2010-04-15 03:16:26 -06:00
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platform_device_register(&pmu_device);
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2014-04-23 03:49:31 -06:00
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vexpress_syscfg_device_register(&osc1_device);
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2010-02-28 10:26:25 -07:00
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}
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2011-02-28 09:01:04 -07:00
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#ifdef CONFIG_SMP
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2012-01-25 08:37:29 -07:00
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static void *ct_ca9x4_scu_base __initdata;
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2012-01-18 12:40:13 -07:00
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static void __init ct_ca9x4_init_cpu_map(void)
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2011-02-28 09:01:04 -07:00
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{
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2012-01-25 08:37:29 -07:00
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int i, ncores;
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ct_ca9x4_scu_base = ioremap(A9_MPCORE_SCU, SZ_128);
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if (WARN_ON(!ct_ca9x4_scu_base))
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return;
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ncores = scu_get_core_count(ct_ca9x4_scu_base);
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2011-02-28 09:01:04 -07:00
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2011-10-20 15:04:18 -06:00
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if (ncores > nr_cpu_ids) {
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pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
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ncores, nr_cpu_ids);
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ncores = nr_cpu_ids;
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}
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2011-02-28 09:01:04 -07:00
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for (i = 0; i < ncores; ++i)
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set_cpu_possible(i, true);
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}
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2012-01-18 12:40:13 -07:00
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static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)
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2011-02-28 09:01:04 -07:00
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{
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2012-01-25 08:37:29 -07:00
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scu_enable(ct_ca9x4_scu_base);
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2011-02-28 09:01:04 -07:00
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}
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#endif
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struct ct_desc ct_ca9x4_desc __initdata = {
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.id = V2M_CT_ID_CA9,
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.name = "CA9x4",
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2010-02-28 10:26:25 -07:00
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.map_io = ct_ca9x4_map_io,
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2011-02-28 09:01:04 -07:00
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.init_irq = ct_ca9x4_init_irq,
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.init_tile = ct_ca9x4_init,
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#ifdef CONFIG_SMP
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.init_cpu_map = ct_ca9x4_init_cpu_map,
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.smp_enable = ct_ca9x4_smp_enable,
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2010-02-28 10:26:25 -07:00
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#endif
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2011-02-28 09:01:04 -07:00
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};
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