2010-09-27 08:50:49 -06:00
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/*
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* Driver for OMAP-UART controller.
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* Based on drivers/serial/8250.c
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*
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* Copyright (C) 2010 Texas Instruments.
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*
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* Authors:
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* Govindraj R <govindraj.raja@ti.com>
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* Thara Gopinath <thara@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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2011-03-30 19:57:33 -06:00
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* Note: This driver is made separate from 8250 driver as we cannot
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2010-09-27 08:50:49 -06:00
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* over load 8250 driver with omap platform specific configuration for
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* features like DMA, it makes easier to implement features like DMA and
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* hardware flow control and software flow control configuration with
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* this driver as required for the omap-platform.
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*/
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2011-02-01 00:30:41 -07:00
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#if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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#define SUPPORT_SYSRQ
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#endif
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2010-09-27 08:50:49 -06:00
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/serial_reg.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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2012-09-06 06:45:38 -06:00
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#include <linux/platform_device.h>
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2010-09-27 08:50:49 -06:00
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/serial_core.h>
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#include <linux/irq.h>
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2011-02-28 05:42:23 -07:00
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#include <linux/pm_runtime.h>
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2015-06-10 00:35:00 -06:00
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#include <linux/pm_wakeirq.h>
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2011-12-14 04:55:45 -07:00
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#include <linux/of.h>
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2013-10-22 07:49:48 -06:00
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#include <linux/of_irq.h>
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2012-07-29 18:30:26 -06:00
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#include <linux/gpio.h>
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2013-08-14 04:29:38 -06:00
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#include <linux/of_gpio.h>
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2012-12-14 10:09:11 -07:00
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#include <linux/platform_data/serial-omap.h>
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2010-09-27 08:50:49 -06:00
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2013-08-14 04:29:38 -06:00
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#include <dt-bindings/gpio/gpio.h>
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2014-10-22 06:46:50 -06:00
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#define OMAP_MAX_HSUART_PORTS 10
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2012-10-06 03:50:58 -06:00
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2012-04-03 07:42:34 -06:00
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#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
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#define OMAP_UART_REV_42 0x0402
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#define OMAP_UART_REV_46 0x0406
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#define OMAP_UART_REV_52 0x0502
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#define OMAP_UART_REV_63 0x0603
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2013-07-05 09:25:59 -06:00
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#define OMAP_UART_TX_WAKEUP_EN BIT(7)
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/* Feature flags */
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#define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
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2012-10-06 03:50:58 -06:00
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#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
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#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
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2014-12-11 14:44:26 -07:00
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#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
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2011-12-14 04:55:44 -07:00
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2012-01-25 19:50:36 -07:00
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/* SCR register bitmasks */
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#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
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2013-02-04 10:19:46 -07:00
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#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
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2012-10-06 03:50:58 -06:00
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#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
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2012-01-25 19:50:36 -07:00
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/* FCR register bitmasks */
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#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
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2012-09-06 06:45:40 -06:00
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#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
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2012-01-25 19:50:36 -07:00
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2012-04-03 07:42:34 -06:00
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/* MVR register bitmasks */
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#define OMAP_UART_MVR_SCHEME_SHIFT 30
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#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
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#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
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#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
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#define OMAP_UART_MVR_MAJ_MASK 0x700
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#define OMAP_UART_MVR_MAJ_SHIFT 8
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#define OMAP_UART_MVR_MIN_MASK 0x3f
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2012-10-06 03:50:58 -06:00
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#define OMAP_UART_DMA_CH_FREE -1
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#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
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#define OMAP_MODE13X_SPEED 230400
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/* WER = 0x7F
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* Enable module level wakeup in WER reg
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*/
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2014-12-11 14:44:26 -07:00
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#define OMAP_UART_WER_MOD_WKUP 0x7F
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2012-10-06 03:50:58 -06:00
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/* Enable XON/XOFF flow control on output */
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2012-10-05 06:32:08 -06:00
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#define OMAP_UART_SW_TX 0x08
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2012-10-06 03:50:58 -06:00
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/* Enable XON/XOFF flow control on input */
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2012-10-05 06:32:08 -06:00
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#define OMAP_UART_SW_RX 0x02
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2012-10-06 03:50:58 -06:00
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#define OMAP_UART_SW_CLR 0xF0
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#define OMAP_UART_TCR_TRIG 0x0F
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struct uart_omap_dma {
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u8 uart_dma_tx;
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u8 uart_dma_rx;
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int rx_dma_channel;
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int tx_dma_channel;
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dma_addr_t rx_buf_dma_phys;
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dma_addr_t tx_buf_dma_phys;
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unsigned int uart_base;
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/*
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2014-12-11 14:44:26 -07:00
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* Buffer for rx dma. It is not required for tx because the buffer
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2012-10-06 03:50:58 -06:00
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* comes from port structure.
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*/
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unsigned char *rx_buf;
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unsigned int prev_rx_dma_pos;
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int tx_buf_size;
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int tx_dma_used;
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int rx_dma_used;
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spinlock_t tx_lock;
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spinlock_t rx_lock;
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/* timer to poll activity on rx dma */
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struct timer_list rx_timer;
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unsigned int rx_buf_size;
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unsigned int rx_poll_rate;
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unsigned int rx_timeout;
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};
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2012-09-06 06:45:39 -06:00
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struct uart_omap_port {
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struct uart_port port;
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struct uart_omap_dma uart_dma;
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struct device *dev;
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2013-10-22 07:49:48 -06:00
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int wakeirq;
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2012-09-06 06:45:39 -06:00
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unsigned char ier;
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unsigned char lcr;
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unsigned char mcr;
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unsigned char fcr;
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unsigned char efr;
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unsigned char dll;
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unsigned char dlh;
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unsigned char mdr1;
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unsigned char scr;
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2013-07-05 09:25:59 -06:00
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unsigned char wer;
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2012-09-06 06:45:39 -06:00
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int use_dma;
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/*
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* Some bits in registers are cleared on a read, so they must
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2014-12-11 14:44:26 -07:00
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* be saved whenever the register is read, but the bits will not
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2012-09-06 06:45:39 -06:00
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* be immediately processed.
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*/
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unsigned int lsr_break_flag;
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unsigned char msr_saved_flags;
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char name[20];
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unsigned long port_activity;
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2012-10-03 05:54:36 -06:00
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int context_loss_cnt;
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2012-09-06 06:45:39 -06:00
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u32 errata;
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2013-07-05 09:25:59 -06:00
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u32 features;
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2012-09-06 06:45:39 -06:00
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2013-08-14 04:29:38 -06:00
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int rts_gpio;
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2012-09-06 06:45:39 -06:00
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struct pm_qos_request pm_qos_request;
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u32 latency;
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u32 calc_latency;
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struct work_struct qos_work;
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2013-05-15 09:35:38 -06:00
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bool is_suspending;
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2012-09-06 06:45:39 -06:00
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};
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2013-10-23 16:49:59 -06:00
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#define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
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2012-09-06 06:45:39 -06:00
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2010-09-27 08:50:49 -06:00
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static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
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/* Forward declaration of functions */
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2011-11-07 06:30:33 -07:00
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static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
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2010-09-27 08:50:49 -06:00
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static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
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{
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offset <<= up->port.regshift;
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return readw(up->port.membase + offset);
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}
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static inline void serial_out(struct uart_omap_port *up, int offset, int value)
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{
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offset <<= up->port.regshift;
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writew(value, up->port.membase + offset);
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}
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static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
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{
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serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
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serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
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UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
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serial_out(up, UART_FCR, 0);
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}
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2012-08-23 04:32:42 -06:00
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static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
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{
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2013-07-30 02:06:57 -06:00
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struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
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2012-08-23 04:32:42 -06:00
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2012-09-07 12:10:33 -06:00
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if (!pdata || !pdata->get_context_loss_count)
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2013-06-10 08:39:09 -06:00
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return -EINVAL;
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2012-08-23 04:32:42 -06:00
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2012-09-06 06:45:20 -06:00
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return pdata->get_context_loss_count(up->dev);
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2012-08-23 04:32:42 -06:00
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}
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2015-06-10 00:35:00 -06:00
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/* REVISIT: Remove this when omap3 boots in device tree only mode */
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2012-08-23 04:32:42 -06:00
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static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
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{
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2013-07-30 02:06:57 -06:00
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struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
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2012-08-23 04:32:42 -06:00
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2012-09-07 12:10:33 -06:00
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if (!pdata || !pdata->enable_wakeup)
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return;
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pdata->enable_wakeup(up->dev, enable);
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2012-08-23 04:32:42 -06:00
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}
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2014-09-24 01:55:22 -06:00
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/*
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* Calculate the absolute difference between the desired and actual baud
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* rate for the given mode.
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*/
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static inline int calculate_baud_abs_diff(struct uart_port *port,
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unsigned int baud, unsigned int mode)
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{
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unsigned int n = port->uartclk / (mode * baud);
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int abs_diff;
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if (n == 0)
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n = 1;
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abs_diff = baud - (port->uartclk / (mode * n));
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if (abs_diff < 0)
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abs_diff = -abs_diff;
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return abs_diff;
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}
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OMAP/serial: Support 1Mbaud and similar baudrates that require Mode16 instead of Mode13
Original table in OMAP TRM named "UART Mode Baud Rates, Divisor
Values, and Error Rates" determines modes not for all common baud
rates. E.g. for 1000000 baud rate mode should be 16x, but according to
that table it's determined as 13x. According to current implementation
of mode divisor selection, after requesting 1000000 baudrate from
driver, later one will configure chip to use MODE13 divisor. Assuming
48Mhz as common UART clock speed, MODE13 divisor will effectively give
1230769 baudrate, what is quite far from desired 1000000 baudrate.
While with MODE16 divisor, chip will produce exact 1000000 baudrate.
In old driver that served UART devices (8250.c and serial_core.c) this
divisor could have been configured by user-space program, but in
omap_serial.c driver implementation this ability was not implemented
(afaik, by design) thus disallowing proper usage of MODE16-compatible
baudrates.
Signed-off-by: Alexey Pelykh <alexey.pelykh@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-01-16 03:08:06 -07:00
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/*
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* serial_omap_baud_is_mode16 - check if baud rate is MODE16X
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* @port: uart port info
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* @baud: baudrate for which mode needs to be determined
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*
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* Returns true if baud rate is MODE16X and false if MODE13X
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* Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
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* and Error Rates" determines modes not for all common baud rates.
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* E.g. for 1000000 baud rate mode must be 16x, but according to that
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* table it's determined as 13x.
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*/
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static bool
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serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
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{
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2014-09-24 01:55:22 -06:00
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int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
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int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
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return (abs_diff_13 >= abs_diff_16);
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OMAP/serial: Support 1Mbaud and similar baudrates that require Mode16 instead of Mode13
Original table in OMAP TRM named "UART Mode Baud Rates, Divisor
Values, and Error Rates" determines modes not for all common baud
rates. E.g. for 1000000 baud rate mode should be 16x, but according to
that table it's determined as 13x. According to current implementation
of mode divisor selection, after requesting 1000000 baudrate from
driver, later one will configure chip to use MODE13 divisor. Assuming
48Mhz as common UART clock speed, MODE13 divisor will effectively give
1230769 baudrate, what is quite far from desired 1000000 baudrate.
While with MODE16 divisor, chip will produce exact 1000000 baudrate.
In old driver that served UART devices (8250.c and serial_core.c) this
divisor could have been configured by user-space program, but in
omap_serial.c driver implementation this ability was not implemented
(afaik, by design) thus disallowing proper usage of MODE16-compatible
baudrates.
Signed-off-by: Alexey Pelykh <alexey.pelykh@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-01-16 03:08:06 -07:00
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}
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2010-09-27 08:50:49 -06:00
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/*
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* serial_omap_get_divisor - calculate divisor value
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* @port: uart port info
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* @baud: baudrate for which divisor needs to be calculated.
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*/
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static unsigned int
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serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
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{
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2013-09-21 02:04:35 -06:00
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unsigned int mode;
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2010-09-27 08:50:49 -06:00
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|
OMAP/serial: Support 1Mbaud and similar baudrates that require Mode16 instead of Mode13
Original table in OMAP TRM named "UART Mode Baud Rates, Divisor
Values, and Error Rates" determines modes not for all common baud
rates. E.g. for 1000000 baud rate mode should be 16x, but according to
that table it's determined as 13x. According to current implementation
of mode divisor selection, after requesting 1000000 baudrate from
driver, later one will configure chip to use MODE13 divisor. Assuming
48Mhz as common UART clock speed, MODE13 divisor will effectively give
1230769 baudrate, what is quite far from desired 1000000 baudrate.
While with MODE16 divisor, chip will produce exact 1000000 baudrate.
In old driver that served UART devices (8250.c and serial_core.c) this
divisor could have been configured by user-space program, but in
omap_serial.c driver implementation this ability was not implemented
(afaik, by design) thus disallowing proper usage of MODE16-compatible
baudrates.
Signed-off-by: Alexey Pelykh <alexey.pelykh@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-01-16 03:08:06 -07:00
|
|
|
if (!serial_omap_baud_is_mode16(port, baud))
|
2013-09-21 02:04:35 -06:00
|
|
|
mode = 13;
|
2010-09-27 08:50:49 -06:00
|
|
|
else
|
2013-09-21 02:04:35 -06:00
|
|
|
mode = 16;
|
|
|
|
return port->uartclk/(mode * baud);
|
2010-09-27 08:50:49 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void serial_omap_enable_ms(struct uart_port *port)
|
|
|
|
{
|
2012-08-23 04:32:41 -06:00
|
|
|
struct uart_omap_port *up = to_uart_omap_port(port);
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2011-12-14 04:55:43 -07:00
|
|
|
dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
|
2011-02-28 05:42:23 -07:00
|
|
|
|
2012-09-06 06:45:20 -06:00
|
|
|
pm_runtime_get_sync(up->dev);
|
2010-09-27 08:50:49 -06:00
|
|
|
up->ier |= UART_IER_MSI;
|
|
|
|
serial_out(up, UART_IER, up->ier);
|
2012-09-06 06:45:26 -06:00
|
|
|
pm_runtime_mark_last_busy(up->dev);
|
|
|
|
pm_runtime_put_autosuspend(up->dev);
|
2010-09-27 08:50:49 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void serial_omap_stop_tx(struct uart_port *port)
|
|
|
|
{
|
2012-08-23 04:32:41 -06:00
|
|
|
struct uart_omap_port *up = to_uart_omap_port(port);
|
2013-08-14 04:29:38 -06:00
|
|
|
int res;
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2012-09-06 06:45:20 -06:00
|
|
|
pm_runtime_get_sync(up->dev);
|
2013-08-14 04:29:38 -06:00
|
|
|
|
2013-10-23 16:49:58 -06:00
|
|
|
/* Handle RS-485 */
|
2014-11-06 14:46:14 -07:00
|
|
|
if (port->rs485.flags & SER_RS485_ENABLED) {
|
2013-10-23 16:49:58 -06:00
|
|
|
if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
|
|
|
|
/* THR interrupt is fired when both TX FIFO and TX
|
|
|
|
* shift register are empty. This means there's nothing
|
|
|
|
* left to transmit now, so make sure the THR interrupt
|
|
|
|
* is fired when TX FIFO is below the trigger level,
|
|
|
|
* disable THR interrupts and toggle the RS-485 GPIO
|
|
|
|
* data direction pin if needed.
|
|
|
|
*/
|
|
|
|
up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
|
|
|
|
serial_out(up, UART_OMAP_SCR, up->scr);
|
2014-11-06 14:46:14 -07:00
|
|
|
res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
|
|
|
|
1 : 0;
|
2013-08-14 04:29:38 -06:00
|
|
|
if (gpio_get_value(up->rts_gpio) != res) {
|
2014-11-06 14:46:14 -07:00
|
|
|
if (port->rs485.delay_rts_after_send > 0)
|
|
|
|
mdelay(
|
|
|
|
port->rs485.delay_rts_after_send);
|
2013-08-14 04:29:38 -06:00
|
|
|
gpio_set_value(up->rts_gpio, res);
|
|
|
|
}
|
2013-10-23 16:49:58 -06:00
|
|
|
} else {
|
|
|
|
/* We're asked to stop, but there's still stuff in the
|
|
|
|
* UART FIFO, so make sure the THR interrupt is fired
|
|
|
|
* when both TX FIFO and TX shift register are empty.
|
|
|
|
* The next THR interrupt (if no transmission is started
|
|
|
|
* in the meantime) will indicate the end of a
|
|
|
|
* transmission. Therefore we _don't_ disable THR
|
|
|
|
* interrupts in this situation.
|
|
|
|
*/
|
|
|
|
up->scr |= OMAP_UART_SCR_TX_EMPTY;
|
|
|
|
serial_out(up, UART_OMAP_SCR, up->scr);
|
|
|
|
return;
|
2013-08-14 04:29:38 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-09-27 08:50:49 -06:00
|
|
|
if (up->ier & UART_IER_THRI) {
|
|
|
|
up->ier &= ~UART_IER_THRI;
|
|
|
|
serial_out(up, UART_IER, up->ier);
|
|
|
|
}
|
2011-02-28 05:42:23 -07:00
|
|
|
|
2014-11-06 14:46:14 -07:00
|
|
|
if ((port->rs485.flags & SER_RS485_ENABLED) &&
|
|
|
|
!(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
|
2014-03-13 07:11:47 -06:00
|
|
|
/*
|
|
|
|
* Empty the RX FIFO, we are not interested in anything
|
|
|
|
* received during the half-duplex transmission.
|
|
|
|
*/
|
|
|
|
serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR);
|
|
|
|
/* Re-enable RX interrupts */
|
2014-03-13 07:11:46 -06:00
|
|
|
up->ier |= UART_IER_RLSI | UART_IER_RDI;
|
|
|
|
up->port.read_status_mask |= UART_LSR_DR;
|
2013-08-14 04:29:38 -06:00
|
|
|
serial_out(up, UART_IER, up->ier);
|
|
|
|
}
|
|
|
|
|
2012-09-06 06:45:20 -06:00
|
|
|
pm_runtime_mark_last_busy(up->dev);
|
|
|
|
pm_runtime_put_autosuspend(up->dev);
|
2010-09-27 08:50:49 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void serial_omap_stop_rx(struct uart_port *port)
|
|
|
|
{
|
2012-08-23 04:32:41 -06:00
|
|
|
struct uart_omap_port *up = to_uart_omap_port(port);
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2012-09-06 06:45:20 -06:00
|
|
|
pm_runtime_get_sync(up->dev);
|
2014-03-13 07:11:46 -06:00
|
|
|
up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
|
2010-09-27 08:50:49 -06:00
|
|
|
up->port.read_status_mask &= ~UART_LSR_DR;
|
|
|
|
serial_out(up, UART_IER, up->ier);
|
2012-09-06 06:45:20 -06:00
|
|
|
pm_runtime_mark_last_busy(up->dev);
|
|
|
|
pm_runtime_put_autosuspend(up->dev);
|
2010-09-27 08:50:49 -06:00
|
|
|
}
|
|
|
|
|
2012-09-06 06:45:25 -06:00
|
|
|
static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
|
2010-09-27 08:50:49 -06:00
|
|
|
{
|
|
|
|
struct circ_buf *xmit = &up->port.state->xmit;
|
|
|
|
int count;
|
|
|
|
|
|
|
|
if (up->port.x_char) {
|
|
|
|
serial_out(up, UART_TX, up->port.x_char);
|
|
|
|
up->port.icount.tx++;
|
|
|
|
up->port.x_char = 0;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
|
|
|
|
serial_omap_stop_tx(&up->port);
|
|
|
|
return;
|
|
|
|
}
|
2013-08-27 17:02:18 -06:00
|
|
|
count = up->port.fifosize / 4;
|
2010-09-27 08:50:49 -06:00
|
|
|
do {
|
|
|
|
serial_out(up, UART_TX, xmit->buf[xmit->tail]);
|
|
|
|
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
|
|
|
|
up->port.icount.tx++;
|
|
|
|
if (uart_circ_empty(xmit))
|
|
|
|
break;
|
|
|
|
} while (--count > 0);
|
|
|
|
|
2014-04-23 08:58:27 -06:00
|
|
|
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
|
2010-09-27 08:50:49 -06:00
|
|
|
uart_write_wakeup(&up->port);
|
|
|
|
|
|
|
|
if (uart_circ_empty(xmit))
|
|
|
|
serial_omap_stop_tx(&up->port);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
|
|
|
|
{
|
|
|
|
if (!(up->ier & UART_IER_THRI)) {
|
|
|
|
up->ier |= UART_IER_THRI;
|
|
|
|
serial_out(up, UART_IER, up->ier);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void serial_omap_start_tx(struct uart_port *port)
|
|
|
|
{
|
2012-08-23 04:32:41 -06:00
|
|
|
struct uart_omap_port *up = to_uart_omap_port(port);
|
2013-08-14 04:29:38 -06:00
|
|
|
int res;
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2012-09-06 06:45:21 -06:00
|
|
|
pm_runtime_get_sync(up->dev);
|
2013-08-14 04:29:38 -06:00
|
|
|
|
2013-10-23 16:49:58 -06:00
|
|
|
/* Handle RS-485 */
|
2014-11-06 14:46:14 -07:00
|
|
|
if (port->rs485.flags & SER_RS485_ENABLED) {
|
2013-10-23 16:49:58 -06:00
|
|
|
/* Fire THR interrupts when FIFO is below trigger level */
|
|
|
|
up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
|
|
|
|
serial_out(up, UART_OMAP_SCR, up->scr);
|
|
|
|
|
2013-08-14 04:29:38 -06:00
|
|
|
/* if rts not already enabled */
|
2014-11-06 14:46:14 -07:00
|
|
|
res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
|
2013-08-14 04:29:38 -06:00
|
|
|
if (gpio_get_value(up->rts_gpio) != res) {
|
|
|
|
gpio_set_value(up->rts_gpio, res);
|
2014-11-06 14:46:14 -07:00
|
|
|
if (port->rs485.delay_rts_before_send > 0)
|
|
|
|
mdelay(port->rs485.delay_rts_before_send);
|
2013-08-14 04:29:38 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-11-06 14:46:14 -07:00
|
|
|
if ((port->rs485.flags & SER_RS485_ENABLED) &&
|
|
|
|
!(port->rs485.flags & SER_RS485_RX_DURING_TX))
|
2013-08-14 04:29:38 -06:00
|
|
|
serial_omap_stop_rx(port);
|
|
|
|
|
2012-09-06 06:45:21 -06:00
|
|
|
serial_omap_enable_ier_thri(up);
|
|
|
|
pm_runtime_mark_last_busy(up->dev);
|
|
|
|
pm_runtime_put_autosuspend(up->dev);
|
2010-09-27 08:50:49 -06:00
|
|
|
}
|
|
|
|
|
2012-10-05 06:32:08 -06:00
|
|
|
static void serial_omap_throttle(struct uart_port *port)
|
|
|
|
{
|
|
|
|
struct uart_omap_port *up = to_uart_omap_port(port);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
pm_runtime_get_sync(up->dev);
|
|
|
|
spin_lock_irqsave(&up->port.lock, flags);
|
|
|
|
up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
|
|
|
|
serial_out(up, UART_IER, up->ier);
|
|
|
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
|
|
|
pm_runtime_mark_last_busy(up->dev);
|
|
|
|
pm_runtime_put_autosuspend(up->dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void serial_omap_unthrottle(struct uart_port *port)
|
|
|
|
{
|
|
|
|
struct uart_omap_port *up = to_uart_omap_port(port);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
pm_runtime_get_sync(up->dev);
|
|
|
|
spin_lock_irqsave(&up->port.lock, flags);
|
|
|
|
up->ier |= UART_IER_RLSI | UART_IER_RDI;
|
|
|
|
serial_out(up, UART_IER, up->ier);
|
|
|
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
|
|
|
pm_runtime_mark_last_busy(up->dev);
|
|
|
|
pm_runtime_put_autosuspend(up->dev);
|
|
|
|
}
|
|
|
|
|
2010-09-27 08:50:49 -06:00
|
|
|
static unsigned int check_modem_status(struct uart_omap_port *up)
|
|
|
|
{
|
|
|
|
unsigned int status;
|
|
|
|
|
|
|
|
status = serial_in(up, UART_MSR);
|
|
|
|
status |= up->msr_saved_flags;
|
|
|
|
up->msr_saved_flags = 0;
|
|
|
|
if ((status & UART_MSR_ANY_DELTA) == 0)
|
|
|
|
return status;
|
|
|
|
|
|
|
|
if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
|
|
|
|
up->port.state != NULL) {
|
|
|
|
if (status & UART_MSR_TERI)
|
|
|
|
up->port.icount.rng++;
|
|
|
|
if (status & UART_MSR_DDSR)
|
|
|
|
up->port.icount.dsr++;
|
|
|
|
if (status & UART_MSR_DDCD)
|
|
|
|
uart_handle_dcd_change
|
|
|
|
(&up->port, status & UART_MSR_DCD);
|
|
|
|
if (status & UART_MSR_DCTS)
|
|
|
|
uart_handle_cts_change
|
|
|
|
(&up->port, status & UART_MSR_CTS);
|
|
|
|
wake_up_interruptible(&up->port.state->port.delta_msr_wait);
|
|
|
|
}
|
|
|
|
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
2012-09-06 06:45:24 -06:00
|
|
|
static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
|
|
|
|
{
|
|
|
|
unsigned int flag;
|
2012-09-21 08:37:19 -06:00
|
|
|
unsigned char ch = 0;
|
|
|
|
|
|
|
|
if (likely(lsr & UART_LSR_DR))
|
|
|
|
ch = serial_in(up, UART_RX);
|
2012-09-06 06:45:24 -06:00
|
|
|
|
|
|
|
up->port.icount.rx++;
|
|
|
|
flag = TTY_NORMAL;
|
|
|
|
|
|
|
|
if (lsr & UART_LSR_BI) {
|
|
|
|
flag = TTY_BREAK;
|
|
|
|
lsr &= ~(UART_LSR_FE | UART_LSR_PE);
|
|
|
|
up->port.icount.brk++;
|
|
|
|
/*
|
|
|
|
* We do the SysRQ and SAK checking
|
|
|
|
* here because otherwise the break
|
|
|
|
* may get masked by ignore_status_mask
|
|
|
|
* or read_status_mask.
|
|
|
|
*/
|
|
|
|
if (uart_handle_break(&up->port))
|
|
|
|
return;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
if (lsr & UART_LSR_PE) {
|
|
|
|
flag = TTY_PARITY;
|
|
|
|
up->port.icount.parity++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (lsr & UART_LSR_FE) {
|
|
|
|
flag = TTY_FRAME;
|
|
|
|
up->port.icount.frame++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (lsr & UART_LSR_OE)
|
|
|
|
up->port.icount.overrun++;
|
|
|
|
|
|
|
|
#ifdef CONFIG_SERIAL_OMAP_CONSOLE
|
|
|
|
if (up->port.line == up->port.cons->index) {
|
|
|
|
/* Recover the break flag from console xmit */
|
|
|
|
lsr |= up->lsr_break_flag;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
|
|
|
|
{
|
|
|
|
unsigned char ch = 0;
|
|
|
|
unsigned int flag;
|
|
|
|
|
|
|
|
if (!(lsr & UART_LSR_DR))
|
|
|
|
return;
|
|
|
|
|
|
|
|
ch = serial_in(up, UART_RX);
|
|
|
|
flag = TTY_NORMAL;
|
|
|
|
up->port.icount.rx++;
|
|
|
|
|
|
|
|
if (uart_handle_sysrq_char(&up->port, ch))
|
|
|
|
return;
|
|
|
|
|
|
|
|
uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
|
|
|
|
}
|
|
|
|
|
2010-09-27 08:50:49 -06:00
|
|
|
/**
|
|
|
|
* serial_omap_irq() - This handles the interrupt from one port
|
|
|
|
* @irq: uart port irq number
|
|
|
|
* @dev_id: uart port info
|
|
|
|
*/
|
2012-09-06 06:45:33 -06:00
|
|
|
static irqreturn_t serial_omap_irq(int irq, void *dev_id)
|
2010-09-27 08:50:49 -06:00
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{
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struct uart_omap_port *up = dev_id;
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unsigned int iir, lsr;
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2012-09-06 06:45:23 -06:00
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unsigned int type;
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2013-08-27 16:59:53 -06:00
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irqreturn_t ret = IRQ_NONE;
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2012-09-06 06:45:24 -06:00
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int max_count = 256;
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2010-09-27 08:50:49 -06:00
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2012-09-06 06:45:30 -06:00
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spin_lock(&up->port.lock);
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2012-09-06 06:45:20 -06:00
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pm_runtime_get_sync(up->dev);
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2012-09-06 06:45:24 -06:00
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do {
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2012-09-06 06:45:23 -06:00
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iir = serial_in(up, UART_IIR);
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2012-09-06 06:45:24 -06:00
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if (iir & UART_IIR_NO_INT)
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break;
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2013-08-27 16:59:53 -06:00
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ret = IRQ_HANDLED;
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2012-09-06 06:45:24 -06:00
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lsr = serial_in(up, UART_LSR);
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/* extract IRQ type from IIR register */
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type = iir & 0x3e;
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switch (type) {
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case UART_IIR_MSI:
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check_modem_status(up);
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break;
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case UART_IIR_THRI:
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2012-09-06 06:45:25 -06:00
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transmit_chars(up, lsr);
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2012-09-06 06:45:24 -06:00
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break;
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case UART_IIR_RX_TIMEOUT:
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/* FALLTHROUGH */
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case UART_IIR_RDI:
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serial_omap_rdi(up, lsr);
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break;
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case UART_IIR_RLSI:
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serial_omap_rlsi(up, lsr);
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break;
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case UART_IIR_CTS_RTS_DSR:
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/* simply try again */
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break;
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case UART_IIR_XOFF:
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/* FALLTHROUGH */
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default:
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break;
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}
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} while (!(iir & UART_IIR_NO_INT) && max_count--);
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2010-09-27 08:50:49 -06:00
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2012-09-06 06:45:30 -06:00
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spin_unlock(&up->port.lock);
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2012-09-06 06:45:24 -06:00
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2013-01-03 07:53:06 -07:00
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tty_flip_buffer_push(&up->port.state->port);
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2012-09-06 06:45:24 -06:00
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2012-09-06 06:45:20 -06:00
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pm_runtime_mark_last_busy(up->dev);
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pm_runtime_put_autosuspend(up->dev);
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2010-09-27 08:50:49 -06:00
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up->port_activity = jiffies;
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2012-09-06 06:45:23 -06:00
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2013-08-27 16:59:53 -06:00
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return ret;
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2010-09-27 08:50:49 -06:00
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}
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static unsigned int serial_omap_tx_empty(struct uart_port *port)
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{
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2012-08-23 04:32:41 -06:00
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struct uart_omap_port *up = to_uart_omap_port(port);
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2010-09-27 08:50:49 -06:00
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unsigned long flags = 0;
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unsigned int ret = 0;
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2012-09-06 06:45:20 -06:00
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pm_runtime_get_sync(up->dev);
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2011-12-14 04:55:43 -07:00
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dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
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2010-09-27 08:50:49 -06:00
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spin_lock_irqsave(&up->port.lock, flags);
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ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
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spin_unlock_irqrestore(&up->port.lock, flags);
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2012-09-06 06:45:26 -06:00
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pm_runtime_mark_last_busy(up->dev);
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pm_runtime_put_autosuspend(up->dev);
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2010-09-27 08:50:49 -06:00
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return ret;
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}
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static unsigned int serial_omap_get_mctrl(struct uart_port *port)
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{
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2012-08-23 04:32:41 -06:00
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struct uart_omap_port *up = to_uart_omap_port(port);
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2011-11-21 03:13:28 -07:00
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unsigned int status;
|
2010-09-27 08:50:49 -06:00
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unsigned int ret = 0;
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2012-09-06 06:45:20 -06:00
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pm_runtime_get_sync(up->dev);
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2010-09-27 08:50:49 -06:00
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status = check_modem_status(up);
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2012-09-06 06:45:26 -06:00
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pm_runtime_mark_last_busy(up->dev);
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pm_runtime_put_autosuspend(up->dev);
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2011-02-28 05:42:23 -07:00
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2011-12-14 04:55:43 -07:00
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dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
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2010-09-27 08:50:49 -06:00
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if (status & UART_MSR_DCD)
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ret |= TIOCM_CAR;
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if (status & UART_MSR_RI)
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ret |= TIOCM_RNG;
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if (status & UART_MSR_DSR)
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ret |= TIOCM_DSR;
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if (status & UART_MSR_CTS)
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ret |= TIOCM_CTS;
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return ret;
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}
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static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
|
2012-08-23 04:32:41 -06:00
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struct uart_omap_port *up = to_uart_omap_port(port);
|
2015-01-25 12:44:53 -07:00
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unsigned char mcr = 0, old_mcr, lcr;
|
2010-09-27 08:50:49 -06:00
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2011-12-14 04:55:43 -07:00
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dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
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2010-09-27 08:50:49 -06:00
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if (mctrl & TIOCM_RTS)
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mcr |= UART_MCR_RTS;
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if (mctrl & TIOCM_DTR)
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mcr |= UART_MCR_DTR;
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if (mctrl & TIOCM_OUT1)
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mcr |= UART_MCR_OUT1;
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if (mctrl & TIOCM_OUT2)
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mcr |= UART_MCR_OUT2;
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if (mctrl & TIOCM_LOOP)
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mcr |= UART_MCR_LOOP;
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|
2012-09-06 06:45:20 -06:00
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pm_runtime_get_sync(up->dev);
|
2012-10-05 05:23:28 -06:00
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old_mcr = serial_in(up, UART_MCR);
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old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
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UART_MCR_DTR | UART_MCR_RTS);
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up->mcr = old_mcr | mcr;
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2011-11-07 06:27:03 -07:00
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serial_out(up, UART_MCR, up->mcr);
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2015-01-25 12:44:53 -07:00
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/* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */
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lcr = serial_in(up, UART_LCR);
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serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
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if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
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up->efr |= UART_EFR_RTS;
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else
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up->efr &= UART_EFR_RTS;
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serial_out(up, UART_EFR, up->efr);
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serial_out(up, UART_LCR, lcr);
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2012-09-06 06:45:26 -06:00
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pm_runtime_mark_last_busy(up->dev);
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pm_runtime_put_autosuspend(up->dev);
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2010-09-27 08:50:49 -06:00
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}
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static void serial_omap_break_ctl(struct uart_port *port, int break_state)
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{
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2012-08-23 04:32:41 -06:00
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struct uart_omap_port *up = to_uart_omap_port(port);
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2010-09-27 08:50:49 -06:00
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unsigned long flags = 0;
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|
2011-12-14 04:55:43 -07:00
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dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
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2012-09-06 06:45:20 -06:00
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pm_runtime_get_sync(up->dev);
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2010-09-27 08:50:49 -06:00
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spin_lock_irqsave(&up->port.lock, flags);
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if (break_state == -1)
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up->lcr |= UART_LCR_SBC;
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else
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up->lcr &= ~UART_LCR_SBC;
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serial_out(up, UART_LCR, up->lcr);
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spin_unlock_irqrestore(&up->port.lock, flags);
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2012-09-06 06:45:26 -06:00
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pm_runtime_mark_last_busy(up->dev);
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pm_runtime_put_autosuspend(up->dev);
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2010-09-27 08:50:49 -06:00
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}
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static int serial_omap_startup(struct uart_port *port)
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{
|
2012-08-23 04:32:41 -06:00
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struct uart_omap_port *up = to_uart_omap_port(port);
|
2010-09-27 08:50:49 -06:00
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unsigned long flags = 0;
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int retval;
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/*
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* Allocate the IRQ
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*/
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retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
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up->name, up);
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if (retval)
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return retval;
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|
2013-10-22 07:49:48 -06:00
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/* Optional wake-up IRQ */
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if (up->wakeirq) {
|
2015-06-10 00:35:00 -06:00
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retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
|
2013-10-22 07:49:48 -06:00
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if (retval) {
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free_irq(up->port.irq, up);
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return retval;
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}
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}
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|
2011-12-14 04:55:43 -07:00
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dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
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2010-09-27 08:50:49 -06:00
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2012-09-06 06:45:20 -06:00
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pm_runtime_get_sync(up->dev);
|
2010-09-27 08:50:49 -06:00
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/*
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* Clear the FIFO buffers and disable them.
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* (they will be reenabled in set_termios())
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*/
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serial_omap_clear_fifos(up);
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/*
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* Clear the interrupt registers.
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*/
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(void) serial_in(up, UART_LSR);
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if (serial_in(up, UART_LSR) & UART_LSR_DR)
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(void) serial_in(up, UART_RX);
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(void) serial_in(up, UART_IIR);
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(void) serial_in(up, UART_MSR);
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/*
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* Now, initialize the UART
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*/
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serial_out(up, UART_LCR, UART_LCR_WLEN8);
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spin_lock_irqsave(&up->port.lock, flags);
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/*
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* Most PC uarts need OUT2 raised to enable interrupts.
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*/
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up->port.mctrl |= TIOCM_OUT2;
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serial_omap_set_mctrl(&up->port, up->port.mctrl);
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spin_unlock_irqrestore(&up->port.lock, flags);
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up->msr_saved_flags = 0;
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/*
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* Finally, enable interrupts. Note: Modem status interrupts
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* are set via set_termios(), which will be occurring imminently
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* anyway, so we don't enable them here.
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*/
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up->ier = UART_IER_RLSI | UART_IER_RDI;
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serial_out(up, UART_IER, up->ier);
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|
2011-01-24 08:51:22 -07:00
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/* Enable module level wake up */
|
2013-07-05 09:25:59 -06:00
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up->wer = OMAP_UART_WER_MOD_WKUP;
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if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
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up->wer |= OMAP_UART_TX_WAKEUP_EN;
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serial_out(up, UART_OMAP_WER, up->wer);
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2011-01-24 08:51:22 -07:00
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2012-09-06 06:45:20 -06:00
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pm_runtime_mark_last_busy(up->dev);
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pm_runtime_put_autosuspend(up->dev);
|
2010-09-27 08:50:49 -06:00
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up->port_activity = jiffies;
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return 0;
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}
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static void serial_omap_shutdown(struct uart_port *port)
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{
|
2012-08-23 04:32:41 -06:00
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struct uart_omap_port *up = to_uart_omap_port(port);
|
2010-09-27 08:50:49 -06:00
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unsigned long flags = 0;
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|
2011-12-14 04:55:43 -07:00
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dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
|
2011-02-28 05:42:23 -07:00
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|
2012-09-06 06:45:20 -06:00
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pm_runtime_get_sync(up->dev);
|
2010-09-27 08:50:49 -06:00
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/*
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* Disable interrupts from this port
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*/
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up->ier = 0;
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serial_out(up, UART_IER, 0);
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spin_lock_irqsave(&up->port.lock, flags);
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up->port.mctrl &= ~TIOCM_OUT2;
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serial_omap_set_mctrl(&up->port, up->port.mctrl);
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spin_unlock_irqrestore(&up->port.lock, flags);
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/*
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* Disable break condition and FIFOs
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*/
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serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
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serial_omap_clear_fifos(up);
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/*
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* Read data port to reset things, and then free the irq
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*/
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if (serial_in(up, UART_LSR) & UART_LSR_DR)
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(void) serial_in(up, UART_RX);
|
2011-02-28 05:42:23 -07:00
|
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|
2012-09-06 06:45:26 -06:00
|
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pm_runtime_mark_last_busy(up->dev);
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pm_runtime_put_autosuspend(up->dev);
|
2010-09-27 08:50:49 -06:00
|
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|
free_irq(up->port.irq, up);
|
2015-06-10 00:35:00 -06:00
|
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dev_pm_clear_wake_irq(up->dev);
|
2010-09-27 08:50:49 -06:00
|
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|
}
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|
2011-11-09 05:11:21 -07:00
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static void serial_omap_uart_qos_work(struct work_struct *work)
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{
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struct uart_omap_port *up = container_of(work, struct uart_omap_port,
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qos_work);
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pm_qos_update_request(&up->pm_qos_request, up->latency);
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}
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|
2010-09-27 08:50:49 -06:00
|
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static void
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serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
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struct ktermios *old)
|
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|
{
|
2012-08-23 04:32:41 -06:00
|
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|
struct uart_omap_port *up = to_uart_omap_port(port);
|
2010-09-27 08:50:49 -06:00
|
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|
unsigned char cval = 0;
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unsigned long flags = 0;
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unsigned int baud, quot;
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switch (termios->c_cflag & CSIZE) {
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|
case CS5:
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|
cval = UART_LCR_WLEN5;
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|
break;
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|
case CS6:
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|
cval = UART_LCR_WLEN6;
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|
break;
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|
case CS7:
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|
cval = UART_LCR_WLEN7;
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|
break;
|
|
|
|
default:
|
|
|
|
case CS8:
|
|
|
|
cval = UART_LCR_WLEN8;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (termios->c_cflag & CSTOPB)
|
|
|
|
cval |= UART_LCR_STOP;
|
|
|
|
if (termios->c_cflag & PARENB)
|
|
|
|
cval |= UART_LCR_PARITY;
|
|
|
|
if (!(termios->c_cflag & PARODD))
|
|
|
|
cval |= UART_LCR_EPAR;
|
2012-12-06 01:45:04 -07:00
|
|
|
if (termios->c_cflag & CMSPAR)
|
|
|
|
cval |= UART_LCR_SPAR;
|
2010-09-27 08:50:49 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Ask the core to calculate the divisor for us.
|
|
|
|
*/
|
|
|
|
|
|
|
|
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
|
|
|
|
quot = serial_omap_get_divisor(port, baud);
|
|
|
|
|
2011-11-09 05:11:21 -07:00
|
|
|
/* calculate wakeup latency constraint */
|
2012-01-25 19:50:56 -07:00
|
|
|
up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
|
2011-11-09 05:11:21 -07:00
|
|
|
up->latency = up->calc_latency;
|
|
|
|
schedule_work(&up->qos_work);
|
|
|
|
|
2011-11-07 06:27:03 -07:00
|
|
|
up->dll = quot & 0xff;
|
|
|
|
up->dlh = quot >> 8;
|
|
|
|
up->mdr1 = UART_OMAP_MDR1_DISABLE;
|
|
|
|
|
2010-09-27 08:50:49 -06:00
|
|
|
up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
|
|
|
|
UART_FCR_ENABLE_FIFO;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Ok, we're now changing the port state. Do it with
|
|
|
|
* interrupts disabled.
|
|
|
|
*/
|
2012-09-06 06:45:20 -06:00
|
|
|
pm_runtime_get_sync(up->dev);
|
2010-09-27 08:50:49 -06:00
|
|
|
spin_lock_irqsave(&up->port.lock, flags);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Update the per-port timeout.
|
|
|
|
*/
|
|
|
|
uart_update_timeout(port, termios->c_cflag, baud);
|
|
|
|
|
|
|
|
up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
|
|
|
|
if (termios->c_iflag & INPCK)
|
|
|
|
up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
|
|
|
|
if (termios->c_iflag & (BRKINT | PARMRK))
|
|
|
|
up->port.read_status_mask |= UART_LSR_BI;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Characters to ignore
|
|
|
|
*/
|
|
|
|
up->port.ignore_status_mask = 0;
|
|
|
|
if (termios->c_iflag & IGNPAR)
|
|
|
|
up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
|
|
|
|
if (termios->c_iflag & IGNBRK) {
|
|
|
|
up->port.ignore_status_mask |= UART_LSR_BI;
|
|
|
|
/*
|
|
|
|
* If we're ignoring parity and break indicators,
|
|
|
|
* ignore overruns too (for real raw support).
|
|
|
|
*/
|
|
|
|
if (termios->c_iflag & IGNPAR)
|
|
|
|
up->port.ignore_status_mask |= UART_LSR_OE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ignore all characters if CREAD is not set
|
|
|
|
*/
|
|
|
|
if ((termios->c_cflag & CREAD) == 0)
|
|
|
|
up->port.ignore_status_mask |= UART_LSR_DR;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Modem status interrupts
|
|
|
|
*/
|
|
|
|
up->ier &= ~UART_IER_MSI;
|
|
|
|
if (UART_ENABLE_MS(&up->port, termios->c_cflag))
|
|
|
|
up->ier |= UART_IER_MSI;
|
|
|
|
serial_out(up, UART_IER, up->ier);
|
|
|
|
serial_out(up, UART_LCR, cval); /* reset DLAB */
|
2011-11-07 06:27:03 -07:00
|
|
|
up->lcr = cval;
|
2013-02-04 10:19:46 -07:00
|
|
|
up->scr = 0;
|
2010-09-27 08:50:49 -06:00
|
|
|
|
|
|
|
/* FIFOs and DMA Settings */
|
|
|
|
|
|
|
|
/* FCR can be changed only when the
|
|
|
|
* baud clock is not running
|
|
|
|
* DLL_REG and DLH_REG set to 0.
|
|
|
|
*/
|
2010-11-30 15:11:49 -07:00
|
|
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
|
2010-09-27 08:50:49 -06:00
|
|
|
serial_out(up, UART_DLL, 0);
|
|
|
|
serial_out(up, UART_DLM, 0);
|
|
|
|
serial_out(up, UART_LCR, 0);
|
|
|
|
|
2010-11-30 15:11:49 -07:00
|
|
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2012-10-05 06:54:53 -06:00
|
|
|
up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
|
2012-10-05 17:51:17 -06:00
|
|
|
up->efr &= ~UART_EFR_SCD;
|
2010-09-27 08:50:49 -06:00
|
|
|
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
|
|
|
|
|
2010-11-30 15:11:49 -07:00
|
|
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
|
2012-10-05 06:54:53 -06:00
|
|
|
up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
|
2010-09-27 08:50:49 -06:00
|
|
|
serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
|
|
|
|
/* FIFO ENABLE, DMA MODE */
|
2012-01-25 19:50:36 -07:00
|
|
|
|
2013-04-03 12:31:46 -06:00
|
|
|
up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
|
|
|
|
/*
|
|
|
|
* NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
|
|
|
|
* sets Enables the granularity of 1 for TRIGGER RX
|
|
|
|
* level. Along with setting RX FIFO trigger level
|
|
|
|
* to 1 (as noted below, 16 characters) and TLR[3:0]
|
|
|
|
* to zero this will result RX FIFO threshold level
|
|
|
|
* to 1 character, instead of 16 as noted in comment
|
|
|
|
* below.
|
|
|
|
*/
|
|
|
|
|
2012-09-06 06:45:40 -06:00
|
|
|
/* Set receive FIFO threshold to 16 characters and
|
2013-10-23 16:49:58 -06:00
|
|
|
* transmit FIFO threshold to 32 spaces
|
2012-09-06 06:45:40 -06:00
|
|
|
*/
|
2012-09-06 06:45:21 -06:00
|
|
|
up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
|
2012-09-06 06:45:40 -06:00
|
|
|
up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
|
|
|
|
up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
|
|
|
|
UART_FCR_ENABLE_FIFO;
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2012-01-25 19:50:36 -07:00
|
|
|
serial_out(up, UART_FCR, up->fcr);
|
|
|
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
|
|
|
|
2011-11-07 06:27:03 -07:00
|
|
|
serial_out(up, UART_OMAP_SCR, up->scr);
|
|
|
|
|
2012-10-05 06:54:53 -06:00
|
|
|
/* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
|
2010-11-30 15:11:49 -07:00
|
|
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
|
2010-09-27 08:50:49 -06:00
|
|
|
serial_out(up, UART_MCR, up->mcr);
|
2012-10-05 06:54:53 -06:00
|
|
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
|
|
|
serial_out(up, UART_EFR, up->efr);
|
|
|
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
|
2010-09-27 08:50:49 -06:00
|
|
|
|
|
|
|
/* Protocol, Baud Rate, and Interrupt Settings */
|
|
|
|
|
2011-11-07 06:30:33 -07:00
|
|
|
if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
|
|
|
|
serial_omap_mdr1_errataset(up, up->mdr1);
|
|
|
|
else
|
|
|
|
serial_out(up, UART_OMAP_MDR1, up->mdr1);
|
|
|
|
|
2010-11-30 15:11:49 -07:00
|
|
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
2010-09-27 08:50:49 -06:00
|
|
|
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
|
|
|
|
|
|
|
|
serial_out(up, UART_LCR, 0);
|
|
|
|
serial_out(up, UART_IER, 0);
|
2010-11-30 15:11:49 -07:00
|
|
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2011-11-07 06:27:03 -07:00
|
|
|
serial_out(up, UART_DLL, up->dll); /* LS of divisor */
|
|
|
|
serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
|
2010-09-27 08:50:49 -06:00
|
|
|
|
|
|
|
serial_out(up, UART_LCR, 0);
|
|
|
|
serial_out(up, UART_IER, up->ier);
|
2010-11-30 15:11:49 -07:00
|
|
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
2010-09-27 08:50:49 -06:00
|
|
|
|
|
|
|
serial_out(up, UART_EFR, up->efr);
|
|
|
|
serial_out(up, UART_LCR, cval);
|
|
|
|
|
OMAP/serial: Support 1Mbaud and similar baudrates that require Mode16 instead of Mode13
Original table in OMAP TRM named "UART Mode Baud Rates, Divisor
Values, and Error Rates" determines modes not for all common baud
rates. E.g. for 1000000 baud rate mode should be 16x, but according to
that table it's determined as 13x. According to current implementation
of mode divisor selection, after requesting 1000000 baudrate from
driver, later one will configure chip to use MODE13 divisor. Assuming
48Mhz as common UART clock speed, MODE13 divisor will effectively give
1230769 baudrate, what is quite far from desired 1000000 baudrate.
While with MODE16 divisor, chip will produce exact 1000000 baudrate.
In old driver that served UART devices (8250.c and serial_core.c) this
divisor could have been configured by user-space program, but in
omap_serial.c driver implementation this ability was not implemented
(afaik, by design) thus disallowing proper usage of MODE16-compatible
baudrates.
Signed-off-by: Alexey Pelykh <alexey.pelykh@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-01-16 03:08:06 -07:00
|
|
|
if (!serial_omap_baud_is_mode16(port, baud))
|
2011-11-07 06:27:03 -07:00
|
|
|
up->mdr1 = UART_OMAP_MDR1_13X_MODE;
|
2010-09-27 08:50:49 -06:00
|
|
|
else
|
2011-11-07 06:27:03 -07:00
|
|
|
up->mdr1 = UART_OMAP_MDR1_16X_MODE;
|
|
|
|
|
2011-11-07 06:30:33 -07:00
|
|
|
if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
|
|
|
|
serial_omap_mdr1_errataset(up, up->mdr1);
|
|
|
|
else
|
|
|
|
serial_out(up, UART_OMAP_MDR1, up->mdr1);
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2012-10-06 02:34:36 -06:00
|
|
|
/* Configure flow control */
|
2012-10-06 02:12:44 -06:00
|
|
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
2012-10-06 02:34:36 -06:00
|
|
|
|
|
|
|
/* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
|
|
|
|
serial_out(up, UART_XON1, termios->c_cc[VSTART]);
|
|
|
|
serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
|
|
|
|
|
|
|
|
/* Enable access to TCR/TLR */
|
2012-10-06 02:12:44 -06:00
|
|
|
serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
|
|
|
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
|
|
|
|
serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2012-10-06 02:12:44 -06:00
|
|
|
serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
|
2010-09-27 08:50:49 -06:00
|
|
|
|
serial: core: Rework hw-assisted flow control support
hw-assisted flow control support was added to the serial core
in v3.8 with commits,
dba05832cbe4f ("SERIAL: core: add hardware assisted h/w flow control support")
2cbacafd7af0f ("SERIAL: core: add hardware assisted s/w flow control support")
9aba8d5b01119 ("SERIAL: core: add throttle/unthrottle callbacks for hardware
assisted flow control")
Since then, additional requirements for serial core support have arisen.
Specifically,
1. Separate tx and rx flow control settings for UARTs which only support
tx flow control (ie., autoCTS).
2. Disable sw-assisted CTS flow control in autoCTS mode
3. Support for RTS flow control by serial core and userspace in autoRTS mode
Distinguish mode from capability; introduce UPSTAT_AUTORTS, UPSTAT_AUTOCTS
and UPSTAT_AUTOXOFF which, when set by the uart driver, enable serial core
support for hw-assisted rx, hw-assisted tx and hw-assisted in-band/IXOFF
rx flow control, respectively. [Note: hw-assisted in-band/IXON tx flow
control does not require serial core support/intervention and can be
enabled by the uart driver when required.]
These modes must be set/reset in the driver's set_termios() method, based
on termios settings, and thus can be safely queried in any context in which
one of the port lock, port mutex or termios rwsem are held. Set these modes
in the 2 in-tree drivers, omap-serial and 8250_omap, which currently
use UPF_HARD_FLOW/UPF_SOFT_FLOW support.
Retain UPF_HARD_FLOW and UPF_SOFT_FLOW as capabilities; re-define
UPF_HARD_FLOW as both UPF_AUTO_RTS and UPF_AUTO_CTS to allow for distinct
and separate rx and tx flow control capabilities.
Disable sw-assisted CTS flow control when UPSTAT_AUTOCTS is enabled.
Signed-off-by: Peter Hurley <peter@hurleysoftware.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-01-25 12:44:51 -07:00
|
|
|
up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
|
|
|
|
|
2012-10-06 02:12:44 -06:00
|
|
|
if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
|
2015-01-25 12:44:53 -07:00
|
|
|
/* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
|
serial: core: Rework hw-assisted flow control support
hw-assisted flow control support was added to the serial core
in v3.8 with commits,
dba05832cbe4f ("SERIAL: core: add hardware assisted h/w flow control support")
2cbacafd7af0f ("SERIAL: core: add hardware assisted s/w flow control support")
9aba8d5b01119 ("SERIAL: core: add throttle/unthrottle callbacks for hardware
assisted flow control")
Since then, additional requirements for serial core support have arisen.
Specifically,
1. Separate tx and rx flow control settings for UARTs which only support
tx flow control (ie., autoCTS).
2. Disable sw-assisted CTS flow control in autoCTS mode
3. Support for RTS flow control by serial core and userspace in autoRTS mode
Distinguish mode from capability; introduce UPSTAT_AUTORTS, UPSTAT_AUTOCTS
and UPSTAT_AUTOXOFF which, when set by the uart driver, enable serial core
support for hw-assisted rx, hw-assisted tx and hw-assisted in-band/IXOFF
rx flow control, respectively. [Note: hw-assisted in-band/IXON tx flow
control does not require serial core support/intervention and can be
enabled by the uart driver when required.]
These modes must be set/reset in the driver's set_termios() method, based
on termios settings, and thus can be safely queried in any context in which
one of the port lock, port mutex or termios rwsem are held. Set these modes
in the 2 in-tree drivers, omap-serial and 8250_omap, which currently
use UPF_HARD_FLOW/UPF_SOFT_FLOW support.
Retain UPF_HARD_FLOW and UPF_SOFT_FLOW as capabilities; re-define
UPF_HARD_FLOW as both UPF_AUTO_RTS and UPF_AUTO_CTS to allow for distinct
and separate rx and tx flow control capabilities.
Disable sw-assisted CTS flow control when UPSTAT_AUTOCTS is enabled.
Signed-off-by: Peter Hurley <peter@hurleysoftware.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-01-25 12:44:51 -07:00
|
|
|
up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
|
2015-01-25 12:44:53 -07:00
|
|
|
up->efr |= UART_EFR_CTS;
|
2012-10-05 16:48:28 -06:00
|
|
|
} else {
|
|
|
|
/* Disable AUTORTS and AUTOCTS */
|
|
|
|
up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
|
2010-09-27 08:50:49 -06:00
|
|
|
}
|
|
|
|
|
2012-10-15 09:50:59 -06:00
|
|
|
if (up->port.flags & UPF_SOFT_FLOW) {
|
|
|
|
/* clear SW control mode bits */
|
|
|
|
up->efr &= OMAP_UART_SW_CLR;
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2012-10-15 09:50:59 -06:00
|
|
|
/*
|
|
|
|
* IXON Flag:
|
2012-10-05 06:32:08 -06:00
|
|
|
* Enable XON/XOFF flow control on input.
|
|
|
|
* Receiver compares XON1, XOFF1.
|
2012-10-15 09:50:59 -06:00
|
|
|
*/
|
|
|
|
if (termios->c_iflag & IXON)
|
2012-10-05 06:32:08 -06:00
|
|
|
up->efr |= OMAP_UART_SW_RX;
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2012-10-15 09:50:59 -06:00
|
|
|
/*
|
|
|
|
* IXOFF Flag:
|
2012-10-05 06:32:08 -06:00
|
|
|
* Enable XON/XOFF flow control on output.
|
|
|
|
* Transmit XON1, XOFF1
|
2012-10-15 09:50:59 -06:00
|
|
|
*/
|
serial: core: Rework hw-assisted flow control support
hw-assisted flow control support was added to the serial core
in v3.8 with commits,
dba05832cbe4f ("SERIAL: core: add hardware assisted h/w flow control support")
2cbacafd7af0f ("SERIAL: core: add hardware assisted s/w flow control support")
9aba8d5b01119 ("SERIAL: core: add throttle/unthrottle callbacks for hardware
assisted flow control")
Since then, additional requirements for serial core support have arisen.
Specifically,
1. Separate tx and rx flow control settings for UARTs which only support
tx flow control (ie., autoCTS).
2. Disable sw-assisted CTS flow control in autoCTS mode
3. Support for RTS flow control by serial core and userspace in autoRTS mode
Distinguish mode from capability; introduce UPSTAT_AUTORTS, UPSTAT_AUTOCTS
and UPSTAT_AUTOXOFF which, when set by the uart driver, enable serial core
support for hw-assisted rx, hw-assisted tx and hw-assisted in-band/IXOFF
rx flow control, respectively. [Note: hw-assisted in-band/IXON tx flow
control does not require serial core support/intervention and can be
enabled by the uart driver when required.]
These modes must be set/reset in the driver's set_termios() method, based
on termios settings, and thus can be safely queried in any context in which
one of the port lock, port mutex or termios rwsem are held. Set these modes
in the 2 in-tree drivers, omap-serial and 8250_omap, which currently
use UPF_HARD_FLOW/UPF_SOFT_FLOW support.
Retain UPF_HARD_FLOW and UPF_SOFT_FLOW as capabilities; re-define
UPF_HARD_FLOW as both UPF_AUTO_RTS and UPF_AUTO_CTS to allow for distinct
and separate rx and tx flow control capabilities.
Disable sw-assisted CTS flow control when UPSTAT_AUTOCTS is enabled.
Signed-off-by: Peter Hurley <peter@hurleysoftware.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-01-25 12:44:51 -07:00
|
|
|
if (termios->c_iflag & IXOFF) {
|
|
|
|
up->port.status |= UPSTAT_AUTOXOFF;
|
2012-10-05 06:32:08 -06:00
|
|
|
up->efr |= OMAP_UART_SW_TX;
|
serial: core: Rework hw-assisted flow control support
hw-assisted flow control support was added to the serial core
in v3.8 with commits,
dba05832cbe4f ("SERIAL: core: add hardware assisted h/w flow control support")
2cbacafd7af0f ("SERIAL: core: add hardware assisted s/w flow control support")
9aba8d5b01119 ("SERIAL: core: add throttle/unthrottle callbacks for hardware
assisted flow control")
Since then, additional requirements for serial core support have arisen.
Specifically,
1. Separate tx and rx flow control settings for UARTs which only support
tx flow control (ie., autoCTS).
2. Disable sw-assisted CTS flow control in autoCTS mode
3. Support for RTS flow control by serial core and userspace in autoRTS mode
Distinguish mode from capability; introduce UPSTAT_AUTORTS, UPSTAT_AUTOCTS
and UPSTAT_AUTOXOFF which, when set by the uart driver, enable serial core
support for hw-assisted rx, hw-assisted tx and hw-assisted in-band/IXOFF
rx flow control, respectively. [Note: hw-assisted in-band/IXON tx flow
control does not require serial core support/intervention and can be
enabled by the uart driver when required.]
These modes must be set/reset in the driver's set_termios() method, based
on termios settings, and thus can be safely queried in any context in which
one of the port lock, port mutex or termios rwsem are held. Set these modes
in the 2 in-tree drivers, omap-serial and 8250_omap, which currently
use UPF_HARD_FLOW/UPF_SOFT_FLOW support.
Retain UPF_HARD_FLOW and UPF_SOFT_FLOW as capabilities; re-define
UPF_HARD_FLOW as both UPF_AUTO_RTS and UPF_AUTO_CTS to allow for distinct
and separate rx and tx flow control capabilities.
Disable sw-assisted CTS flow control when UPSTAT_AUTOCTS is enabled.
Signed-off-by: Peter Hurley <peter@hurleysoftware.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-01-25 12:44:51 -07:00
|
|
|
}
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2012-10-15 09:50:59 -06:00
|
|
|
/*
|
|
|
|
* IXANY Flag:
|
|
|
|
* Enable any character to restart output.
|
|
|
|
* Operation resumes after receiving any
|
|
|
|
* character after recognition of the XOFF character
|
|
|
|
*/
|
|
|
|
if (termios->c_iflag & IXANY)
|
|
|
|
up->mcr |= UART_MCR_XONANY;
|
|
|
|
else
|
|
|
|
up->mcr &= ~UART_MCR_XONANY;
|
2010-09-27 08:50:49 -06:00
|
|
|
}
|
2012-10-06 02:12:44 -06:00
|
|
|
serial_out(up, UART_MCR, up->mcr);
|
2012-10-06 02:08:20 -06:00
|
|
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
|
|
|
serial_out(up, UART_EFR, up->efr);
|
|
|
|
serial_out(up, UART_LCR, up->lcr);
|
2010-09-27 08:50:49 -06:00
|
|
|
|
|
|
|
serial_omap_set_mctrl(&up->port, up->port.mctrl);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&up->port.lock, flags);
|
2012-09-06 06:45:26 -06:00
|
|
|
pm_runtime_mark_last_busy(up->dev);
|
|
|
|
pm_runtime_put_autosuspend(up->dev);
|
2011-12-14 04:55:43 -07:00
|
|
|
dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
|
2010-09-27 08:50:49 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
serial_omap_pm(struct uart_port *port, unsigned int state,
|
|
|
|
unsigned int oldstate)
|
|
|
|
{
|
2012-08-23 04:32:41 -06:00
|
|
|
struct uart_omap_port *up = to_uart_omap_port(port);
|
2010-09-27 08:50:49 -06:00
|
|
|
unsigned char efr;
|
|
|
|
|
2011-12-14 04:55:43 -07:00
|
|
|
dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
|
2011-02-28 05:42:23 -07:00
|
|
|
|
2012-09-06 06:45:20 -06:00
|
|
|
pm_runtime_get_sync(up->dev);
|
2010-11-30 15:11:49 -07:00
|
|
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
2010-09-27 08:50:49 -06:00
|
|
|
efr = serial_in(up, UART_EFR);
|
|
|
|
serial_out(up, UART_EFR, efr | UART_EFR_ECB);
|
|
|
|
serial_out(up, UART_LCR, 0);
|
|
|
|
|
|
|
|
serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
|
2010-11-30 15:11:49 -07:00
|
|
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
|
2010-09-27 08:50:49 -06:00
|
|
|
serial_out(up, UART_EFR, efr);
|
|
|
|
serial_out(up, UART_LCR, 0);
|
2011-02-28 05:42:23 -07:00
|
|
|
|
2012-09-06 06:45:26 -06:00
|
|
|
pm_runtime_mark_last_busy(up->dev);
|
|
|
|
pm_runtime_put_autosuspend(up->dev);
|
2010-09-27 08:50:49 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void serial_omap_release_port(struct uart_port *port)
|
|
|
|
{
|
|
|
|
dev_dbg(port->dev, "serial_omap_release_port+\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static int serial_omap_request_port(struct uart_port *port)
|
|
|
|
{
|
|
|
|
dev_dbg(port->dev, "serial_omap_request_port+\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void serial_omap_config_port(struct uart_port *port, int flags)
|
|
|
|
{
|
2012-08-23 04:32:41 -06:00
|
|
|
struct uart_omap_port *up = to_uart_omap_port(port);
|
2010-09-27 08:50:49 -06:00
|
|
|
|
|
|
|
dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
|
2011-12-14 04:55:43 -07:00
|
|
|
up->port.line);
|
2010-09-27 08:50:49 -06:00
|
|
|
up->port.type = PORT_OMAP;
|
2012-10-05 06:32:08 -06:00
|
|
|
up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
|
2010-09-27 08:50:49 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
|
|
|
|
{
|
|
|
|
/* we don't want the core code to modify any port params */
|
|
|
|
dev_dbg(port->dev, "serial_omap_verify_port+\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const char *
|
|
|
|
serial_omap_type(struct uart_port *port)
|
|
|
|
{
|
2012-08-23 04:32:41 -06:00
|
|
|
struct uart_omap_port *up = to_uart_omap_port(port);
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2011-12-14 04:55:43 -07:00
|
|
|
dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
|
2010-09-27 08:50:49 -06:00
|
|
|
return up->name;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
|
|
|
|
|
|
|
|
static inline void wait_for_xmitr(struct uart_omap_port *up)
|
|
|
|
{
|
|
|
|
unsigned int status, tmout = 10000;
|
|
|
|
|
|
|
|
/* Wait up to 10ms for the character(s) to be sent. */
|
|
|
|
do {
|
|
|
|
status = serial_in(up, UART_LSR);
|
|
|
|
|
|
|
|
if (status & UART_LSR_BI)
|
|
|
|
up->lsr_break_flag = UART_LSR_BI;
|
|
|
|
|
|
|
|
if (--tmout == 0)
|
|
|
|
break;
|
|
|
|
udelay(1);
|
|
|
|
} while ((status & BOTH_EMPTY) != BOTH_EMPTY);
|
|
|
|
|
|
|
|
/* Wait up to 1s for flow control if necessary */
|
|
|
|
if (up->port.flags & UPF_CONS_FLOW) {
|
|
|
|
tmout = 1000000;
|
|
|
|
for (tmout = 1000000; tmout; tmout--) {
|
|
|
|
unsigned int msr = serial_in(up, UART_MSR);
|
|
|
|
|
|
|
|
up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
|
|
|
|
if (msr & UART_MSR_CTS)
|
|
|
|
break;
|
|
|
|
|
|
|
|
udelay(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-12-05 08:15:10 -07:00
|
|
|
#ifdef CONFIG_CONSOLE_POLL
|
|
|
|
|
|
|
|
static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
|
|
|
|
{
|
2012-08-23 04:32:41 -06:00
|
|
|
struct uart_omap_port *up = to_uart_omap_port(port);
|
2011-02-28 05:42:23 -07:00
|
|
|
|
2012-09-06 06:45:20 -06:00
|
|
|
pm_runtime_get_sync(up->dev);
|
2010-12-05 08:15:10 -07:00
|
|
|
wait_for_xmitr(up);
|
|
|
|
serial_out(up, UART_TX, ch);
|
2012-09-06 06:45:26 -06:00
|
|
|
pm_runtime_mark_last_busy(up->dev);
|
|
|
|
pm_runtime_put_autosuspend(up->dev);
|
2010-12-05 08:15:10 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int serial_omap_poll_get_char(struct uart_port *port)
|
|
|
|
{
|
2012-08-23 04:32:41 -06:00
|
|
|
struct uart_omap_port *up = to_uart_omap_port(port);
|
2011-02-28 05:42:23 -07:00
|
|
|
unsigned int status;
|
2010-12-05 08:15:10 -07:00
|
|
|
|
2012-09-06 06:45:20 -06:00
|
|
|
pm_runtime_get_sync(up->dev);
|
2011-02-28 05:42:23 -07:00
|
|
|
status = serial_in(up, UART_LSR);
|
2012-09-06 06:45:36 -06:00
|
|
|
if (!(status & UART_LSR_DR)) {
|
|
|
|
status = NO_POLL_CHAR;
|
|
|
|
goto out;
|
|
|
|
}
|
2010-12-05 08:15:10 -07:00
|
|
|
|
2011-02-28 05:42:23 -07:00
|
|
|
status = serial_in(up, UART_RX);
|
2012-09-06 06:45:36 -06:00
|
|
|
|
|
|
|
out:
|
2012-09-06 06:45:26 -06:00
|
|
|
pm_runtime_mark_last_busy(up->dev);
|
|
|
|
pm_runtime_put_autosuspend(up->dev);
|
2012-09-06 06:45:36 -06:00
|
|
|
|
2011-02-28 05:42:23 -07:00
|
|
|
return status;
|
2010-12-05 08:15:10 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* CONFIG_CONSOLE_POLL */
|
|
|
|
|
|
|
|
#ifdef CONFIG_SERIAL_OMAP_CONSOLE
|
|
|
|
|
2012-10-03 05:54:38 -06:00
|
|
|
static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
|
2010-12-05 08:15:10 -07:00
|
|
|
|
|
|
|
static struct uart_driver serial_omap_reg;
|
|
|
|
|
2010-09-27 08:50:49 -06:00
|
|
|
static void serial_omap_console_putchar(struct uart_port *port, int ch)
|
|
|
|
{
|
2012-08-23 04:32:41 -06:00
|
|
|
struct uart_omap_port *up = to_uart_omap_port(port);
|
2010-09-27 08:50:49 -06:00
|
|
|
|
|
|
|
wait_for_xmitr(up);
|
|
|
|
serial_out(up, UART_TX, ch);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
serial_omap_console_write(struct console *co, const char *s,
|
|
|
|
unsigned int count)
|
|
|
|
{
|
|
|
|
struct uart_omap_port *up = serial_omap_console_ports[co->index];
|
|
|
|
unsigned long flags;
|
|
|
|
unsigned int ier;
|
|
|
|
int locked = 1;
|
|
|
|
|
2012-09-06 06:45:20 -06:00
|
|
|
pm_runtime_get_sync(up->dev);
|
2011-02-28 05:42:23 -07:00
|
|
|
|
2010-09-27 08:50:49 -06:00
|
|
|
local_irq_save(flags);
|
|
|
|
if (up->port.sysrq)
|
|
|
|
locked = 0;
|
|
|
|
else if (oops_in_progress)
|
|
|
|
locked = spin_trylock(&up->port.lock);
|
|
|
|
else
|
|
|
|
spin_lock(&up->port.lock);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* First save the IER then disable the interrupts
|
|
|
|
*/
|
|
|
|
ier = serial_in(up, UART_IER);
|
|
|
|
serial_out(up, UART_IER, 0);
|
|
|
|
|
|
|
|
uart_console_write(&up->port, s, count, serial_omap_console_putchar);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Finally, wait for transmitter to become empty
|
|
|
|
* and restore the IER
|
|
|
|
*/
|
|
|
|
wait_for_xmitr(up);
|
|
|
|
serial_out(up, UART_IER, ier);
|
|
|
|
/*
|
|
|
|
* The receive handling will happen properly because the
|
|
|
|
* receive ready bit will still be set; it is not cleared
|
|
|
|
* on read. However, modem control will not, we must
|
|
|
|
* call it if we have saved something in the saved flags
|
|
|
|
* while processing with interrupts off.
|
|
|
|
*/
|
|
|
|
if (up->msr_saved_flags)
|
|
|
|
check_modem_status(up);
|
|
|
|
|
2012-09-06 06:45:20 -06:00
|
|
|
pm_runtime_mark_last_busy(up->dev);
|
|
|
|
pm_runtime_put_autosuspend(up->dev);
|
2010-09-27 08:50:49 -06:00
|
|
|
if (locked)
|
|
|
|
spin_unlock(&up->port.lock);
|
|
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __init
|
|
|
|
serial_omap_console_setup(struct console *co, char *options)
|
|
|
|
{
|
|
|
|
struct uart_omap_port *up;
|
|
|
|
int baud = 115200;
|
|
|
|
int bits = 8;
|
|
|
|
int parity = 'n';
|
|
|
|
int flow = 'n';
|
|
|
|
|
|
|
|
if (serial_omap_console_ports[co->index] == NULL)
|
|
|
|
return -ENODEV;
|
|
|
|
up = serial_omap_console_ports[co->index];
|
|
|
|
|
|
|
|
if (options)
|
|
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
|
|
|
|
|
|
return uart_set_options(&up->port, co, baud, parity, bits, flow);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct console serial_omap_console = {
|
|
|
|
.name = OMAP_SERIAL_NAME,
|
|
|
|
.write = serial_omap_console_write,
|
|
|
|
.device = uart_console_device,
|
|
|
|
.setup = serial_omap_console_setup,
|
|
|
|
.flags = CON_PRINTBUFFER,
|
|
|
|
.index = -1,
|
|
|
|
.data = &serial_omap_reg,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void serial_omap_add_console_port(struct uart_omap_port *up)
|
|
|
|
{
|
2011-12-14 04:55:43 -07:00
|
|
|
serial_omap_console_ports[up->port.line] = up;
|
2010-09-27 08:50:49 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
#define OMAP_CONSOLE (&serial_omap_console)
|
|
|
|
|
|
|
|
#else
|
|
|
|
|
|
|
|
#define OMAP_CONSOLE NULL
|
|
|
|
|
|
|
|
static inline void serial_omap_add_console_port(struct uart_omap_port *up)
|
|
|
|
{}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
2013-08-14 04:29:38 -06:00
|
|
|
/* Enable or disable the rs485 support */
|
2014-11-06 14:46:14 -07:00
|
|
|
static int
|
2013-08-14 04:29:38 -06:00
|
|
|
serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
|
|
|
|
{
|
|
|
|
struct uart_omap_port *up = to_uart_omap_port(port);
|
|
|
|
unsigned int mode;
|
|
|
|
int val;
|
|
|
|
|
|
|
|
pm_runtime_get_sync(up->dev);
|
|
|
|
|
|
|
|
/* Disable interrupts from this port */
|
|
|
|
mode = up->ier;
|
|
|
|
up->ier = 0;
|
|
|
|
serial_out(up, UART_IER, 0);
|
|
|
|
|
|
|
|
/* store new config */
|
2014-11-06 14:46:14 -07:00
|
|
|
port->rs485 = *rs485conf;
|
2013-08-14 04:29:38 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Just as a precaution, only allow rs485
|
|
|
|
* to be enabled if the gpio pin is valid
|
|
|
|
*/
|
|
|
|
if (gpio_is_valid(up->rts_gpio)) {
|
|
|
|
/* enable / disable rts */
|
2014-11-06 14:46:14 -07:00
|
|
|
val = (port->rs485.flags & SER_RS485_ENABLED) ?
|
2013-08-14 04:29:38 -06:00
|
|
|
SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
|
2014-11-06 14:46:14 -07:00
|
|
|
val = (port->rs485.flags & val) ? 1 : 0;
|
2013-08-14 04:29:38 -06:00
|
|
|
gpio_set_value(up->rts_gpio, val);
|
|
|
|
} else
|
2014-11-06 14:46:14 -07:00
|
|
|
port->rs485.flags &= ~SER_RS485_ENABLED;
|
2013-08-14 04:29:38 -06:00
|
|
|
|
|
|
|
/* Enable interrupts */
|
|
|
|
up->ier = mode;
|
|
|
|
serial_out(up, UART_IER, up->ier);
|
|
|
|
|
2013-10-23 16:49:58 -06:00
|
|
|
/* If RS-485 is disabled, make sure the THR interrupt is fired when
|
|
|
|
* TX FIFO is below the trigger level.
|
|
|
|
*/
|
2014-11-06 14:46:14 -07:00
|
|
|
if (!(port->rs485.flags & SER_RS485_ENABLED) &&
|
2013-10-23 16:49:58 -06:00
|
|
|
(up->scr & OMAP_UART_SCR_TX_EMPTY)) {
|
|
|
|
up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
|
|
|
|
serial_out(up, UART_OMAP_SCR, up->scr);
|
|
|
|
}
|
|
|
|
|
2013-08-14 04:29:38 -06:00
|
|
|
pm_runtime_mark_last_busy(up->dev);
|
|
|
|
pm_runtime_put_autosuspend(up->dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-09-27 08:50:49 -06:00
|
|
|
static struct uart_ops serial_omap_pops = {
|
|
|
|
.tx_empty = serial_omap_tx_empty,
|
|
|
|
.set_mctrl = serial_omap_set_mctrl,
|
|
|
|
.get_mctrl = serial_omap_get_mctrl,
|
|
|
|
.stop_tx = serial_omap_stop_tx,
|
|
|
|
.start_tx = serial_omap_start_tx,
|
2012-10-05 06:32:08 -06:00
|
|
|
.throttle = serial_omap_throttle,
|
|
|
|
.unthrottle = serial_omap_unthrottle,
|
2010-09-27 08:50:49 -06:00
|
|
|
.stop_rx = serial_omap_stop_rx,
|
|
|
|
.enable_ms = serial_omap_enable_ms,
|
|
|
|
.break_ctl = serial_omap_break_ctl,
|
|
|
|
.startup = serial_omap_startup,
|
|
|
|
.shutdown = serial_omap_shutdown,
|
|
|
|
.set_termios = serial_omap_set_termios,
|
|
|
|
.pm = serial_omap_pm,
|
|
|
|
.type = serial_omap_type,
|
|
|
|
.release_port = serial_omap_release_port,
|
|
|
|
.request_port = serial_omap_request_port,
|
|
|
|
.config_port = serial_omap_config_port,
|
|
|
|
.verify_port = serial_omap_verify_port,
|
2010-12-05 08:15:10 -07:00
|
|
|
#ifdef CONFIG_CONSOLE_POLL
|
|
|
|
.poll_put_char = serial_omap_poll_put_char,
|
|
|
|
.poll_get_char = serial_omap_poll_get_char,
|
|
|
|
#endif
|
2010-09-27 08:50:49 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct uart_driver serial_omap_reg = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.driver_name = "OMAP-SERIAL",
|
|
|
|
.dev_name = OMAP_SERIAL_NAME,
|
|
|
|
.nr = OMAP_MAX_HSUART_PORTS,
|
|
|
|
.cons = OMAP_CONSOLE,
|
|
|
|
};
|
|
|
|
|
2012-01-16 03:22:36 -07:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2013-05-15 09:35:38 -06:00
|
|
|
static int serial_omap_prepare(struct device *dev)
|
|
|
|
{
|
|
|
|
struct uart_omap_port *up = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
up->is_suspending = true;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void serial_omap_complete(struct device *dev)
|
|
|
|
{
|
|
|
|
struct uart_omap_port *up = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
up->is_suspending = false;
|
|
|
|
}
|
|
|
|
|
2011-02-28 05:42:23 -07:00
|
|
|
static int serial_omap_suspend(struct device *dev)
|
2010-09-27 08:50:49 -06:00
|
|
|
{
|
2011-02-28 05:42:23 -07:00
|
|
|
struct uart_omap_port *up = dev_get_drvdata(dev);
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2012-09-18 05:35:54 -06:00
|
|
|
uart_suspend_port(&serial_omap_reg, &up->port);
|
2012-10-02 10:54:49 -06:00
|
|
|
flush_work(&up->qos_work);
|
2011-11-09 05:11:21 -07:00
|
|
|
|
2014-03-25 12:48:47 -06:00
|
|
|
if (device_may_wakeup(dev))
|
|
|
|
serial_omap_enable_wakeup(up, true);
|
|
|
|
else
|
|
|
|
serial_omap_enable_wakeup(up, false);
|
|
|
|
|
2010-09-27 08:50:49 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-02-28 05:42:23 -07:00
|
|
|
static int serial_omap_resume(struct device *dev)
|
2010-09-27 08:50:49 -06:00
|
|
|
{
|
2011-02-28 05:42:23 -07:00
|
|
|
struct uart_omap_port *up = dev_get_drvdata(dev);
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2014-03-25 12:48:47 -06:00
|
|
|
if (device_may_wakeup(dev))
|
|
|
|
serial_omap_enable_wakeup(up, false);
|
|
|
|
|
2012-09-18 05:35:54 -06:00
|
|
|
uart_resume_port(&serial_omap_reg, &up->port);
|
|
|
|
|
2010-09-27 08:50:49 -06:00
|
|
|
return 0;
|
|
|
|
}
|
2013-05-15 09:35:38 -06:00
|
|
|
#else
|
|
|
|
#define serial_omap_prepare NULL
|
2013-06-01 03:18:13 -06:00
|
|
|
#define serial_omap_complete NULL
|
2013-05-15 09:35:38 -06:00
|
|
|
#endif /* CONFIG_PM_SLEEP */
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2012-11-19 11:21:50 -07:00
|
|
|
static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
|
2012-04-03 07:42:34 -06:00
|
|
|
{
|
|
|
|
u32 mvr, scheme;
|
|
|
|
u16 revision, major, minor;
|
|
|
|
|
2013-07-08 01:28:57 -06:00
|
|
|
mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
|
2012-04-03 07:42:34 -06:00
|
|
|
|
|
|
|
/* Check revision register scheme */
|
|
|
|
scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
|
|
|
|
|
|
|
|
switch (scheme) {
|
|
|
|
case 0: /* Legacy Scheme: OMAP2/3 */
|
|
|
|
/* MINOR_REV[0:4], MAJOR_REV[4:7] */
|
|
|
|
major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
|
|
|
|
OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
|
|
|
|
minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
/* New Scheme: OMAP4+ */
|
|
|
|
/* MINOR_REV[0:5], MAJOR_REV[8:10] */
|
|
|
|
major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
|
|
|
|
OMAP_UART_MVR_MAJ_SHIFT;
|
|
|
|
minor = (mvr & OMAP_UART_MVR_MIN_MASK);
|
|
|
|
break;
|
|
|
|
default:
|
2012-09-06 06:45:20 -06:00
|
|
|
dev_warn(up->dev,
|
2012-04-03 07:42:34 -06:00
|
|
|
"Unknown %s revision, defaulting to highest\n",
|
|
|
|
up->name);
|
|
|
|
/* highest possible revision */
|
|
|
|
major = 0xff;
|
|
|
|
minor = 0xff;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* normalize revision for the driver */
|
|
|
|
revision = UART_BUILD_REVISION(major, minor);
|
|
|
|
|
|
|
|
switch (revision) {
|
|
|
|
case OMAP_UART_REV_46:
|
|
|
|
up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
|
|
|
|
UART_ERRATA_i291_DMA_FORCEIDLE);
|
|
|
|
break;
|
|
|
|
case OMAP_UART_REV_52:
|
|
|
|
up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
|
|
|
|
UART_ERRATA_i291_DMA_FORCEIDLE);
|
2013-07-05 09:25:59 -06:00
|
|
|
up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
|
2012-04-03 07:42:34 -06:00
|
|
|
break;
|
|
|
|
case OMAP_UART_REV_63:
|
|
|
|
up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
|
2013-07-05 09:25:59 -06:00
|
|
|
up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
|
2012-04-03 07:42:34 -06:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-11-19 11:21:50 -07:00
|
|
|
static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
|
2011-12-14 04:55:45 -07:00
|
|
|
{
|
|
|
|
struct omap_uart_port_info *omap_up_info;
|
|
|
|
|
|
|
|
omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
|
|
|
|
if (!omap_up_info)
|
|
|
|
return NULL; /* out of memory */
|
|
|
|
|
|
|
|
of_property_read_u32(dev->of_node, "clock-frequency",
|
|
|
|
&omap_up_info->uartclk);
|
|
|
|
return omap_up_info;
|
|
|
|
}
|
|
|
|
|
2013-08-14 04:29:38 -06:00
|
|
|
static int serial_omap_probe_rs485(struct uart_omap_port *up,
|
|
|
|
struct device_node *np)
|
|
|
|
{
|
2014-11-06 14:46:14 -07:00
|
|
|
struct serial_rs485 *rs485conf = &up->port.rs485;
|
2013-08-14 04:29:38 -06:00
|
|
|
u32 rs485_delay[2];
|
|
|
|
enum of_gpio_flags flags;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
rs485conf->flags = 0;
|
|
|
|
up->rts_gpio = -EINVAL;
|
|
|
|
|
|
|
|
if (!np)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (of_property_read_bool(np, "rs485-rts-active-high"))
|
|
|
|
rs485conf->flags |= SER_RS485_RTS_ON_SEND;
|
|
|
|
else
|
|
|
|
rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
|
|
|
|
|
|
|
|
/* check for tx enable gpio */
|
|
|
|
up->rts_gpio = of_get_named_gpio_flags(np, "rts-gpio", 0, &flags);
|
|
|
|
if (gpio_is_valid(up->rts_gpio)) {
|
2014-04-23 08:58:30 -06:00
|
|
|
ret = devm_gpio_request(up->dev, up->rts_gpio, "omap-serial");
|
2013-08-14 04:29:38 -06:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
ret = gpio_direction_output(up->rts_gpio,
|
|
|
|
flags & SER_RS485_RTS_AFTER_SEND);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2014-02-13 02:52:03 -07:00
|
|
|
} else if (up->rts_gpio == -EPROBE_DEFER) {
|
|
|
|
return -EPROBE_DEFER;
|
|
|
|
} else {
|
2013-08-14 04:29:38 -06:00
|
|
|
up->rts_gpio = -EINVAL;
|
2014-02-13 02:52:03 -07:00
|
|
|
}
|
2013-08-14 04:29:38 -06:00
|
|
|
|
|
|
|
if (of_property_read_u32_array(np, "rs485-rts-delay",
|
|
|
|
rs485_delay, 2) == 0) {
|
|
|
|
rs485conf->delay_rts_before_send = rs485_delay[0];
|
|
|
|
rs485conf->delay_rts_after_send = rs485_delay[1];
|
|
|
|
}
|
|
|
|
|
|
|
|
if (of_property_read_bool(np, "rs485-rx-during-tx"))
|
|
|
|
rs485conf->flags |= SER_RS485_RX_DURING_TX;
|
|
|
|
|
|
|
|
if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time"))
|
|
|
|
rs485conf->flags |= SER_RS485_ENABLED;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-11-19 11:21:50 -07:00
|
|
|
static int serial_omap_probe(struct platform_device *pdev)
|
2010-09-27 08:50:49 -06:00
|
|
|
{
|
2013-07-30 02:06:57 -06:00
|
|
|
struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
|
2014-04-23 08:58:31 -06:00
|
|
|
struct uart_omap_port *up;
|
|
|
|
struct resource *mem;
|
2014-04-23 08:58:33 -06:00
|
|
|
void __iomem *base;
|
2014-04-23 08:58:31 -06:00
|
|
|
int uartirq = 0;
|
|
|
|
int wakeirq = 0;
|
|
|
|
int ret;
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2013-10-22 07:49:48 -06:00
|
|
|
/* The optional wakeirq may be specified in the board dts file */
|
2013-07-08 01:25:43 -06:00
|
|
|
if (pdev->dev.of_node) {
|
2013-10-22 07:49:48 -06:00
|
|
|
uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
|
|
|
|
if (!uartirq)
|
|
|
|
return -EPROBE_DEFER;
|
|
|
|
wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
|
2011-12-14 04:55:45 -07:00
|
|
|
omap_up_info = of_get_uart_port_info(&pdev->dev);
|
2013-07-08 01:25:43 -06:00
|
|
|
pdev->dev.platform_data = omap_up_info;
|
2013-10-22 07:49:48 -06:00
|
|
|
} else {
|
2014-04-23 08:58:32 -06:00
|
|
|
uartirq = platform_get_irq(pdev, 0);
|
|
|
|
if (uartirq < 0)
|
|
|
|
return -EPROBE_DEFER;
|
2013-07-08 01:25:43 -06:00
|
|
|
}
|
2011-12-14 04:55:45 -07:00
|
|
|
|
2014-04-23 08:58:33 -06:00
|
|
|
up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
|
|
|
|
if (!up)
|
|
|
|
return -ENOMEM;
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2014-04-23 08:58:33 -06:00
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
base = devm_ioremap_resource(&pdev->dev, mem);
|
|
|
|
if (IS_ERR(base))
|
|
|
|
return PTR_ERR(base);
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2012-09-06 06:45:20 -06:00
|
|
|
up->dev = &pdev->dev;
|
2010-09-27 08:50:49 -06:00
|
|
|
up->port.dev = &pdev->dev;
|
|
|
|
up->port.type = PORT_OMAP;
|
|
|
|
up->port.iotype = UPIO_MEM;
|
2013-10-22 07:49:48 -06:00
|
|
|
up->port.irq = uartirq;
|
2010-09-27 08:50:49 -06:00
|
|
|
up->port.regshift = 2;
|
|
|
|
up->port.fifosize = 64;
|
|
|
|
up->port.ops = &serial_omap_pops;
|
|
|
|
|
2011-12-14 04:55:45 -07:00
|
|
|
if (pdev->dev.of_node)
|
2014-11-12 02:28:34 -07:00
|
|
|
ret = of_alias_get_id(pdev->dev.of_node, "serial");
|
2011-12-14 04:55:45 -07:00
|
|
|
else
|
2014-11-12 02:28:34 -07:00
|
|
|
ret = pdev->id;
|
2011-12-14 04:55:45 -07:00
|
|
|
|
2014-11-12 02:28:34 -07:00
|
|
|
if (ret < 0) {
|
2011-12-14 04:55:45 -07:00
|
|
|
dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
|
2014-11-12 02:28:34 -07:00
|
|
|
ret);
|
2012-03-21 05:52:22 -06:00
|
|
|
goto err_port_line;
|
2011-12-14 04:55:45 -07:00
|
|
|
}
|
2014-11-12 02:28:34 -07:00
|
|
|
up->port.line = ret;
|
2011-12-14 04:55:45 -07:00
|
|
|
|
2014-10-22 06:46:50 -06:00
|
|
|
if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
|
|
|
|
dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line,
|
|
|
|
OMAP_MAX_HSUART_PORTS);
|
|
|
|
ret = -ENXIO;
|
|
|
|
goto err_port_line;
|
|
|
|
}
|
|
|
|
|
tty/serial: omap: fix !wakeirq message
When wakeirq is not used/enabled, "no wakeirq for uart0" is output for
all TTY as the log message is generated before the port line is
initialized.
[ 0.802656] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 0.811700] omap_uart 44e09000.serial: no wakeirq for uart0
[ 0.812379] 44e09000.serial: ttyO0 at MMIO 0x44e09000 (irq = 88, base_baud = 3000000) is a OMAP UART0
[ 1.503622] console [ttyO0] enabled
[ 1.509836] omap_uart 48022000.serial: no wakeirq for uart0
[ 1.516118] 48022000.serial: ttyO1 at MMIO 0x48022000 (irq = 89, base_baud = 3000000) is a OMAP UART1
[ 1.527711] omap_uart 48024000.serial: no wakeirq for uart0
[ 1.533881] 48024000.serial: ttyO2 at MMIO 0x48024000 (irq = 90, base_baud = 3000000) is a OMAP UART2
[ 1.545324] omap_uart 481a6000.serial: no wakeirq for uart0
[ 1.551410] 481a6000.serial: ttyO3 at MMIO 0x481a6000 (irq = 60, base_baud = 3000000) is a OMAP UART3
[ 1.562946] omap_uart 481a8000.serial: no wakeirq for uart0
[ 1.569036] 481a8000.serial: ttyO4 at MMIO 0x481a8000 (irq = 61, base_baud = 3000000) is a OMAP UART4
Fix by moving wakeirq initialization, check, and dev_info() call to
after port line initialization and validation.
Signed-off-by: Doug Kehn <rdkehn@yahoo.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-03-24 07:19:27 -06:00
|
|
|
up->wakeirq = wakeirq;
|
|
|
|
if (!up->wakeirq)
|
|
|
|
dev_info(up->port.dev, "no wakeirq for uart%d\n",
|
|
|
|
up->port.line);
|
|
|
|
|
2013-08-14 04:29:38 -06:00
|
|
|
ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
|
|
|
|
if (ret < 0)
|
|
|
|
goto err_rs485;
|
|
|
|
|
2011-12-14 04:55:45 -07:00
|
|
|
sprintf(up->name, "OMAP UART%d", up->port.line);
|
2011-10-11 03:25:41 -06:00
|
|
|
up->port.mapbase = mem->start;
|
2014-04-23 08:58:33 -06:00
|
|
|
up->port.membase = base;
|
2010-09-27 08:50:49 -06:00
|
|
|
up->port.flags = omap_up_info->flags;
|
|
|
|
up->port.uartclk = omap_up_info->uartclk;
|
2014-11-06 14:46:14 -07:00
|
|
|
up->port.rs485_config = serial_omap_config_rs485;
|
2011-12-14 04:55:44 -07:00
|
|
|
if (!up->port.uartclk) {
|
|
|
|
up->port.uartclk = DEFAULT_CLK_SPEED;
|
2013-10-23 16:49:59 -06:00
|
|
|
dev_warn(&pdev->dev,
|
2013-10-31 07:39:58 -06:00
|
|
|
"No clock speed specified: using default: %d\n",
|
2013-10-23 16:49:59 -06:00
|
|
|
DEFAULT_CLK_SPEED);
|
2011-12-14 04:55:44 -07:00
|
|
|
}
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2011-11-09 05:11:21 -07:00
|
|
|
up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
|
|
|
|
up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
|
|
|
|
pm_qos_add_request(&up->pm_qos_request,
|
|
|
|
PM_QOS_CPU_DMA_LATENCY, up->latency);
|
|
|
|
INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
|
|
|
|
|
2012-09-06 06:45:27 -06:00
|
|
|
platform_set_drvdata(pdev, up);
|
2013-06-10 08:39:09 -06:00
|
|
|
if (omap_up_info->autosuspend_timeout == 0)
|
|
|
|
omap_up_info->autosuspend_timeout = -1;
|
2014-04-23 08:58:29 -06:00
|
|
|
|
2013-06-10 08:39:09 -06:00
|
|
|
device_init_wakeup(up->dev, true);
|
2011-02-28 05:42:23 -07:00
|
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev,
|
2011-11-09 05:03:38 -07:00
|
|
|
omap_up_info->autosuspend_timeout);
|
2011-02-28 05:42:23 -07:00
|
|
|
|
|
|
|
pm_runtime_irq_safe(&pdev->dev);
|
2013-07-22 04:01:15 -06:00
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
|
2011-02-28 05:42:23 -07:00
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
|
|
|
2012-04-03 07:42:34 -06:00
|
|
|
omap_serial_fill_features_erratas(up);
|
|
|
|
|
2011-12-14 04:55:43 -07:00
|
|
|
ui[up->port.line] = up;
|
2010-09-27 08:50:49 -06:00
|
|
|
serial_omap_add_console_port(up);
|
|
|
|
|
|
|
|
ret = uart_add_one_port(&serial_omap_reg, &up->port);
|
|
|
|
if (ret != 0)
|
2012-03-21 05:52:22 -06:00
|
|
|
goto err_add_port;
|
2010-09-27 08:50:49 -06:00
|
|
|
|
2012-09-06 06:45:26 -06:00
|
|
|
pm_runtime_mark_last_busy(up->dev);
|
|
|
|
pm_runtime_put_autosuspend(up->dev);
|
2010-09-27 08:50:49 -06:00
|
|
|
return 0;
|
2012-03-21 05:52:22 -06:00
|
|
|
|
|
|
|
err_add_port:
|
|
|
|
pm_runtime_put(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
2015-04-30 09:35:27 -06:00
|
|
|
pm_qos_remove_request(&up->pm_qos_request);
|
|
|
|
device_init_wakeup(up->dev, false);
|
2013-08-14 04:29:38 -06:00
|
|
|
err_rs485:
|
2012-03-21 05:52:22 -06:00
|
|
|
err_port_line:
|
2010-09-27 08:50:49 -06:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-11-19 11:26:18 -07:00
|
|
|
static int serial_omap_remove(struct platform_device *dev)
|
2010-09-27 08:50:49 -06:00
|
|
|
{
|
|
|
|
struct uart_omap_port *up = platform_get_drvdata(dev);
|
|
|
|
|
2012-09-06 06:45:29 -06:00
|
|
|
pm_runtime_put_sync(up->dev);
|
2012-09-06 06:45:28 -06:00
|
|
|
pm_runtime_disable(up->dev);
|
|
|
|
uart_remove_one_port(&serial_omap_reg, &up->port);
|
|
|
|
pm_qos_remove_request(&up->pm_qos_request);
|
2014-03-21 02:25:10 -06:00
|
|
|
device_init_wakeup(&dev->dev, false);
|
2011-02-28 05:42:23 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-11-07 06:30:33 -07:00
|
|
|
/*
|
|
|
|
* Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
|
|
|
|
* The access to uart register after MDR1 Access
|
|
|
|
* causes UART to corrupt data.
|
|
|
|
*
|
|
|
|
* Need a delay =
|
|
|
|
* 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
|
|
|
|
* give 10 times as much
|
|
|
|
*/
|
|
|
|
static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
|
|
|
|
{
|
|
|
|
u8 timeout = 255;
|
|
|
|
|
|
|
|
serial_out(up, UART_OMAP_MDR1, mdr1);
|
|
|
|
udelay(2);
|
|
|
|
serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
|
|
|
|
UART_FCR_CLEAR_RCVR);
|
|
|
|
/*
|
|
|
|
* Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
|
|
|
|
* TX_FIFO_E bit is 1.
|
|
|
|
*/
|
|
|
|
while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
|
|
|
|
(UART_LSR_THRE | UART_LSR_DR))) {
|
|
|
|
timeout--;
|
|
|
|
if (!timeout) {
|
|
|
|
/* Should *never* happen. we warn and carry on */
|
2012-09-06 06:45:20 -06:00
|
|
|
dev_crit(up->dev, "Errata i202: timedout %x\n",
|
2011-11-07 06:30:33 -07:00
|
|
|
serial_in(up, UART_LSR));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
udelay(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-12-12 16:41:36 -07:00
|
|
|
#ifdef CONFIG_PM
|
2011-11-07 06:26:12 -07:00
|
|
|
static void serial_omap_restore_context(struct uart_omap_port *up)
|
|
|
|
{
|
2011-11-07 06:30:33 -07:00
|
|
|
if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
|
|
|
|
serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
|
|
|
|
else
|
|
|
|
serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
|
|
|
|
|
2011-11-07 06:26:12 -07:00
|
|
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
|
|
|
|
serial_out(up, UART_EFR, UART_EFR_ECB);
|
|
|
|
serial_out(up, UART_LCR, 0x0); /* Operational mode */
|
|
|
|
serial_out(up, UART_IER, 0x0);
|
|
|
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
|
2011-11-07 06:27:03 -07:00
|
|
|
serial_out(up, UART_DLL, up->dll);
|
|
|
|
serial_out(up, UART_DLM, up->dlh);
|
2011-11-07 06:26:12 -07:00
|
|
|
serial_out(up, UART_LCR, 0x0); /* Operational mode */
|
|
|
|
serial_out(up, UART_IER, up->ier);
|
|
|
|
serial_out(up, UART_FCR, up->fcr);
|
|
|
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
|
|
|
|
serial_out(up, UART_MCR, up->mcr);
|
|
|
|
serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
|
2011-11-07 06:27:03 -07:00
|
|
|
serial_out(up, UART_OMAP_SCR, up->scr);
|
2011-11-07 06:26:12 -07:00
|
|
|
serial_out(up, UART_EFR, up->efr);
|
|
|
|
serial_out(up, UART_LCR, up->lcr);
|
2011-11-07 06:30:33 -07:00
|
|
|
if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
|
|
|
|
serial_omap_mdr1_errataset(up, up->mdr1);
|
|
|
|
else
|
|
|
|
serial_out(up, UART_OMAP_MDR1, up->mdr1);
|
2013-07-05 09:25:59 -06:00
|
|
|
serial_out(up, UART_OMAP_WER, up->wer);
|
2011-11-07 06:26:12 -07:00
|
|
|
}
|
|
|
|
|
2011-02-28 05:42:23 -07:00
|
|
|
static int serial_omap_runtime_suspend(struct device *dev)
|
|
|
|
{
|
2011-10-11 07:41:27 -06:00
|
|
|
struct uart_omap_port *up = dev_get_drvdata(dev);
|
|
|
|
|
2013-06-04 20:04:49 -06:00
|
|
|
if (!up)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2013-05-15 09:35:38 -06:00
|
|
|
/*
|
|
|
|
* When using 'no_console_suspend', the console UART must not be
|
|
|
|
* suspended. Since driver suspend is managed by runtime suspend,
|
|
|
|
* preventing runtime suspend (by returning error) will keep device
|
|
|
|
* active during suspend.
|
|
|
|
*/
|
|
|
|
if (up->is_suspending && !console_suspend_enabled &&
|
|
|
|
uart_console(&up->port))
|
|
|
|
return -EBUSY;
|
|
|
|
|
2012-08-23 04:32:42 -06:00
|
|
|
up->context_loss_cnt = serial_omap_get_context_loss_count(up);
|
2011-10-11 07:41:27 -06:00
|
|
|
|
2014-03-25 12:48:47 -06:00
|
|
|
serial_omap_enable_wakeup(up, true);
|
2011-10-13 02:41:09 -06:00
|
|
|
|
2011-11-09 05:11:21 -07:00
|
|
|
up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
|
|
|
|
schedule_work(&up->qos_work);
|
|
|
|
|
2010-09-27 08:50:49 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-02-28 05:42:23 -07:00
|
|
|
static int serial_omap_runtime_resume(struct device *dev)
|
|
|
|
{
|
2011-11-07 06:26:12 -07:00
|
|
|
struct uart_omap_port *up = dev_get_drvdata(dev);
|
|
|
|
|
2012-10-03 05:54:36 -06:00
|
|
|
int loss_cnt = serial_omap_get_context_loss_count(up);
|
2011-10-11 07:41:27 -06:00
|
|
|
|
2014-03-25 12:48:47 -06:00
|
|
|
serial_omap_enable_wakeup(up, false);
|
|
|
|
|
2012-10-03 05:54:36 -06:00
|
|
|
if (loss_cnt < 0) {
|
2013-06-10 08:39:09 -06:00
|
|
|
dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
|
2012-10-03 05:54:36 -06:00
|
|
|
loss_cnt);
|
2012-09-18 05:35:54 -06:00
|
|
|
serial_omap_restore_context(up);
|
2012-10-03 05:54:36 -06:00
|
|
|
} else if (up->context_loss_cnt != loss_cnt) {
|
|
|
|
serial_omap_restore_context(up);
|
|
|
|
}
|
2012-09-18 05:35:54 -06:00
|
|
|
up->latency = up->calc_latency;
|
|
|
|
schedule_work(&up->qos_work);
|
2011-11-07 06:26:12 -07:00
|
|
|
|
2010-09-27 08:50:49 -06:00
|
|
|
return 0;
|
|
|
|
}
|
2011-02-28 05:42:23 -07:00
|
|
|
#endif
|
|
|
|
|
|
|
|
static const struct dev_pm_ops serial_omap_dev_pm_ops = {
|
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
|
|
|
|
SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
|
|
|
|
serial_omap_runtime_resume, NULL)
|
2013-05-15 09:35:38 -06:00
|
|
|
.prepare = serial_omap_prepare,
|
|
|
|
.complete = serial_omap_complete,
|
2011-02-28 05:42:23 -07:00
|
|
|
};
|
|
|
|
|
2011-12-14 04:55:45 -07:00
|
|
|
#if defined(CONFIG_OF)
|
|
|
|
static const struct of_device_id omap_serial_of_match[] = {
|
|
|
|
{ .compatible = "ti,omap2-uart" },
|
|
|
|
{ .compatible = "ti,omap3-uart" },
|
|
|
|
{ .compatible = "ti,omap4-uart" },
|
|
|
|
{},
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, omap_serial_of_match);
|
|
|
|
#endif
|
2010-09-27 08:50:49 -06:00
|
|
|
|
|
|
|
static struct platform_driver serial_omap_driver = {
|
|
|
|
.probe = serial_omap_probe,
|
2012-11-19 11:21:34 -07:00
|
|
|
.remove = serial_omap_remove,
|
2010-09-27 08:50:49 -06:00
|
|
|
.driver = {
|
|
|
|
.name = DRIVER_NAME,
|
2011-02-28 05:42:23 -07:00
|
|
|
.pm = &serial_omap_dev_pm_ops,
|
2011-12-14 04:55:45 -07:00
|
|
|
.of_match_table = of_match_ptr(omap_serial_of_match),
|
2010-09-27 08:50:49 -06:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init serial_omap_init(void)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = uart_register_driver(&serial_omap_reg);
|
|
|
|
if (ret != 0)
|
|
|
|
return ret;
|
|
|
|
ret = platform_driver_register(&serial_omap_driver);
|
|
|
|
if (ret != 0)
|
|
|
|
uart_unregister_driver(&serial_omap_reg);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit serial_omap_exit(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&serial_omap_driver);
|
|
|
|
uart_unregister_driver(&serial_omap_reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
module_init(serial_omap_init);
|
|
|
|
module_exit(serial_omap_exit);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("OMAP High Speed UART driver");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_AUTHOR("Texas Instruments Inc");
|