2009-11-03 02:23:50 -07:00
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/*
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* linux/drivers/video/omap2/dss/dss.c
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*
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* Copyright (C) 2009 Nokia Corporation
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* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
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*
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* Some code and ideas taken from drivers/video/omap/ driver
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* by Imre Deak.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define DSS_SUBSYS_NAME "DSS"
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/clk.h>
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#include <plat/display.h>
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2011-01-23 23:21:58 -07:00
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#include <plat/clock.h>
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2009-11-03 02:23:50 -07:00
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#include "dss.h"
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2011-02-24 05:18:50 -07:00
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#include "dss_features.h"
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2009-11-03 02:23:50 -07:00
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#define DSS_SZ_REGS SZ_512
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struct dss_reg {
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u16 idx;
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};
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#define DSS_REG(idx) ((const struct dss_reg) { idx })
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#define DSS_REVISION DSS_REG(0x0000)
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#define DSS_SYSCONFIG DSS_REG(0x0010)
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#define DSS_SYSSTATUS DSS_REG(0x0014)
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#define DSS_IRQSTATUS DSS_REG(0x0018)
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#define DSS_CONTROL DSS_REG(0x0040)
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#define DSS_SDI_CONTROL DSS_REG(0x0044)
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#define DSS_PLL_CONTROL DSS_REG(0x0048)
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#define DSS_SDI_STATUS DSS_REG(0x005C)
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#define REG_GET(idx, start, end) \
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FLD_GET(dss_read_reg(idx), start, end)
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#define REG_FLD_MOD(idx, val, start, end) \
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dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
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static struct {
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2011-01-23 23:21:57 -07:00
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struct platform_device *pdev;
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2009-11-03 02:23:50 -07:00
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void __iomem *base;
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2011-01-23 23:21:58 -07:00
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int ctx_id;
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2009-11-03 02:23:50 -07:00
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struct clk *dpll4_m4_ck;
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2011-01-23 23:21:58 -07:00
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struct clk *dss_ick;
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2011-01-31 09:27:45 -07:00
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struct clk *dss_fck;
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struct clk *dss_sys_clk;
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struct clk *dss_tv_fck;
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struct clk *dss_video_fck;
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2011-01-23 23:21:58 -07:00
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unsigned num_clks_enabled;
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2009-11-03 02:23:50 -07:00
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unsigned long cache_req_pck;
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unsigned long cache_prate;
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struct dss_clock_info cache_dss_cinfo;
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struct dispc_clock_info cache_dispc_cinfo;
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2010-01-08 09:00:36 -07:00
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enum dss_clk_source dsi_clk_source;
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enum dss_clk_source dispc_clk_source;
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2011-03-08 04:50:35 -07:00
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enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
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2010-01-08 09:00:36 -07:00
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2009-11-03 02:23:50 -07:00
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u32 ctx[DSS_SZ_REGS / sizeof(u32)];
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} dss;
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2011-03-01 23:27:25 -07:00
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static const struct dss_clk_source_name dss_generic_clk_source_names[] = {
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{ DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "DSI_PLL_HSDIV_DISPC" },
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{ DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "DSI_PLL_HSDIV_DSI" },
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{ DSS_CLK_SRC_FCK, "DSS_FCK" },
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};
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2011-01-23 23:21:58 -07:00
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static void dss_clk_enable_all_no_ctx(void);
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static void dss_clk_disable_all_no_ctx(void);
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static void dss_clk_enable_no_ctx(enum dss_clock clks);
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static void dss_clk_disable_no_ctx(enum dss_clock clks);
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2009-11-03 02:23:50 -07:00
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static int _omap_dss_wait_reset(void);
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static inline void dss_write_reg(const struct dss_reg idx, u32 val)
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{
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__raw_writel(val, dss.base + idx.idx);
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}
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static inline u32 dss_read_reg(const struct dss_reg idx)
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{
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return __raw_readl(dss.base + idx.idx);
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}
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#define SR(reg) \
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dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
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#define RR(reg) \
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dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
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void dss_save_context(void)
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{
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if (cpu_is_omap24xx())
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return;
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SR(SYSCONFIG);
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SR(CONTROL);
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2011-02-24 05:18:50 -07:00
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if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
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OMAP_DISPLAY_TYPE_SDI) {
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SR(SDI_CONTROL);
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SR(PLL_CONTROL);
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}
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2009-11-03 02:23:50 -07:00
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}
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void dss_restore_context(void)
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{
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if (_omap_dss_wait_reset())
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DSSERR("DSS not coming out of reset after sleep\n");
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RR(SYSCONFIG);
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RR(CONTROL);
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2011-02-24 05:18:50 -07:00
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if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
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OMAP_DISPLAY_TYPE_SDI) {
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RR(SDI_CONTROL);
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RR(PLL_CONTROL);
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}
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2009-11-03 02:23:50 -07:00
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}
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#undef SR
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#undef RR
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void dss_sdi_init(u8 datapairs)
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{
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u32 l;
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BUG_ON(datapairs > 3 || datapairs < 1);
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l = dss_read_reg(DSS_SDI_CONTROL);
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l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */
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l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */
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l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */
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dss_write_reg(DSS_SDI_CONTROL, l);
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l = dss_read_reg(DSS_PLL_CONTROL);
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l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */
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l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */
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l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */
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dss_write_reg(DSS_PLL_CONTROL, l);
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}
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int dss_sdi_enable(void)
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{
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unsigned long timeout;
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dispc_pck_free_enable(1);
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/* Reset SDI PLL */
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REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
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udelay(1); /* wait 2x PCLK */
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/* Lock SDI PLL */
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REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
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/* Waiting for PLL lock request to complete */
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timeout = jiffies + msecs_to_jiffies(500);
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while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
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if (time_after_eq(jiffies, timeout)) {
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DSSERR("PLL lock request timed out\n");
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goto err1;
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}
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}
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/* Clearing PLL_GO bit */
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REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
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/* Waiting for PLL to lock */
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timeout = jiffies + msecs_to_jiffies(500);
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while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
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if (time_after_eq(jiffies, timeout)) {
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DSSERR("PLL lock timed out\n");
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goto err1;
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}
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}
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dispc_lcd_enable_signal(1);
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/* Waiting for SDI reset to complete */
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timeout = jiffies + msecs_to_jiffies(500);
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while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
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if (time_after_eq(jiffies, timeout)) {
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DSSERR("SDI reset timed out\n");
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goto err2;
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}
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}
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return 0;
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err2:
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dispc_lcd_enable_signal(0);
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err1:
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/* Reset SDI PLL */
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REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
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dispc_pck_free_enable(0);
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return -ETIMEDOUT;
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}
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void dss_sdi_disable(void)
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{
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dispc_lcd_enable_signal(0);
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dispc_pck_free_enable(0);
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/* Reset SDI PLL */
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REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
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}
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2011-03-01 23:27:25 -07:00
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const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src)
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{
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return dss_generic_clk_source_names[clk_src].clksrc_name;
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}
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2009-11-03 02:23:50 -07:00
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void dss_dump_clocks(struct seq_file *s)
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{
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unsigned long dpll4_ck_rate;
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unsigned long dpll4_m4_ck_rate;
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2011-01-31 09:27:44 -07:00
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
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2009-11-03 02:23:50 -07:00
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dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
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dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
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seq_printf(s, "- DSS -\n");
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seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
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2010-04-25 04:57:19 -06:00
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if (cpu_is_omap3630())
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2011-03-01 23:27:25 -07:00
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seq_printf(s, "%s (%s) = %lu / %lu = %lu\n",
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dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK),
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dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK),
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2010-04-25 04:57:19 -06:00
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dpll4_ck_rate,
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dpll4_ck_rate / dpll4_m4_ck_rate,
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2011-01-31 09:27:44 -07:00
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dss_clk_get_rate(DSS_CLK_FCK));
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2010-04-25 04:57:19 -06:00
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else
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2011-03-01 23:27:25 -07:00
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seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n",
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dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK),
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dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK),
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2009-11-03 02:23:50 -07:00
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dpll4_ck_rate,
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dpll4_ck_rate / dpll4_m4_ck_rate,
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2011-01-31 09:27:44 -07:00
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dss_clk_get_rate(DSS_CLK_FCK));
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2009-11-03 02:23:50 -07:00
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2011-01-31 09:27:44 -07:00
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
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2009-11-03 02:23:50 -07:00
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}
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void dss_dump_regs(struct seq_file *s)
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{
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#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
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2011-01-31 09:27:44 -07:00
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dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
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2009-11-03 02:23:50 -07:00
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DUMPREG(DSS_REVISION);
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DUMPREG(DSS_SYSCONFIG);
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DUMPREG(DSS_SYSSTATUS);
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DUMPREG(DSS_IRQSTATUS);
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DUMPREG(DSS_CONTROL);
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2011-02-24 05:18:50 -07:00
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if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
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OMAP_DISPLAY_TYPE_SDI) {
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DUMPREG(DSS_SDI_CONTROL);
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DUMPREG(DSS_PLL_CONTROL);
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DUMPREG(DSS_SDI_STATUS);
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}
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2009-11-03 02:23:50 -07:00
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2011-01-31 09:27:44 -07:00
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dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
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2009-11-03 02:23:50 -07:00
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#undef DUMPREG
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}
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2010-01-08 09:00:36 -07:00
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void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
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{
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int b;
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2011-03-08 04:50:35 -07:00
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u8 start, end;
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2010-01-08 09:00:36 -07:00
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2011-03-08 04:50:34 -07:00
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switch (clk_src) {
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case DSS_CLK_SRC_FCK:
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b = 0;
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break;
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case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
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b = 1;
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2011-02-24 01:47:30 -07:00
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dsi_wait_pll_hsdiv_dispc_active();
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2011-03-08 04:50:34 -07:00
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break;
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default:
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BUG();
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}
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2010-06-09 06:28:12 -06:00
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2011-03-08 04:50:35 -07:00
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dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
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REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */
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2010-01-08 09:00:36 -07:00
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dss.dispc_clk_source = clk_src;
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}
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void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
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2009-11-03 02:23:50 -07:00
|
|
|
{
|
2010-01-08 09:00:36 -07:00
|
|
|
int b;
|
|
|
|
|
2011-03-08 04:50:34 -07:00
|
|
|
switch (clk_src) {
|
|
|
|
case DSS_CLK_SRC_FCK:
|
|
|
|
b = 0;
|
|
|
|
break;
|
|
|
|
case DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
|
|
|
|
b = 1;
|
2011-02-24 01:47:30 -07:00
|
|
|
dsi_wait_pll_hsdiv_dsi_active();
|
2011-03-08 04:50:34 -07:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
2010-06-09 06:28:12 -06:00
|
|
|
|
2010-01-08 09:00:36 -07:00
|
|
|
REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */
|
|
|
|
|
|
|
|
dss.dsi_clk_source = clk_src;
|
2009-11-03 02:23:50 -07:00
|
|
|
}
|
|
|
|
|
2011-03-08 04:50:35 -07:00
|
|
|
void dss_select_lcd_clk_source(enum omap_channel channel,
|
|
|
|
enum dss_clk_source clk_src)
|
|
|
|
{
|
|
|
|
int b, ix, pos;
|
|
|
|
|
|
|
|
if (!dss_has_feature(FEAT_LCD_CLK_SRC))
|
|
|
|
return;
|
|
|
|
|
|
|
|
switch (clk_src) {
|
|
|
|
case DSS_CLK_SRC_FCK:
|
|
|
|
b = 0;
|
|
|
|
break;
|
|
|
|
case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
|
|
|
|
BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
|
|
|
|
b = 1;
|
|
|
|
dsi_wait_pll_hsdiv_dispc_active();
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
|
|
|
|
pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12;
|
|
|
|
REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */
|
|
|
|
|
|
|
|
ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
|
|
|
|
dss.lcd_clk_source[ix] = clk_src;
|
|
|
|
}
|
|
|
|
|
2010-01-08 09:00:36 -07:00
|
|
|
enum dss_clk_source dss_get_dispc_clk_source(void)
|
2009-11-03 02:23:50 -07:00
|
|
|
{
|
2010-01-08 09:00:36 -07:00
|
|
|
return dss.dispc_clk_source;
|
2009-11-03 02:23:50 -07:00
|
|
|
}
|
|
|
|
|
2010-01-08 09:00:36 -07:00
|
|
|
enum dss_clk_source dss_get_dsi_clk_source(void)
|
2009-11-03 02:23:50 -07:00
|
|
|
{
|
2010-01-08 09:00:36 -07:00
|
|
|
return dss.dsi_clk_source;
|
2009-11-03 02:23:50 -07:00
|
|
|
}
|
|
|
|
|
2011-03-08 04:50:35 -07:00
|
|
|
enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
|
|
|
|
{
|
|
|
|
int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
|
|
|
|
return dss.lcd_clk_source[ix];
|
|
|
|
}
|
|
|
|
|
2009-11-03 02:23:50 -07:00
|
|
|
/* calculate clock rates using dividers in cinfo */
|
|
|
|
int dss_calc_clock_rates(struct dss_clock_info *cinfo)
|
|
|
|
{
|
|
|
|
unsigned long prate;
|
|
|
|
|
2010-04-25 04:57:19 -06:00
|
|
|
if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) ||
|
|
|
|
cinfo->fck_div == 0)
|
2009-11-03 02:23:50 -07:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
|
|
|
|
|
|
|
|
cinfo->fck = prate / cinfo->fck_div;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int dss_set_clock_div(struct dss_clock_info *cinfo)
|
|
|
|
{
|
|
|
|
unsigned long prate;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
if (cpu_is_omap34xx()) {
|
|
|
|
prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
|
|
|
|
DSSDBG("dpll4_m4 = %ld\n", prate);
|
|
|
|
|
|
|
|
r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int dss_get_clock_div(struct dss_clock_info *cinfo)
|
|
|
|
{
|
2011-01-31 09:27:44 -07:00
|
|
|
cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK);
|
2009-11-03 02:23:50 -07:00
|
|
|
|
|
|
|
if (cpu_is_omap34xx()) {
|
|
|
|
unsigned long prate;
|
|
|
|
prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
|
2010-04-25 04:57:19 -06:00
|
|
|
if (cpu_is_omap3630())
|
|
|
|
cinfo->fck_div = prate / (cinfo->fck);
|
|
|
|
else
|
|
|
|
cinfo->fck_div = prate / (cinfo->fck / 2);
|
2009-11-03 02:23:50 -07:00
|
|
|
} else {
|
|
|
|
cinfo->fck_div = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned long dss_get_dpll4_rate(void)
|
|
|
|
{
|
|
|
|
if (cpu_is_omap34xx())
|
|
|
|
return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
|
|
|
|
else
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
|
|
|
|
struct dss_clock_info *dss_cinfo,
|
|
|
|
struct dispc_clock_info *dispc_cinfo)
|
|
|
|
{
|
|
|
|
unsigned long prate;
|
|
|
|
struct dss_clock_info best_dss;
|
|
|
|
struct dispc_clock_info best_dispc;
|
|
|
|
|
2011-02-28 23:24:00 -07:00
|
|
|
unsigned long fck, max_dss_fck;
|
2009-11-03 02:23:50 -07:00
|
|
|
|
|
|
|
u16 fck_div;
|
|
|
|
|
|
|
|
int match = 0;
|
|
|
|
int min_fck_per_pck;
|
|
|
|
|
|
|
|
prate = dss_get_dpll4_rate();
|
|
|
|
|
2011-02-28 23:24:00 -07:00
|
|
|
max_dss_fck = dss_feat_get_max_dss_fck();
|
|
|
|
|
2011-01-31 09:27:44 -07:00
|
|
|
fck = dss_clk_get_rate(DSS_CLK_FCK);
|
2009-11-03 02:23:50 -07:00
|
|
|
if (req_pck == dss.cache_req_pck &&
|
|
|
|
((cpu_is_omap34xx() && prate == dss.cache_prate) ||
|
|
|
|
dss.cache_dss_cinfo.fck == fck)) {
|
|
|
|
DSSDBG("dispc clock info found from cache.\n");
|
|
|
|
*dss_cinfo = dss.cache_dss_cinfo;
|
|
|
|
*dispc_cinfo = dss.cache_dispc_cinfo;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
|
|
|
|
|
|
|
|
if (min_fck_per_pck &&
|
2011-02-28 23:24:00 -07:00
|
|
|
req_pck * min_fck_per_pck > max_dss_fck) {
|
2009-11-03 02:23:50 -07:00
|
|
|
DSSERR("Requested pixel clock not possible with the current "
|
|
|
|
"OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
|
|
|
|
"the constraint off.\n");
|
|
|
|
min_fck_per_pck = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
retry:
|
|
|
|
memset(&best_dss, 0, sizeof(best_dss));
|
|
|
|
memset(&best_dispc, 0, sizeof(best_dispc));
|
|
|
|
|
|
|
|
if (cpu_is_omap24xx()) {
|
|
|
|
struct dispc_clock_info cur_dispc;
|
|
|
|
/* XXX can we change the clock on omap2? */
|
2011-01-31 09:27:44 -07:00
|
|
|
fck = dss_clk_get_rate(DSS_CLK_FCK);
|
2009-11-03 02:23:50 -07:00
|
|
|
fck_div = 1;
|
|
|
|
|
|
|
|
dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
|
|
|
|
match = 1;
|
|
|
|
|
|
|
|
best_dss.fck = fck;
|
|
|
|
best_dss.fck_div = fck_div;
|
|
|
|
|
|
|
|
best_dispc = cur_dispc;
|
|
|
|
|
|
|
|
goto found;
|
|
|
|
} else if (cpu_is_omap34xx()) {
|
2010-04-25 04:57:19 -06:00
|
|
|
for (fck_div = (cpu_is_omap3630() ? 32 : 16);
|
|
|
|
fck_div > 0; --fck_div) {
|
2009-11-03 02:23:50 -07:00
|
|
|
struct dispc_clock_info cur_dispc;
|
|
|
|
|
2010-04-25 04:57:19 -06:00
|
|
|
if (cpu_is_omap3630())
|
|
|
|
fck = prate / fck_div;
|
|
|
|
else
|
|
|
|
fck = prate / fck_div * 2;
|
2009-11-03 02:23:50 -07:00
|
|
|
|
2011-02-28 23:24:00 -07:00
|
|
|
if (fck > max_dss_fck)
|
2009-11-03 02:23:50 -07:00
|
|
|
continue;
|
|
|
|
|
|
|
|
if (min_fck_per_pck &&
|
|
|
|
fck < req_pck * min_fck_per_pck)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
match = 1;
|
|
|
|
|
|
|
|
dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
|
|
|
|
|
|
|
|
if (abs(cur_dispc.pck - req_pck) <
|
|
|
|
abs(best_dispc.pck - req_pck)) {
|
|
|
|
|
|
|
|
best_dss.fck = fck;
|
|
|
|
best_dss.fck_div = fck_div;
|
|
|
|
|
|
|
|
best_dispc = cur_dispc;
|
|
|
|
|
|
|
|
if (cur_dispc.pck == req_pck)
|
|
|
|
goto found;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
|
|
|
|
found:
|
|
|
|
if (!match) {
|
|
|
|
if (min_fck_per_pck) {
|
|
|
|
DSSERR("Could not find suitable clock settings.\n"
|
|
|
|
"Turning FCK/PCK constraint off and"
|
|
|
|
"trying again.\n");
|
|
|
|
min_fck_per_pck = 0;
|
|
|
|
goto retry;
|
|
|
|
}
|
|
|
|
|
|
|
|
DSSERR("Could not find suitable clock settings.\n");
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dss_cinfo)
|
|
|
|
*dss_cinfo = best_dss;
|
|
|
|
if (dispc_cinfo)
|
|
|
|
*dispc_cinfo = best_dispc;
|
|
|
|
|
|
|
|
dss.cache_req_pck = req_pck;
|
|
|
|
dss.cache_prate = prate;
|
|
|
|
dss.cache_dss_cinfo = best_dss;
|
|
|
|
dss.cache_dispc_cinfo = best_dispc;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int _omap_dss_wait_reset(void)
|
|
|
|
{
|
2010-01-07 05:19:48 -07:00
|
|
|
int t = 0;
|
2009-11-03 02:23:50 -07:00
|
|
|
|
|
|
|
while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) {
|
2010-01-07 05:19:48 -07:00
|
|
|
if (++t > 1000) {
|
2009-11-03 02:23:50 -07:00
|
|
|
DSSERR("soft reset failed\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
2010-01-07 05:19:48 -07:00
|
|
|
udelay(1);
|
2009-11-03 02:23:50 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int _omap_dss_reset(void)
|
|
|
|
{
|
|
|
|
/* Soft reset */
|
|
|
|
REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1);
|
|
|
|
return _omap_dss_wait_reset();
|
|
|
|
}
|
|
|
|
|
|
|
|
void dss_set_venc_output(enum omap_dss_venc_type type)
|
|
|
|
{
|
|
|
|
int l = 0;
|
|
|
|
|
|
|
|
if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
|
|
|
|
l = 0;
|
|
|
|
else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
|
|
|
|
l = 1;
|
|
|
|
else
|
|
|
|
BUG();
|
|
|
|
|
|
|
|
/* venc out selection. 0 = comp, 1 = svideo */
|
|
|
|
REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
|
|
|
|
}
|
|
|
|
|
|
|
|
void dss_set_dac_pwrdn_bgz(bool enable)
|
|
|
|
{
|
|
|
|
REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
|
|
|
|
}
|
|
|
|
|
2011-03-02 03:29:27 -07:00
|
|
|
static int dss_init(void)
|
2009-11-03 02:23:50 -07:00
|
|
|
{
|
|
|
|
int r;
|
|
|
|
u32 rev;
|
2011-01-23 23:22:04 -07:00
|
|
|
struct resource *dss_mem;
|
2009-11-03 02:23:50 -07:00
|
|
|
|
2011-01-23 23:22:04 -07:00
|
|
|
dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!dss_mem) {
|
|
|
|
DSSERR("can't get IORESOURCE_MEM DSS\n");
|
|
|
|
r = -EINVAL;
|
|
|
|
goto fail0;
|
|
|
|
}
|
|
|
|
dss.base = ioremap(dss_mem->start, resource_size(dss_mem));
|
2009-11-03 02:23:50 -07:00
|
|
|
if (!dss.base) {
|
|
|
|
DSSERR("can't ioremap DSS\n");
|
|
|
|
r = -ENOMEM;
|
|
|
|
goto fail0;
|
|
|
|
}
|
|
|
|
|
2011-03-02 03:29:27 -07:00
|
|
|
/* disable LCD and DIGIT output. This seems to fix the synclost
|
|
|
|
* problem that we get, if the bootloader starts the DSS and
|
|
|
|
* the kernel resets it */
|
|
|
|
omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
|
|
|
|
|
|
|
|
/* We need to wait here a bit, otherwise we sometimes start to
|
|
|
|
* get synclost errors, and after that only power cycle will
|
|
|
|
* restore DSS functionality. I have no idea why this happens.
|
|
|
|
* And we have to wait _before_ resetting the DSS, but after
|
|
|
|
* enabling clocks.
|
|
|
|
*/
|
|
|
|
msleep(50);
|
|
|
|
|
|
|
|
_omap_dss_reset();
|
2009-11-03 02:23:50 -07:00
|
|
|
|
|
|
|
/* autoidle */
|
|
|
|
REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
|
|
|
|
|
|
|
|
/* Select DPLL */
|
|
|
|
REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
|
|
|
|
|
|
|
|
#ifdef CONFIG_OMAP2_DSS_VENC
|
|
|
|
REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
|
|
|
|
REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
|
|
|
|
REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
|
|
|
|
#endif
|
|
|
|
|
|
|
|
if (cpu_is_omap34xx()) {
|
|
|
|
dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
|
|
|
|
if (IS_ERR(dss.dpll4_m4_ck)) {
|
|
|
|
DSSERR("Failed to get dpll4_m4_ck\n");
|
|
|
|
r = PTR_ERR(dss.dpll4_m4_ck);
|
2011-02-23 01:41:03 -07:00
|
|
|
goto fail1;
|
2009-11-03 02:23:50 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-01-05 22:14:10 -07:00
|
|
|
dss.dsi_clk_source = DSS_CLK_SRC_FCK;
|
|
|
|
dss.dispc_clk_source = DSS_CLK_SRC_FCK;
|
2011-03-08 04:50:35 -07:00
|
|
|
dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK;
|
|
|
|
dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK;
|
2010-03-12 03:46:05 -07:00
|
|
|
|
2009-11-03 02:23:50 -07:00
|
|
|
dss_save_context();
|
|
|
|
|
|
|
|
rev = dss_read_reg(DSS_REVISION);
|
|
|
|
printk(KERN_INFO "OMAP DSS rev %d.%d\n",
|
|
|
|
FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
fail1:
|
|
|
|
iounmap(dss.base);
|
|
|
|
fail0:
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2011-01-23 23:21:57 -07:00
|
|
|
static void dss_exit(void)
|
2009-11-03 02:23:50 -07:00
|
|
|
{
|
|
|
|
if (cpu_is_omap34xx())
|
|
|
|
clk_put(dss.dpll4_m4_ck);
|
|
|
|
|
|
|
|
iounmap(dss.base);
|
|
|
|
}
|
|
|
|
|
2011-01-23 23:21:58 -07:00
|
|
|
/* CONTEXT */
|
|
|
|
static int dss_get_ctx_id(void)
|
|
|
|
{
|
|
|
|
struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
if (!pdata->board_data->get_last_off_on_transaction_id)
|
|
|
|
return 0;
|
|
|
|
r = pdata->board_data->get_last_off_on_transaction_id(&dss.pdev->dev);
|
|
|
|
if (r < 0) {
|
|
|
|
dev_err(&dss.pdev->dev, "getting transaction ID failed, "
|
|
|
|
"will force context restore\n");
|
|
|
|
r = -1;
|
|
|
|
}
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
int dss_need_ctx_restore(void)
|
|
|
|
{
|
|
|
|
int id = dss_get_ctx_id();
|
|
|
|
|
|
|
|
if (id < 0 || id != dss.ctx_id) {
|
|
|
|
DSSDBG("ctx id %d -> id %d\n",
|
|
|
|
dss.ctx_id, id);
|
|
|
|
dss.ctx_id = id;
|
|
|
|
return 1;
|
|
|
|
} else {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void save_all_ctx(void)
|
|
|
|
{
|
|
|
|
DSSDBG("save context\n");
|
|
|
|
|
2011-01-31 09:27:44 -07:00
|
|
|
dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
|
2011-01-23 23:21:58 -07:00
|
|
|
|
|
|
|
dss_save_context();
|
|
|
|
dispc_save_context();
|
|
|
|
#ifdef CONFIG_OMAP2_DSS_DSI
|
|
|
|
dsi_save_context();
|
|
|
|
#endif
|
|
|
|
|
2011-01-31 09:27:44 -07:00
|
|
|
dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
|
2011-01-23 23:21:58 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void restore_all_ctx(void)
|
|
|
|
{
|
|
|
|
DSSDBG("restore context\n");
|
|
|
|
|
|
|
|
dss_clk_enable_all_no_ctx();
|
|
|
|
|
|
|
|
dss_restore_context();
|
|
|
|
dispc_restore_context();
|
|
|
|
#ifdef CONFIG_OMAP2_DSS_DSI
|
|
|
|
dsi_restore_context();
|
|
|
|
#endif
|
|
|
|
|
|
|
|
dss_clk_disable_all_no_ctx();
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dss_get_clock(struct clk **clock, const char *clk_name)
|
|
|
|
{
|
|
|
|
struct clk *clk;
|
|
|
|
|
|
|
|
clk = clk_get(&dss.pdev->dev, clk_name);
|
|
|
|
|
|
|
|
if (IS_ERR(clk)) {
|
|
|
|
DSSERR("can't get clock %s", clk_name);
|
|
|
|
return PTR_ERR(clk);
|
|
|
|
}
|
|
|
|
|
|
|
|
*clock = clk;
|
|
|
|
|
|
|
|
DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dss_get_clocks(void)
|
|
|
|
{
|
|
|
|
int r;
|
2011-03-01 01:42:14 -07:00
|
|
|
struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data;
|
2011-01-23 23:21:58 -07:00
|
|
|
|
|
|
|
dss.dss_ick = NULL;
|
2011-01-31 09:27:45 -07:00
|
|
|
dss.dss_fck = NULL;
|
|
|
|
dss.dss_sys_clk = NULL;
|
|
|
|
dss.dss_tv_fck = NULL;
|
|
|
|
dss.dss_video_fck = NULL;
|
2011-01-23 23:21:58 -07:00
|
|
|
|
|
|
|
r = dss_get_clock(&dss.dss_ick, "ick");
|
|
|
|
if (r)
|
|
|
|
goto err;
|
|
|
|
|
2011-01-31 09:27:45 -07:00
|
|
|
r = dss_get_clock(&dss.dss_fck, "fck");
|
2011-01-23 23:21:58 -07:00
|
|
|
if (r)
|
|
|
|
goto err;
|
|
|
|
|
2011-03-01 01:42:14 -07:00
|
|
|
if (!pdata->opt_clock_available) {
|
|
|
|
r = -ENODEV;
|
2011-01-23 23:21:58 -07:00
|
|
|
goto err;
|
2011-03-01 01:42:14 -07:00
|
|
|
}
|
2011-01-23 23:21:58 -07:00
|
|
|
|
2011-03-01 01:42:14 -07:00
|
|
|
if (pdata->opt_clock_available("sys_clk")) {
|
|
|
|
r = dss_get_clock(&dss.dss_sys_clk, "sys_clk");
|
|
|
|
if (r)
|
|
|
|
goto err;
|
|
|
|
}
|
2011-01-23 23:21:58 -07:00
|
|
|
|
2011-03-01 01:42:14 -07:00
|
|
|
if (pdata->opt_clock_available("tv_clk")) {
|
|
|
|
r = dss_get_clock(&dss.dss_tv_fck, "tv_clk");
|
|
|
|
if (r)
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pdata->opt_clock_available("video_clk")) {
|
|
|
|
r = dss_get_clock(&dss.dss_video_fck, "video_clk");
|
|
|
|
if (r)
|
|
|
|
goto err;
|
|
|
|
}
|
2011-01-23 23:21:58 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err:
|
|
|
|
if (dss.dss_ick)
|
|
|
|
clk_put(dss.dss_ick);
|
2011-01-31 09:27:45 -07:00
|
|
|
if (dss.dss_fck)
|
|
|
|
clk_put(dss.dss_fck);
|
|
|
|
if (dss.dss_sys_clk)
|
|
|
|
clk_put(dss.dss_sys_clk);
|
|
|
|
if (dss.dss_tv_fck)
|
|
|
|
clk_put(dss.dss_tv_fck);
|
|
|
|
if (dss.dss_video_fck)
|
|
|
|
clk_put(dss.dss_video_fck);
|
2011-01-23 23:21:58 -07:00
|
|
|
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dss_put_clocks(void)
|
|
|
|
{
|
2011-01-31 09:27:45 -07:00
|
|
|
if (dss.dss_video_fck)
|
|
|
|
clk_put(dss.dss_video_fck);
|
2011-03-01 01:42:14 -07:00
|
|
|
if (dss.dss_tv_fck)
|
|
|
|
clk_put(dss.dss_tv_fck);
|
|
|
|
if (dss.dss_sys_clk)
|
|
|
|
clk_put(dss.dss_sys_clk);
|
2011-01-31 09:27:45 -07:00
|
|
|
clk_put(dss.dss_fck);
|
2011-01-23 23:21:58 -07:00
|
|
|
clk_put(dss.dss_ick);
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned long dss_clk_get_rate(enum dss_clock clk)
|
|
|
|
{
|
|
|
|
switch (clk) {
|
|
|
|
case DSS_CLK_ICK:
|
|
|
|
return clk_get_rate(dss.dss_ick);
|
2011-01-31 09:27:44 -07:00
|
|
|
case DSS_CLK_FCK:
|
2011-01-31 09:27:45 -07:00
|
|
|
return clk_get_rate(dss.dss_fck);
|
2011-01-31 09:27:44 -07:00
|
|
|
case DSS_CLK_SYSCK:
|
2011-01-31 09:27:45 -07:00
|
|
|
return clk_get_rate(dss.dss_sys_clk);
|
2011-01-31 09:27:44 -07:00
|
|
|
case DSS_CLK_TVFCK:
|
2011-01-31 09:27:45 -07:00
|
|
|
return clk_get_rate(dss.dss_tv_fck);
|
2011-01-31 09:27:44 -07:00
|
|
|
case DSS_CLK_VIDFCK:
|
2011-01-31 09:27:45 -07:00
|
|
|
return clk_get_rate(dss.dss_video_fck);
|
2011-01-23 23:21:58 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
BUG();
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned count_clk_bits(enum dss_clock clks)
|
|
|
|
{
|
|
|
|
unsigned num_clks = 0;
|
|
|
|
|
|
|
|
if (clks & DSS_CLK_ICK)
|
|
|
|
++num_clks;
|
2011-01-31 09:27:44 -07:00
|
|
|
if (clks & DSS_CLK_FCK)
|
2011-01-23 23:21:58 -07:00
|
|
|
++num_clks;
|
2011-01-31 09:27:44 -07:00
|
|
|
if (clks & DSS_CLK_SYSCK)
|
2011-01-23 23:21:58 -07:00
|
|
|
++num_clks;
|
2011-01-31 09:27:44 -07:00
|
|
|
if (clks & DSS_CLK_TVFCK)
|
2011-01-23 23:21:58 -07:00
|
|
|
++num_clks;
|
2011-01-31 09:27:44 -07:00
|
|
|
if (clks & DSS_CLK_VIDFCK)
|
2011-01-23 23:21:58 -07:00
|
|
|
++num_clks;
|
|
|
|
|
|
|
|
return num_clks;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dss_clk_enable_no_ctx(enum dss_clock clks)
|
|
|
|
{
|
|
|
|
unsigned num_clks = count_clk_bits(clks);
|
|
|
|
|
|
|
|
if (clks & DSS_CLK_ICK)
|
|
|
|
clk_enable(dss.dss_ick);
|
2011-01-31 09:27:44 -07:00
|
|
|
if (clks & DSS_CLK_FCK)
|
2011-01-31 09:27:45 -07:00
|
|
|
clk_enable(dss.dss_fck);
|
2011-03-01 01:42:14 -07:00
|
|
|
if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk)
|
2011-01-31 09:27:45 -07:00
|
|
|
clk_enable(dss.dss_sys_clk);
|
2011-03-01 01:42:14 -07:00
|
|
|
if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck)
|
2011-01-31 09:27:45 -07:00
|
|
|
clk_enable(dss.dss_tv_fck);
|
2011-03-01 01:42:14 -07:00
|
|
|
if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck)
|
2011-01-31 09:27:45 -07:00
|
|
|
clk_enable(dss.dss_video_fck);
|
2011-01-23 23:21:58 -07:00
|
|
|
|
|
|
|
dss.num_clks_enabled += num_clks;
|
|
|
|
}
|
|
|
|
|
|
|
|
void dss_clk_enable(enum dss_clock clks)
|
|
|
|
{
|
|
|
|
bool check_ctx = dss.num_clks_enabled == 0;
|
|
|
|
|
|
|
|
dss_clk_enable_no_ctx(clks);
|
|
|
|
|
2011-03-03 04:16:23 -07:00
|
|
|
/*
|
|
|
|
* HACK: On omap4 the registers may not be accessible right after
|
|
|
|
* enabling the clocks. At some point this will be handled by
|
|
|
|
* pm_runtime, but for the time begin this should make things work.
|
|
|
|
*/
|
|
|
|
if (cpu_is_omap44xx() && check_ctx)
|
|
|
|
udelay(10);
|
|
|
|
|
2011-01-23 23:21:58 -07:00
|
|
|
if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore())
|
|
|
|
restore_all_ctx();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dss_clk_disable_no_ctx(enum dss_clock clks)
|
|
|
|
{
|
|
|
|
unsigned num_clks = count_clk_bits(clks);
|
|
|
|
|
|
|
|
if (clks & DSS_CLK_ICK)
|
|
|
|
clk_disable(dss.dss_ick);
|
2011-01-31 09:27:44 -07:00
|
|
|
if (clks & DSS_CLK_FCK)
|
2011-01-31 09:27:45 -07:00
|
|
|
clk_disable(dss.dss_fck);
|
2011-03-01 01:42:14 -07:00
|
|
|
if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk)
|
2011-01-31 09:27:45 -07:00
|
|
|
clk_disable(dss.dss_sys_clk);
|
2011-03-01 01:42:14 -07:00
|
|
|
if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck)
|
2011-01-31 09:27:45 -07:00
|
|
|
clk_disable(dss.dss_tv_fck);
|
2011-03-01 01:42:14 -07:00
|
|
|
if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck)
|
2011-01-31 09:27:45 -07:00
|
|
|
clk_disable(dss.dss_video_fck);
|
2011-01-23 23:21:58 -07:00
|
|
|
|
|
|
|
dss.num_clks_enabled -= num_clks;
|
|
|
|
}
|
|
|
|
|
|
|
|
void dss_clk_disable(enum dss_clock clks)
|
|
|
|
{
|
|
|
|
if (cpu_is_omap34xx()) {
|
|
|
|
unsigned num_clks = count_clk_bits(clks);
|
|
|
|
|
|
|
|
BUG_ON(dss.num_clks_enabled < num_clks);
|
|
|
|
|
|
|
|
if (dss.num_clks_enabled == num_clks)
|
|
|
|
save_all_ctx();
|
|
|
|
}
|
|
|
|
|
|
|
|
dss_clk_disable_no_ctx(clks);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dss_clk_enable_all_no_ctx(void)
|
|
|
|
{
|
|
|
|
enum dss_clock clks;
|
|
|
|
|
2011-01-31 09:27:44 -07:00
|
|
|
clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
|
2011-01-23 23:21:58 -07:00
|
|
|
if (cpu_is_omap34xx())
|
2011-01-31 09:27:44 -07:00
|
|
|
clks |= DSS_CLK_VIDFCK;
|
2011-01-23 23:21:58 -07:00
|
|
|
dss_clk_enable_no_ctx(clks);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dss_clk_disable_all_no_ctx(void)
|
|
|
|
{
|
|
|
|
enum dss_clock clks;
|
|
|
|
|
2011-01-31 09:27:44 -07:00
|
|
|
clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
|
2011-01-23 23:21:58 -07:00
|
|
|
if (cpu_is_omap34xx())
|
2011-01-31 09:27:44 -07:00
|
|
|
clks |= DSS_CLK_VIDFCK;
|
2011-01-23 23:21:58 -07:00
|
|
|
dss_clk_disable_no_ctx(clks);
|
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
|
|
|
|
/* CLOCKS */
|
|
|
|
static void core_dump_clocks(struct seq_file *s)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
struct clk *clocks[5] = {
|
|
|
|
dss.dss_ick,
|
2011-01-31 09:27:45 -07:00
|
|
|
dss.dss_fck,
|
|
|
|
dss.dss_sys_clk,
|
|
|
|
dss.dss_tv_fck,
|
|
|
|
dss.dss_video_fck
|
2011-01-23 23:21:58 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
seq_printf(s, "- CORE -\n");
|
|
|
|
|
|
|
|
seq_printf(s, "internal clk count\t\t%u\n", dss.num_clks_enabled);
|
|
|
|
|
|
|
|
for (i = 0; i < 5; i++) {
|
|
|
|
if (!clocks[i])
|
|
|
|
continue;
|
|
|
|
seq_printf(s, "%-15s\t%lu\t%d\n",
|
|
|
|
clocks[i]->name,
|
|
|
|
clk_get_rate(clocks[i]),
|
|
|
|
clocks[i]->usecount);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */
|
|
|
|
|
|
|
|
/* DEBUGFS */
|
|
|
|
#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
|
|
|
|
void dss_debug_dump_clocks(struct seq_file *s)
|
|
|
|
{
|
|
|
|
core_dump_clocks(s);
|
|
|
|
dss_dump_clocks(s);
|
|
|
|
dispc_dump_clocks(s);
|
|
|
|
#ifdef CONFIG_OMAP2_DSS_DSI
|
|
|
|
dsi_dump_clocks(s);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
2011-01-23 23:21:57 -07:00
|
|
|
/* DSS HW IP initialisation */
|
|
|
|
static int omap_dsshw_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
int r;
|
|
|
|
|
|
|
|
dss.pdev = pdev;
|
|
|
|
|
2011-01-23 23:21:58 -07:00
|
|
|
r = dss_get_clocks();
|
|
|
|
if (r)
|
|
|
|
goto err_clocks;
|
|
|
|
|
|
|
|
dss_clk_enable_all_no_ctx();
|
|
|
|
|
|
|
|
dss.ctx_id = dss_get_ctx_id();
|
|
|
|
DSSDBG("initial ctx id %u\n", dss.ctx_id);
|
|
|
|
|
2011-03-02 03:29:27 -07:00
|
|
|
r = dss_init();
|
2011-01-23 23:21:57 -07:00
|
|
|
if (r) {
|
|
|
|
DSSERR("Failed to initialize DSS\n");
|
|
|
|
goto err_dss;
|
|
|
|
}
|
|
|
|
|
2011-03-02 03:47:54 -07:00
|
|
|
r = dpi_init();
|
|
|
|
if (r) {
|
|
|
|
DSSERR("Failed to initialize DPI\n");
|
|
|
|
goto err_dpi;
|
|
|
|
}
|
|
|
|
|
|
|
|
r = sdi_init();
|
|
|
|
if (r) {
|
|
|
|
DSSERR("Failed to initialize SDI\n");
|
|
|
|
goto err_sdi;
|
|
|
|
}
|
|
|
|
|
2011-01-23 23:21:58 -07:00
|
|
|
dss_clk_disable_all_no_ctx();
|
|
|
|
return 0;
|
2011-03-02 03:47:54 -07:00
|
|
|
err_sdi:
|
|
|
|
dpi_exit();
|
|
|
|
err_dpi:
|
|
|
|
dss_exit();
|
2011-01-23 23:21:58 -07:00
|
|
|
err_dss:
|
|
|
|
dss_clk_disable_all_no_ctx();
|
|
|
|
dss_put_clocks();
|
|
|
|
err_clocks:
|
2011-01-23 23:21:57 -07:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_dsshw_remove(struct platform_device *pdev)
|
|
|
|
{
|
2011-01-23 23:21:58 -07:00
|
|
|
|
2011-01-23 23:21:57 -07:00
|
|
|
dss_exit();
|
|
|
|
|
2011-01-23 23:21:58 -07:00
|
|
|
/*
|
|
|
|
* As part of hwmod changes, DSS is not the only controller of dss
|
|
|
|
* clocks; hwmod framework itself will also enable clocks during hwmod
|
|
|
|
* init for dss, and autoidle is set in h/w for DSS. Hence, there's no
|
|
|
|
* need to disable clocks if their usecounts > 1.
|
|
|
|
*/
|
|
|
|
WARN_ON(dss.num_clks_enabled > 0);
|
|
|
|
|
|
|
|
dss_put_clocks();
|
2011-01-23 23:21:57 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver omap_dsshw_driver = {
|
|
|
|
.probe = omap_dsshw_probe,
|
|
|
|
.remove = omap_dsshw_remove,
|
|
|
|
.driver = {
|
|
|
|
.name = "omapdss_dss",
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
int dss_init_platform_driver(void)
|
|
|
|
{
|
|
|
|
return platform_driver_register(&omap_dsshw_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
void dss_uninit_platform_driver(void)
|
|
|
|
{
|
|
|
|
return platform_driver_unregister(&omap_dsshw_driver);
|
|
|
|
}
|