2010-05-14 13:05:26 -06:00
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/*
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* OMAP4 specific common source file.
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*
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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*
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* This program is free software,you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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2012-10-18 03:20:08 -06:00
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#include <linux/irq.h>
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2012-11-05 15:18:28 -07:00
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#include <linux/irqchip.h>
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2010-05-14 13:05:26 -06:00
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#include <linux/platform_device.h>
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2011-06-25 19:04:31 -06:00
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#include <linux/memblock.h>
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2012-08-27 18:43:01 -06:00
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/export.h>
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2012-12-27 12:10:24 -07:00
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#include <linux/irqchip/arm-gic.h>
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2013-02-25 01:42:58 -07:00
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#include <linux/of_address.h>
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2013-07-08 17:01:40 -06:00
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#include <linux/reboot.h>
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2014-09-10 10:04:04 -06:00
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#include <linux/genalloc.h>
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2010-05-14 13:05:26 -06:00
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#include <asm/hardware/cache-l2x0.h>
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2011-06-25 19:04:31 -06:00
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#include <asm/mach/map.h>
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2012-01-13 08:00:51 -07:00
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#include <asm/memblock.h>
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2012-10-18 03:20:08 -06:00
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#include <asm/smp_twd.h>
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2010-05-14 13:05:26 -06:00
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2012-09-20 12:41:16 -06:00
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#include "omap-wakeupgen.h"
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2012-08-31 11:59:07 -06:00
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#include "soc.h"
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2012-10-29 20:50:21 -06:00
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#include "iomap.h"
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2011-11-10 14:45:17 -07:00
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#include "common.h"
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2012-10-29 20:56:07 -06:00
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#include "prminst44xx.h"
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2012-10-29 20:57:39 -06:00
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#include "prcm_mpu44xx.h"
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2011-01-01 07:26:04 -07:00
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#include "omap4-sar-layout.h"
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2012-10-01 12:47:06 -06:00
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#include "omap-secure.h"
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2012-10-29 10:35:35 -06:00
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#include "sram.h"
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2010-05-14 13:05:26 -06:00
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#ifdef CONFIG_CACHE_L2X0
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2011-03-03 05:33:25 -07:00
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static void __iomem *l2cache_base;
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2010-05-14 13:05:26 -06:00
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#endif
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2011-01-01 07:26:04 -07:00
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static void __iomem *sar_ram_base;
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ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control register change.
On OMAP4+ devices, GIC register context is lost when MPUSS hits
the OSWR(Open Switch Retention). On the CPU wakeup path, ROM code
gets executed and one of the steps in it is to restore the
saved context of the GIC. The ROM Code GIC distributor restoration
is split in two parts: CPU specific register done by each CPU and
common register done by only one CPU.
Below is the abstract flow.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[...]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU0 is online in OS
- CPU0 enables the GIC distributor. GICD.Enable Non-secure = 1
- CPU0 wakes up CPU1 with clock-domain force wakeup method.
- CPU0 continues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU1 is online in OS and start executing.
[...] -
GIC Restoration: /* Common routine for HS and GP devices */
{
if (GICD != 1) { /* This will be true in OSWR state */
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restores GIC distributor
else
- reconfigure GIC distributor to boot values.
GICD.Enable secure = 1
}
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restore its GIC CPU interface registers if saved.
else
- reconfigure its GIC CPU interface registers to boot
values.
}
...............................................................
So as mentioned in the flow, GICD != 1 condition decides how
the GIC registers are handled in ROM code wakeup path from
OSWR. As evident from the flow, ROM code relies on the entire
GICD register value and not specific register bits.
The assumption was valid till CortexA9 r1pX version since there
was only one banked bit to control secure and non-secure GICD.
Secure view which ROM code sees:
bit 0 == Enable Non-secure
Non-secure view which HLOS sees:
bit 0 == Enable secure
But GICD register has changed between CortexA9 r1pX and r2pX.
On r2pX GICD register is composed of 2 bits.
Secure view which ROM code sees:
bit 1 == Enable Non-secure
bit 0 == Enable secure
Non-secure view which HLOS sees:
bit 0 == Enable Non-secure
Hence on OMAP4460(r2pX) devices, if you go through the
above flow again during CPU1 wakeup, GICD == 3 and hence
ROM code fails to understand the real wakeup power state
and reconfigures GIC distributor to boot values. This is
nasty since you loose the entire interrupt controller
context in a live system.
The ROM code fix done on next OMAP4 device (OMAP4470 - r2px) is to
check "GICD.Enable secure != 1" for GIC restoration in OSWR wakeup path.
Since ROM code can't be fixed on OMAP4460 devices, a work around
needs to be implemented. As evident from the flow, as long as
CPU1 sees GICD == 1 in it's wakeup path from OSWR, the issue
won't happen. Below is the flow with the work-around.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[..]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU0 is online in OS.
- CPU0 does GICD.Enable Non-secure = 0
- CPU0 wakes up CPU1 with clock domain force wakeup method.
- CPU0 waits for GICD.Enable Non-secure = 1
- CPU0 coninues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU1 is online in OS
- CPU1 does GICD.Enable Non-secure = 1
- CPU1 start executing
[...]
...............................................................
With this procedure, the GIC configuration done between the
CPU0 wakeup and CPU1 wakeup will not be lost but during this
short windows, the CPU0 will not receive interrupts.
The BUG is applicable to only OMAP4460(r2pX) devices.
OMAP4470 (also r2pX) is not affected by this bug because
ROM code has been fixed.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-10-18 03:20:05 -06:00
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static void __iomem *gic_dist_base_addr;
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2012-10-18 03:20:08 -06:00
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static void __iomem *twd_base;
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#define IRQ_LOCALTIMER 29
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2011-01-01 07:26:04 -07:00
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2015-06-05 17:38:08 -06:00
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#ifdef CONFIG_OMAP_INTERCONNECT_BARRIER
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2015-06-05 17:13:40 -06:00
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/* Used to implement memory barrier on DRAM path */
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#define OMAP4_DRAM_BARRIER_VA 0xfe600000
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2015-06-05 17:38:08 -06:00
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static void __iomem *dram_sync, *sram_sync;
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static phys_addr_t dram_sync_paddr;
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static u32 dram_sync_size;
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/*
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2016-05-21 05:50:19 -06:00
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* The OMAP4 bus structure contains asynchronous bridges which can buffer
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2015-06-05 17:38:08 -06:00
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* data writes from the MPU. These asynchronous bridges can be found on
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* paths between the MPU to EMIF, and the MPU to L3 interconnects.
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*
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* We need to be careful about re-ordering which can happen as a result
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* of different accesses being performed via different paths, and
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* therefore different asynchronous bridges.
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*/
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2015-06-05 17:13:40 -06:00
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2015-06-05 17:38:08 -06:00
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/*
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* OMAP4 interconnect barrier which is called for each mb() and wmb().
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* This is to ensure that normal paths to DRAM (normal memory, cacheable
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* accesses) are properly synchronised with writes to DMA coherent memory
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* (normal memory, uncacheable) and device writes.
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*
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* The mb() and wmb() barriers only operate only on the MPU->MA->EMIF
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* path, as we need to ensure that data is visible to other system
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* masters prior to writes to those system masters being seen.
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*
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* Note: the SRAM path is not synchronised via mb() and wmb().
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*/
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static void omap4_mb(void)
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{
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if (dram_sync)
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writel_relaxed(0, dram_sync);
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}
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2015-06-05 17:13:40 -06:00
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2015-06-05 17:38:08 -06:00
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/*
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* OMAP4 Errata i688 - asynchronous bridge corruption when entering WFI.
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*
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* If a data is stalled inside asynchronous bridge because of back
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* pressure, it may be accepted multiple times, creating pointer
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* misalignment that will corrupt next transfers on that data path until
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* next reset of the system. No recovery procedure once the issue is hit,
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* the path remains consistently broken.
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*
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* Async bridges can be found on paths between MPU to EMIF and MPU to L3
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* interconnects.
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*
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* This situation can happen only when the idle is initiated by a Master
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* Request Disconnection (which is trigged by software when executing WFI
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* on the CPU).
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*
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* The work-around for this errata needs all the initiators connected
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* through an async bridge to ensure that data path is properly drained
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* before issuing WFI. This condition will be met if one Strongly ordered
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* access is performed to the target right before executing the WFI.
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*
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* In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
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* IO barrier ensure that there is no synchronisation loss on initiators
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* operating on both interconnect port simultaneously.
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*
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* This is a stronger version of the OMAP4 memory barrier below, and
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* operates on both the MPU->MA->EMIF path but also the MPU->OCP path
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* as well, and is necessary prior to executing a WFI.
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*/
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void omap_interconnect_sync(void)
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2015-06-05 17:13:40 -06:00
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{
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if (dram_sync && sram_sync) {
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writel_relaxed(readl_relaxed(dram_sync), dram_sync);
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writel_relaxed(readl_relaxed(sram_sync), sram_sync);
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isb();
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}
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}
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static int __init omap4_sram_init(void)
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{
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struct device_node *np;
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struct gen_pool *sram_pool;
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np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
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if (!np)
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pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
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__func__);
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2015-06-05 17:38:08 -06:00
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sram_pool = of_gen_pool_get(np, "sram", 0);
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2015-06-05 17:13:40 -06:00
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if (!sram_pool)
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pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
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__func__);
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else
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sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
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return 0;
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}
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omap_arch_initcall(omap4_sram_init);
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/* Steal one page physical memory for barrier implementation */
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2015-06-05 17:38:08 -06:00
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void __init omap_barrier_reserve_memblock(void)
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2015-06-05 17:13:40 -06:00
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{
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2015-06-05 17:38:08 -06:00
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dram_sync_size = ALIGN(PAGE_SIZE, SZ_1M);
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dram_sync_paddr = arm_memblock_steal(dram_sync_size, SZ_1M);
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2015-06-05 17:13:40 -06:00
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}
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void __init omap_barriers_init(void)
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{
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struct map_desc dram_io_desc[1];
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dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
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2015-06-05 17:38:08 -06:00
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dram_io_desc[0].pfn = __phys_to_pfn(dram_sync_paddr);
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dram_io_desc[0].length = dram_sync_size;
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2015-06-05 17:13:40 -06:00
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dram_io_desc[0].type = MT_MEMORY_RW_SO;
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iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
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dram_sync = (void __iomem *) dram_io_desc[0].virtual;
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2015-06-05 17:38:08 -06:00
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pr_info("OMAP4: Map %pa to %p for dram barrier\n",
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&dram_sync_paddr, dram_sync);
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2015-06-05 17:13:40 -06:00
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2015-06-05 17:38:08 -06:00
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soc_mb = omap4_mb;
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2015-06-05 17:13:40 -06:00
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}
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2015-06-05 17:38:08 -06:00
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2015-06-05 17:13:40 -06:00
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#endif
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ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control register change.
On OMAP4+ devices, GIC register context is lost when MPUSS hits
the OSWR(Open Switch Retention). On the CPU wakeup path, ROM code
gets executed and one of the steps in it is to restore the
saved context of the GIC. The ROM Code GIC distributor restoration
is split in two parts: CPU specific register done by each CPU and
common register done by only one CPU.
Below is the abstract flow.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[...]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU0 is online in OS
- CPU0 enables the GIC distributor. GICD.Enable Non-secure = 1
- CPU0 wakes up CPU1 with clock-domain force wakeup method.
- CPU0 continues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU1 is online in OS and start executing.
[...] -
GIC Restoration: /* Common routine for HS and GP devices */
{
if (GICD != 1) { /* This will be true in OSWR state */
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restores GIC distributor
else
- reconfigure GIC distributor to boot values.
GICD.Enable secure = 1
}
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restore its GIC CPU interface registers if saved.
else
- reconfigure its GIC CPU interface registers to boot
values.
}
...............................................................
So as mentioned in the flow, GICD != 1 condition decides how
the GIC registers are handled in ROM code wakeup path from
OSWR. As evident from the flow, ROM code relies on the entire
GICD register value and not specific register bits.
The assumption was valid till CortexA9 r1pX version since there
was only one banked bit to control secure and non-secure GICD.
Secure view which ROM code sees:
bit 0 == Enable Non-secure
Non-secure view which HLOS sees:
bit 0 == Enable secure
But GICD register has changed between CortexA9 r1pX and r2pX.
On r2pX GICD register is composed of 2 bits.
Secure view which ROM code sees:
bit 1 == Enable Non-secure
bit 0 == Enable secure
Non-secure view which HLOS sees:
bit 0 == Enable Non-secure
Hence on OMAP4460(r2pX) devices, if you go through the
above flow again during CPU1 wakeup, GICD == 3 and hence
ROM code fails to understand the real wakeup power state
and reconfigures GIC distributor to boot values. This is
nasty since you loose the entire interrupt controller
context in a live system.
The ROM code fix done on next OMAP4 device (OMAP4470 - r2px) is to
check "GICD.Enable secure != 1" for GIC restoration in OSWR wakeup path.
Since ROM code can't be fixed on OMAP4460 devices, a work around
needs to be implemented. As evident from the flow, as long as
CPU1 sees GICD == 1 in it's wakeup path from OSWR, the issue
won't happen. Below is the flow with the work-around.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[..]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU0 is online in OS.
- CPU0 does GICD.Enable Non-secure = 0
- CPU0 wakes up CPU1 with clock domain force wakeup method.
- CPU0 waits for GICD.Enable Non-secure = 1
- CPU0 coninues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU1 is online in OS
- CPU1 does GICD.Enable Non-secure = 1
- CPU1 start executing
[...]
...............................................................
With this procedure, the GIC configuration done between the
CPU0 wakeup and CPU1 wakeup will not be lost but during this
short windows, the CPU0 will not receive interrupts.
The BUG is applicable to only OMAP4460(r2pX) devices.
OMAP4470 (also r2pX) is not affected by this bug because
ROM code has been fixed.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-10-18 03:20:05 -06:00
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void gic_dist_disable(void)
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{
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if (gic_dist_base_addr)
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2014-04-15 11:37:46 -06:00
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writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
|
ARM: OMAP4460: Workaround for ROM bug because of CA9 r2pX GIC control register change.
On OMAP4+ devices, GIC register context is lost when MPUSS hits
the OSWR(Open Switch Retention). On the CPU wakeup path, ROM code
gets executed and one of the steps in it is to restore the
saved context of the GIC. The ROM Code GIC distributor restoration
is split in two parts: CPU specific register done by each CPU and
common register done by only one CPU.
Below is the abstract flow.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[...]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU0 is online in OS
- CPU0 enables the GIC distributor. GICD.Enable Non-secure = 1
- CPU0 wakes up CPU1 with clock-domain force wakeup method.
- CPU0 continues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU1 is online in OS and start executing.
[...] -
GIC Restoration: /* Common routine for HS and GP devices */
{
if (GICD != 1) { /* This will be true in OSWR state */
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restores GIC distributor
else
- reconfigure GIC distributor to boot values.
GICD.Enable secure = 1
}
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restore its GIC CPU interface registers if saved.
else
- reconfigure its GIC CPU interface registers to boot
values.
}
...............................................................
So as mentioned in the flow, GICD != 1 condition decides how
the GIC registers are handled in ROM code wakeup path from
OSWR. As evident from the flow, ROM code relies on the entire
GICD register value and not specific register bits.
The assumption was valid till CortexA9 r1pX version since there
was only one banked bit to control secure and non-secure GICD.
Secure view which ROM code sees:
bit 0 == Enable Non-secure
Non-secure view which HLOS sees:
bit 0 == Enable secure
But GICD register has changed between CortexA9 r1pX and r2pX.
On r2pX GICD register is composed of 2 bits.
Secure view which ROM code sees:
bit 1 == Enable Non-secure
bit 0 == Enable secure
Non-secure view which HLOS sees:
bit 0 == Enable Non-secure
Hence on OMAP4460(r2pX) devices, if you go through the
above flow again during CPU1 wakeup, GICD == 3 and hence
ROM code fails to understand the real wakeup power state
and reconfigures GIC distributor to boot values. This is
nasty since you loose the entire interrupt controller
context in a live system.
The ROM code fix done on next OMAP4 device (OMAP4470 - r2px) is to
check "GICD.Enable secure != 1" for GIC restoration in OSWR wakeup path.
Since ROM code can't be fixed on OMAP4460 devices, a work around
needs to be implemented. As evident from the flow, as long as
CPU1 sees GICD == 1 in it's wakeup path from OSWR, the issue
won't happen. Below is the flow with the work-around.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[..]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU0 is online in OS.
- CPU0 does GICD.Enable Non-secure = 0
- CPU0 wakes up CPU1 with clock domain force wakeup method.
- CPU0 waits for GICD.Enable Non-secure = 1
- CPU0 coninues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU1 is online in OS
- CPU1 does GICD.Enable Non-secure = 1
- CPU1 start executing
[...]
...............................................................
With this procedure, the GIC configuration done between the
CPU0 wakeup and CPU1 wakeup will not be lost but during this
short windows, the CPU0 will not receive interrupts.
The BUG is applicable to only OMAP4460(r2pX) devices.
OMAP4470 (also r2pX) is not affected by this bug because
ROM code has been fixed.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-10-18 03:20:05 -06:00
|
|
|
}
|
|
|
|
|
2013-10-22 13:07:15 -06:00
|
|
|
void gic_dist_enable(void)
|
|
|
|
{
|
|
|
|
if (gic_dist_base_addr)
|
2014-04-15 11:37:46 -06:00
|
|
|
writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
|
2013-10-22 13:07:15 -06:00
|
|
|
}
|
|
|
|
|
2012-10-18 03:20:08 -06:00
|
|
|
bool gic_dist_disabled(void)
|
|
|
|
{
|
2014-04-15 11:37:46 -06:00
|
|
|
return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
|
2012-10-18 03:20:08 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
void gic_timer_retrigger(void)
|
|
|
|
{
|
2014-04-15 11:37:46 -06:00
|
|
|
u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
|
|
|
|
u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
|
|
|
|
u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
|
2012-10-18 03:20:08 -06:00
|
|
|
|
|
|
|
if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
|
|
|
|
/*
|
|
|
|
* The local timer interrupt got lost while the distributor was
|
|
|
|
* disabled. Ack the pending interrupt, and retrigger it.
|
|
|
|
*/
|
|
|
|
pr_warn("%s: lost localtimer interrupt\n", __func__);
|
2014-04-15 11:37:46 -06:00
|
|
|
writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
|
2012-10-18 03:20:08 -06:00
|
|
|
if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
|
2014-04-15 11:37:46 -06:00
|
|
|
writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
|
2012-10-18 03:20:08 -06:00
|
|
|
twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
|
2014-04-15 11:37:46 -06:00
|
|
|
writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
|
2012-10-18 03:20:08 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-05-14 13:05:26 -06:00
|
|
|
#ifdef CONFIG_CACHE_L2X0
|
2010-07-31 10:10:10 -06:00
|
|
|
|
2011-03-03 05:33:25 -07:00
|
|
|
void __iomem *omap4_get_l2cache_base(void)
|
|
|
|
{
|
|
|
|
return l2cache_base;
|
|
|
|
}
|
|
|
|
|
2015-01-07 23:48:58 -07:00
|
|
|
void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
|
2010-07-31 10:10:10 -06:00
|
|
|
{
|
2014-03-16 11:45:56 -06:00
|
|
|
unsigned smc_op;
|
2010-07-31 10:10:10 -06:00
|
|
|
|
2014-03-16 11:45:56 -06:00
|
|
|
switch (reg) {
|
|
|
|
case L2X0_CTRL:
|
|
|
|
smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case L2X0_AUX_CTRL:
|
|
|
|
smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case L2X0_DEBUG_CTRL:
|
|
|
|
smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case L310_PREFETCH_CTRL:
|
|
|
|
smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
|
|
|
|
break;
|
|
|
|
|
2014-07-14 07:13:46 -06:00
|
|
|
case L310_POWER_CTRL:
|
|
|
|
pr_info_once("OMAP L2C310: ROM does not support power control setting\n");
|
|
|
|
return;
|
|
|
|
|
2014-03-16 11:45:56 -06:00
|
|
|
default:
|
|
|
|
WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
omap_smc1(smc_op, val);
|
2011-02-22 02:00:44 -07:00
|
|
|
}
|
|
|
|
|
2014-04-22 02:28:01 -06:00
|
|
|
int __init omap_l2_cache_init(void)
|
2010-05-14 13:05:26 -06:00
|
|
|
{
|
|
|
|
/* Static mapping, never released */
|
|
|
|
l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
|
2011-03-03 05:06:52 -07:00
|
|
|
if (WARN_ON(!l2cache_base))
|
|
|
|
return -ENOMEM;
|
2010-05-14 13:05:26 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
2011-01-01 07:26:04 -07:00
|
|
|
|
|
|
|
void __iomem *omap4_get_sar_ram_base(void)
|
|
|
|
{
|
|
|
|
return sar_ram_base;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2016-06-22 02:59:39 -06:00
|
|
|
* SAR RAM used to save and restore the HW context in low power modes.
|
|
|
|
* Note that we need to initialize this very early for kexec. See
|
|
|
|
* omap4_mpuss_early_init().
|
2011-01-01 07:26:04 -07:00
|
|
|
*/
|
2016-06-22 02:59:39 -06:00
|
|
|
void __init omap4_sar_ram_init(void)
|
2011-01-01 07:26:04 -07:00
|
|
|
{
|
2013-02-06 05:24:39 -07:00
|
|
|
unsigned long sar_base;
|
|
|
|
|
2011-01-01 07:26:04 -07:00
|
|
|
/*
|
|
|
|
* To avoid code running on other OMAPs in
|
|
|
|
* multi-omap builds
|
|
|
|
*/
|
2013-02-06 05:24:39 -07:00
|
|
|
if (cpu_is_omap44xx())
|
|
|
|
sar_base = OMAP44XX_SAR_RAM_BASE;
|
|
|
|
else if (soc_is_omap54xx())
|
|
|
|
sar_base = OMAP54XX_SAR_RAM_BASE;
|
|
|
|
else
|
2016-06-22 02:59:39 -06:00
|
|
|
return;
|
2011-01-01 07:26:04 -07:00
|
|
|
|
|
|
|
/* Static mapping, never released */
|
2013-02-06 05:24:39 -07:00
|
|
|
sar_ram_base = ioremap(sar_base, SZ_16K);
|
2011-01-01 07:26:04 -07:00
|
|
|
if (WARN_ON(!sar_ram_base))
|
2016-06-22 02:59:39 -06:00
|
|
|
return;
|
2011-01-01 07:26:04 -07:00
|
|
|
}
|
2012-04-25 05:57:46 -06:00
|
|
|
|
2015-03-11 09:43:49 -06:00
|
|
|
static const struct of_device_id intc_match[] = {
|
|
|
|
{ .compatible = "ti,omap4-wugen-mpu", },
|
|
|
|
{ .compatible = "ti,omap5-wugen-mpu", },
|
2015-01-17 03:21:08 -07:00
|
|
|
{ },
|
|
|
|
};
|
|
|
|
|
2015-03-11 09:43:49 -06:00
|
|
|
static struct device_node *intc_node;
|
2015-01-17 03:21:08 -07:00
|
|
|
|
|
|
|
unsigned int omap4_xlate_irq(unsigned int hwirq)
|
|
|
|
{
|
|
|
|
struct of_phandle_args irq_data;
|
|
|
|
unsigned int irq;
|
|
|
|
|
2015-03-11 09:43:49 -06:00
|
|
|
if (!intc_node)
|
|
|
|
intc_node = of_find_matching_node(NULL, intc_match);
|
2015-01-17 03:21:08 -07:00
|
|
|
|
2015-03-11 09:43:49 -06:00
|
|
|
if (WARN_ON(!intc_node))
|
2015-01-17 03:21:08 -07:00
|
|
|
return hwirq;
|
|
|
|
|
2015-03-11 09:43:49 -06:00
|
|
|
irq_data.np = intc_node;
|
2015-01-17 03:21:08 -07:00
|
|
|
irq_data.args_count = 3;
|
|
|
|
irq_data.args[0] = 0;
|
|
|
|
irq_data.args[1] = hwirq - OMAP44XX_IRQ_GIC_START;
|
|
|
|
irq_data.args[2] = IRQ_TYPE_LEVEL_HIGH;
|
|
|
|
|
|
|
|
irq = irq_create_of_mapping(&irq_data);
|
|
|
|
if (WARN_ON(!irq))
|
|
|
|
irq = hwirq;
|
|
|
|
|
|
|
|
return irq;
|
|
|
|
}
|
|
|
|
|
2012-06-05 05:01:06 -06:00
|
|
|
void __init omap_gic_of_init(void)
|
|
|
|
{
|
2013-02-25 01:42:58 -07:00
|
|
|
struct device_node *np;
|
|
|
|
|
2015-03-11 09:43:49 -06:00
|
|
|
intc_node = of_find_matching_node(NULL, intc_match);
|
|
|
|
if (WARN_ON(!intc_node)) {
|
|
|
|
pr_err("No WUGEN found in DT, system will misbehave.\n");
|
|
|
|
pr_err("UPDATE YOUR DEVICE TREE!\n");
|
|
|
|
}
|
|
|
|
|
2013-02-25 01:42:58 -07:00
|
|
|
/* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
|
|
|
|
if (!cpu_is_omap446x())
|
|
|
|
goto skip_errata_init;
|
|
|
|
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
|
|
|
|
gic_dist_base_addr = of_iomap(np, 0);
|
|
|
|
WARN_ON(!gic_dist_base_addr);
|
|
|
|
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
|
|
|
|
twd_base = of_iomap(np, 0);
|
|
|
|
WARN_ON(!twd_base);
|
|
|
|
|
|
|
|
skip_errata_init:
|
2012-11-05 15:18:28 -07:00
|
|
|
irqchip_init();
|
2012-06-05 05:01:06 -06:00
|
|
|
}
|