2009-06-05 06:42:42 -06:00
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/*
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* Copyright 2009 Jerome Glisse.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
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* Dave Airlie
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*/
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#include <ttm/ttm_bo_api.h>
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#include <ttm/ttm_bo_driver.h>
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#include <ttm/ttm_placement.h>
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#include <ttm/ttm_module.h>
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2010-04-01 06:44:59 -06:00
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#include <ttm/ttm_page_alloc.h>
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2009-06-05 06:42:42 -06:00
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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2009-08-25 21:13:37 -06:00
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#include <linux/seq_file.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2013-02-01 11:44:33 -07:00
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#include <linux/swiotlb.h>
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2009-06-05 06:42:42 -06:00
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#include "radeon_reg.h"
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#include "radeon.h"
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#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
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2009-08-25 21:13:37 -06:00
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static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
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2009-06-05 06:42:42 -06:00
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static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
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{
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struct radeon_mman *mman;
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struct radeon_device *rdev;
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mman = container_of(bdev, struct radeon_mman, bdev);
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rdev = container_of(mman, struct radeon_device, mman);
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return rdev;
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}
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/*
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* Global memory.
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*/
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2010-03-08 17:56:52 -07:00
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static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
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2009-06-05 06:42:42 -06:00
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{
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return ttm_mem_global_init(ref->object);
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}
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2010-03-08 17:56:52 -07:00
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static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
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2009-06-05 06:42:42 -06:00
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{
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ttm_mem_global_release(ref->object);
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}
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static int radeon_ttm_global_init(struct radeon_device *rdev)
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{
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2010-03-08 17:56:52 -07:00
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struct drm_global_reference *global_ref;
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2009-06-05 06:42:42 -06:00
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int r;
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rdev->mman.mem_global_referenced = false;
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global_ref = &rdev->mman.mem_global_ref;
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2010-03-08 17:56:52 -07:00
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global_ref->global_type = DRM_GLOBAL_TTM_MEM;
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2009-06-05 06:42:42 -06:00
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global_ref->size = sizeof(struct ttm_mem_global);
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global_ref->init = &radeon_ttm_mem_global_init;
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global_ref->release = &radeon_ttm_mem_global_release;
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2010-03-08 17:56:52 -07:00
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r = drm_global_item_ref(global_ref);
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2009-06-05 06:42:42 -06:00
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if (r != 0) {
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2009-08-18 08:51:56 -06:00
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DRM_ERROR("Failed setting up TTM memory accounting "
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"subsystem.\n");
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2009-06-05 06:42:42 -06:00
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return r;
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}
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2009-08-18 08:51:56 -06:00
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rdev->mman.bo_global_ref.mem_glob =
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rdev->mman.mem_global_ref.object;
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global_ref = &rdev->mman.bo_global_ref.ref;
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2010-03-08 17:56:52 -07:00
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global_ref->global_type = DRM_GLOBAL_TTM_BO;
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2009-08-20 02:29:08 -06:00
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global_ref->size = sizeof(struct ttm_bo_global);
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2009-08-18 08:51:56 -06:00
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global_ref->init = &ttm_bo_global_init;
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global_ref->release = &ttm_bo_global_release;
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2010-03-08 17:56:52 -07:00
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r = drm_global_item_ref(global_ref);
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2009-08-18 08:51:56 -06:00
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if (r != 0) {
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DRM_ERROR("Failed setting up TTM BO subsystem.\n");
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2010-03-08 17:56:52 -07:00
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drm_global_item_unref(&rdev->mman.mem_global_ref);
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2009-08-18 08:51:56 -06:00
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return r;
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}
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2009-06-05 06:42:42 -06:00
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rdev->mman.mem_global_referenced = true;
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return 0;
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}
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static void radeon_ttm_global_fini(struct radeon_device *rdev)
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{
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if (rdev->mman.mem_global_referenced) {
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2010-03-08 17:56:52 -07:00
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drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
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drm_global_item_unref(&rdev->mman.mem_global_ref);
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2009-06-05 06:42:42 -06:00
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rdev->mman.mem_global_referenced = false;
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}
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}
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static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
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{
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return 0;
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}
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static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
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struct ttm_mem_type_manager *man)
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{
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struct radeon_device *rdev;
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rdev = radeon_get_rdev(bdev);
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switch (type) {
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case TTM_PL_SYSTEM:
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/* System memory */
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man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
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man->available_caching = TTM_PL_MASK_CACHING;
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man->default_caching = TTM_PL_FLAG_CACHED;
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break;
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case TTM_PL_TT:
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2010-08-04 18:48:18 -06:00
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man->func = &ttm_bo_manager_func;
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
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man->gpu_offset = rdev->mc.gtt_start;
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2009-06-05 06:42:42 -06:00
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man->available_caching = TTM_PL_MASK_CACHING;
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man->default_caching = TTM_PL_FLAG_CACHED;
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2009-06-15 08:56:11 -06:00
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man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
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2009-06-05 06:42:42 -06:00
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#if __OS_HAS_AGP
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if (rdev->flags & RADEON_IS_AGP) {
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if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) {
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DRM_ERROR("AGP is not enabled for memory type %u\n",
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(unsigned)type);
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return -EINVAL;
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}
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2009-06-15 08:56:11 -06:00
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if (!rdev->ddev->agp->cant_use_aperture)
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2010-04-09 06:39:24 -06:00
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man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
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2009-06-05 06:42:42 -06:00
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man->available_caching = TTM_PL_FLAG_UNCACHED |
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TTM_PL_FLAG_WC;
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man->default_caching = TTM_PL_FLAG_WC;
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}
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2010-04-07 04:21:27 -06:00
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#endif
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2009-06-05 06:42:42 -06:00
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break;
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case TTM_PL_VRAM:
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/* "On-card" video ram */
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2010-08-04 18:48:18 -06:00
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man->func = &ttm_bo_manager_func;
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
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man->gpu_offset = rdev->mc.vram_start;
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2009-06-05 06:42:42 -06:00
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man->flags = TTM_MEMTYPE_FLAG_FIXED |
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TTM_MEMTYPE_FLAG_MAPPABLE;
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man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
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man->default_caching = TTM_PL_FLAG_WC;
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break;
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default:
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DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
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return -EINVAL;
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}
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return 0;
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}
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2009-12-07 07:52:58 -07:00
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static void radeon_evict_flags(struct ttm_buffer_object *bo,
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struct ttm_placement *placement)
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2009-06-05 06:42:42 -06:00
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|
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{
|
2009-12-14 13:02:09 -07:00
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struct radeon_bo *rbo;
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|
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static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
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|
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|
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if (!radeon_ttm_bo_is_radeon_bo(bo)) {
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|
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placement->fpfn = 0;
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placement->lpfn = 0;
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placement->placement = &placements;
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placement->busy_placement = &placements;
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|
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placement->num_placement = 1;
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placement->num_busy_placement = 1;
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|
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return;
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|
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}
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|
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|
rbo = container_of(bo, struct radeon_bo, tbo);
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2009-06-05 06:42:42 -06:00
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|
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switch (bo->mem.mem_type) {
|
2009-12-07 07:52:58 -07:00
|
|
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case TTM_PL_VRAM:
|
2011-10-23 04:56:27 -06:00
|
|
|
if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false)
|
2010-01-12 16:21:49 -07:00
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radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
|
|
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|
else
|
|
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|
radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
|
2009-12-07 07:52:58 -07:00
|
|
|
break;
|
|
|
|
case TTM_PL_TT:
|
2009-06-05 06:42:42 -06:00
|
|
|
default:
|
2009-12-07 07:52:58 -07:00
|
|
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radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
|
2009-06-05 06:42:42 -06:00
|
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}
|
2009-12-09 13:57:37 -07:00
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|
|
*placement = rbo->placement;
|
2009-06-05 06:42:42 -06:00
|
|
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}
|
|
|
|
|
|
|
|
static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
|
|
|
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{
|
|
|
|
return 0;
|
|
|
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}
|
|
|
|
|
|
|
|
static void radeon_move_null(struct ttm_buffer_object *bo,
|
|
|
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struct ttm_mem_reg *new_mem)
|
|
|
|
{
|
|
|
|
struct ttm_mem_reg *old_mem = &bo->mem;
|
|
|
|
|
|
|
|
BUG_ON(old_mem->mm_node != NULL);
|
|
|
|
*old_mem = *new_mem;
|
|
|
|
new_mem->mm_node = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int radeon_move_blit(struct ttm_buffer_object *bo,
|
2012-11-28 04:25:44 -07:00
|
|
|
bool evict, bool no_wait_gpu,
|
2010-04-07 04:21:19 -06:00
|
|
|
struct ttm_mem_reg *new_mem,
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|
|
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struct ttm_mem_reg *old_mem)
|
2009-06-05 06:42:42 -06:00
|
|
|
{
|
|
|
|
struct radeon_device *rdev;
|
|
|
|
uint64_t old_start, new_start;
|
2012-05-08 06:24:01 -06:00
|
|
|
struct radeon_fence *fence;
|
|
|
|
int r, ridx;
|
2009-06-05 06:42:42 -06:00
|
|
|
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|
|
|
rdev = radeon_get_rdev(bo->bdev);
|
2012-05-08 06:24:01 -06:00
|
|
|
ridx = radeon_copy_ring_index(rdev);
|
2010-08-04 18:48:18 -06:00
|
|
|
old_start = old_mem->start << PAGE_SHIFT;
|
|
|
|
new_start = new_mem->start << PAGE_SHIFT;
|
2009-06-05 06:42:42 -06:00
|
|
|
|
|
|
|
switch (old_mem->mem_type) {
|
|
|
|
case TTM_PL_VRAM:
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
|
|
|
old_start += rdev->mc.vram_start;
|
2009-06-05 06:42:42 -06:00
|
|
|
break;
|
|
|
|
case TTM_PL_TT:
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
|
|
|
old_start += rdev->mc.gtt_start;
|
2009-06-05 06:42:42 -06:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
switch (new_mem->mem_type) {
|
|
|
|
case TTM_PL_VRAM:
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
|
|
|
new_start += rdev->mc.vram_start;
|
2009-06-05 06:42:42 -06:00
|
|
|
break;
|
|
|
|
case TTM_PL_TT:
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
|
|
|
new_start += rdev->mc.gtt_start;
|
2009-06-05 06:42:42 -06:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2012-05-08 06:24:01 -06:00
|
|
|
if (!rdev->ring[ridx].ready) {
|
2012-01-05 20:11:07 -07:00
|
|
|
DRM_ERROR("Trying to move memory with ring turned off.\n");
|
2009-06-05 06:42:42 -06:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
2011-09-16 10:04:08 -06:00
|
|
|
|
|
|
|
BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
|
|
|
|
|
2012-01-05 20:11:07 -07:00
|
|
|
/* sync other rings */
|
2012-05-08 06:24:01 -06:00
|
|
|
fence = bo->sync_obj;
|
2011-09-16 10:04:08 -06:00
|
|
|
r = radeon_copy(rdev, old_start, new_start,
|
|
|
|
new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */
|
2012-05-08 06:24:01 -06:00
|
|
|
&fence);
|
2009-06-05 06:42:42 -06:00
|
|
|
/* FIXME: handle copy error */
|
2012-10-12 09:03:11 -06:00
|
|
|
r = ttm_bo_move_accel_cleanup(bo, (void *)fence,
|
2012-11-28 04:25:44 -07:00
|
|
|
evict, no_wait_gpu, new_mem);
|
2009-06-05 06:42:42 -06:00
|
|
|
radeon_fence_unref(&fence);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
|
2010-04-07 04:21:19 -06:00
|
|
|
bool evict, bool interruptible,
|
2012-11-28 04:25:44 -07:00
|
|
|
bool no_wait_gpu,
|
2009-06-05 06:42:42 -06:00
|
|
|
struct ttm_mem_reg *new_mem)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev;
|
|
|
|
struct ttm_mem_reg *old_mem = &bo->mem;
|
|
|
|
struct ttm_mem_reg tmp_mem;
|
2009-12-07 07:52:58 -07:00
|
|
|
u32 placements;
|
|
|
|
struct ttm_placement placement;
|
2009-06-05 06:42:42 -06:00
|
|
|
int r;
|
|
|
|
|
|
|
|
rdev = radeon_get_rdev(bo->bdev);
|
|
|
|
tmp_mem = *new_mem;
|
|
|
|
tmp_mem.mm_node = NULL;
|
2009-12-07 07:52:58 -07:00
|
|
|
placement.fpfn = 0;
|
|
|
|
placement.lpfn = 0;
|
|
|
|
placement.num_placement = 1;
|
|
|
|
placement.placement = &placements;
|
|
|
|
placement.num_busy_placement = 1;
|
|
|
|
placement.busy_placement = &placements;
|
|
|
|
placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
|
|
|
|
r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
|
2012-11-28 04:25:44 -07:00
|
|
|
interruptible, no_wait_gpu);
|
2009-06-05 06:42:42 -06:00
|
|
|
if (unlikely(r)) {
|
|
|
|
return r;
|
|
|
|
}
|
2009-10-29 21:31:26 -06:00
|
|
|
|
|
|
|
r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
|
|
|
|
if (unlikely(r)) {
|
|
|
|
goto out_cleanup;
|
|
|
|
}
|
|
|
|
|
2009-06-05 06:42:42 -06:00
|
|
|
r = ttm_tt_bind(bo->ttm, &tmp_mem);
|
|
|
|
if (unlikely(r)) {
|
|
|
|
goto out_cleanup;
|
|
|
|
}
|
2012-11-28 04:25:44 -07:00
|
|
|
r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
|
2009-06-05 06:42:42 -06:00
|
|
|
if (unlikely(r)) {
|
|
|
|
goto out_cleanup;
|
|
|
|
}
|
2012-11-28 04:25:44 -07:00
|
|
|
r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
|
2009-06-05 06:42:42 -06:00
|
|
|
out_cleanup:
|
2010-08-03 20:07:08 -06:00
|
|
|
ttm_bo_mem_put(bo, &tmp_mem);
|
2009-06-05 06:42:42 -06:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
|
2010-04-07 04:21:19 -06:00
|
|
|
bool evict, bool interruptible,
|
2012-11-28 04:25:44 -07:00
|
|
|
bool no_wait_gpu,
|
2009-06-05 06:42:42 -06:00
|
|
|
struct ttm_mem_reg *new_mem)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev;
|
|
|
|
struct ttm_mem_reg *old_mem = &bo->mem;
|
|
|
|
struct ttm_mem_reg tmp_mem;
|
2009-12-07 07:52:58 -07:00
|
|
|
struct ttm_placement placement;
|
|
|
|
u32 placements;
|
2009-06-05 06:42:42 -06:00
|
|
|
int r;
|
|
|
|
|
|
|
|
rdev = radeon_get_rdev(bo->bdev);
|
|
|
|
tmp_mem = *new_mem;
|
|
|
|
tmp_mem.mm_node = NULL;
|
2009-12-07 07:52:58 -07:00
|
|
|
placement.fpfn = 0;
|
|
|
|
placement.lpfn = 0;
|
|
|
|
placement.num_placement = 1;
|
|
|
|
placement.placement = &placements;
|
|
|
|
placement.num_busy_placement = 1;
|
|
|
|
placement.busy_placement = &placements;
|
|
|
|
placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
|
2012-11-28 04:25:44 -07:00
|
|
|
r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
|
|
|
|
interruptible, no_wait_gpu);
|
2009-06-05 06:42:42 -06:00
|
|
|
if (unlikely(r)) {
|
|
|
|
return r;
|
|
|
|
}
|
2012-11-28 04:25:44 -07:00
|
|
|
r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
|
2009-06-05 06:42:42 -06:00
|
|
|
if (unlikely(r)) {
|
|
|
|
goto out_cleanup;
|
|
|
|
}
|
2012-11-28 04:25:44 -07:00
|
|
|
r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
|
2009-06-05 06:42:42 -06:00
|
|
|
if (unlikely(r)) {
|
|
|
|
goto out_cleanup;
|
|
|
|
}
|
|
|
|
out_cleanup:
|
2010-08-03 20:07:08 -06:00
|
|
|
ttm_bo_mem_put(bo, &tmp_mem);
|
2009-06-05 06:42:42 -06:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int radeon_bo_move(struct ttm_buffer_object *bo,
|
2010-04-07 04:21:19 -06:00
|
|
|
bool evict, bool interruptible,
|
2012-11-28 04:25:44 -07:00
|
|
|
bool no_wait_gpu,
|
2010-04-07 04:21:19 -06:00
|
|
|
struct ttm_mem_reg *new_mem)
|
2009-06-05 06:42:42 -06:00
|
|
|
{
|
|
|
|
struct radeon_device *rdev;
|
|
|
|
struct ttm_mem_reg *old_mem = &bo->mem;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
rdev = radeon_get_rdev(bo->bdev);
|
|
|
|
if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
|
|
|
|
radeon_move_null(bo, new_mem);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
if ((old_mem->mem_type == TTM_PL_TT &&
|
|
|
|
new_mem->mem_type == TTM_PL_SYSTEM) ||
|
|
|
|
(old_mem->mem_type == TTM_PL_SYSTEM &&
|
|
|
|
new_mem->mem_type == TTM_PL_TT)) {
|
tree-wide: fix assorted typos all over the place
That is "success", "unknown", "through", "performance", "[re|un]mapping"
, "access", "default", "reasonable", "[con]currently", "temperature"
, "channel", "[un]used", "application", "example","hierarchy", "therefore"
, "[over|under]flow", "contiguous", "threshold", "enough" and others.
Signed-off-by: André Goddard Rosa <andre.goddard@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2009-11-14 08:09:05 -07:00
|
|
|
/* bind is enough */
|
2009-06-05 06:42:42 -06:00
|
|
|
radeon_move_null(bo, new_mem);
|
|
|
|
return 0;
|
|
|
|
}
|
2012-02-23 15:53:42 -07:00
|
|
|
if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
|
|
|
|
rdev->asic->copy.copy == NULL) {
|
2009-06-05 06:42:42 -06:00
|
|
|
/* use memcpy */
|
2009-07-28 04:30:56 -06:00
|
|
|
goto memcpy;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
if (old_mem->mem_type == TTM_PL_VRAM &&
|
|
|
|
new_mem->mem_type == TTM_PL_SYSTEM) {
|
2009-07-28 04:30:56 -06:00
|
|
|
r = radeon_move_vram_ram(bo, evict, interruptible,
|
2012-11-28 04:25:44 -07:00
|
|
|
no_wait_gpu, new_mem);
|
2009-06-05 06:42:42 -06:00
|
|
|
} else if (old_mem->mem_type == TTM_PL_SYSTEM &&
|
|
|
|
new_mem->mem_type == TTM_PL_VRAM) {
|
2009-07-28 04:30:56 -06:00
|
|
|
r = radeon_move_ram_vram(bo, evict, interruptible,
|
2012-11-28 04:25:44 -07:00
|
|
|
no_wait_gpu, new_mem);
|
2009-06-05 06:42:42 -06:00
|
|
|
} else {
|
2012-11-28 04:25:44 -07:00
|
|
|
r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem);
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
2009-07-28 04:30:56 -06:00
|
|
|
|
|
|
|
if (r) {
|
|
|
|
memcpy:
|
2012-11-28 04:25:44 -07:00
|
|
|
r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
|
2009-07-28 04:30:56 -06:00
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2010-04-09 06:39:24 -06:00
|
|
|
static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
|
|
|
|
{
|
|
|
|
struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
|
|
|
|
struct radeon_device *rdev = radeon_get_rdev(bdev);
|
|
|
|
|
|
|
|
mem->bus.addr = NULL;
|
|
|
|
mem->bus.offset = 0;
|
|
|
|
mem->bus.size = mem->num_pages << PAGE_SHIFT;
|
|
|
|
mem->bus.base = 0;
|
|
|
|
mem->bus.is_iomem = false;
|
|
|
|
if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
|
|
|
|
return -EINVAL;
|
|
|
|
switch (mem->mem_type) {
|
|
|
|
case TTM_PL_SYSTEM:
|
|
|
|
/* system memory */
|
|
|
|
return 0;
|
|
|
|
case TTM_PL_TT:
|
|
|
|
#if __OS_HAS_AGP
|
|
|
|
if (rdev->flags & RADEON_IS_AGP) {
|
|
|
|
/* RADEON_IS_AGP is set only if AGP is active */
|
2010-08-04 18:48:18 -06:00
|
|
|
mem->bus.offset = mem->start << PAGE_SHIFT;
|
2010-04-09 06:39:24 -06:00
|
|
|
mem->bus.base = rdev->mc.agp_base;
|
2010-05-19 04:46:22 -06:00
|
|
|
mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
|
2010-04-09 06:39:24 -06:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
break;
|
|
|
|
case TTM_PL_VRAM:
|
2010-08-04 18:48:18 -06:00
|
|
|
mem->bus.offset = mem->start << PAGE_SHIFT;
|
2010-04-09 06:39:24 -06:00
|
|
|
/* check if it's visible */
|
|
|
|
if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
|
|
|
|
return -EINVAL;
|
|
|
|
mem->bus.base = rdev->mc.aper_base;
|
|
|
|
mem->bus.is_iomem = true;
|
2011-07-06 17:57:13 -06:00
|
|
|
#ifdef __alpha__
|
|
|
|
/*
|
|
|
|
* Alpha: use bus.addr to hold the ioremap() return,
|
|
|
|
* so we can modify bus.base below.
|
|
|
|
*/
|
|
|
|
if (mem->placement & TTM_PL_FLAG_WC)
|
|
|
|
mem->bus.addr =
|
|
|
|
ioremap_wc(mem->bus.base + mem->bus.offset,
|
|
|
|
mem->bus.size);
|
|
|
|
else
|
|
|
|
mem->bus.addr =
|
|
|
|
ioremap_nocache(mem->bus.base + mem->bus.offset,
|
|
|
|
mem->bus.size);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Alpha: Use just the bus offset plus
|
|
|
|
* the hose/domain memory base for bus.base.
|
|
|
|
* It then can be used to build PTEs for VRAM
|
|
|
|
* access, as done in ttm_bo_vm_fault().
|
|
|
|
*/
|
|
|
|
mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
|
|
|
|
rdev->ddev->hose->dense_mem_base;
|
|
|
|
#endif
|
2010-04-09 06:39:24 -06:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2012-10-12 09:04:00 -06:00
|
|
|
static int radeon_sync_obj_wait(void *sync_obj, bool lazy, bool interruptible)
|
2009-06-05 06:42:42 -06:00
|
|
|
{
|
|
|
|
return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible);
|
|
|
|
}
|
|
|
|
|
2012-10-12 09:04:00 -06:00
|
|
|
static int radeon_sync_obj_flush(void *sync_obj)
|
2009-06-05 06:42:42 -06:00
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void radeon_sync_obj_unref(void **sync_obj)
|
|
|
|
{
|
|
|
|
radeon_fence_unref((struct radeon_fence **)sync_obj);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void *radeon_sync_obj_ref(void *sync_obj)
|
|
|
|
{
|
|
|
|
return radeon_fence_ref((struct radeon_fence *)sync_obj);
|
|
|
|
}
|
|
|
|
|
2012-10-12 09:04:00 -06:00
|
|
|
static bool radeon_sync_obj_signaled(void *sync_obj)
|
2009-06-05 06:42:42 -06:00
|
|
|
{
|
|
|
|
return radeon_fence_signaled((struct radeon_fence *)sync_obj);
|
|
|
|
}
|
|
|
|
|
2011-11-01 18:46:13 -06:00
|
|
|
/*
|
|
|
|
* TTM backend functions.
|
|
|
|
*/
|
|
|
|
struct radeon_ttm_tt {
|
2011-11-09 15:15:26 -07:00
|
|
|
struct ttm_dma_tt ttm;
|
2011-11-01 18:46:13 -06:00
|
|
|
struct radeon_device *rdev;
|
|
|
|
u64 offset;
|
|
|
|
};
|
|
|
|
|
|
|
|
static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
|
|
|
|
struct ttm_mem_reg *bo_mem)
|
|
|
|
{
|
2011-11-09 15:15:26 -07:00
|
|
|
struct radeon_ttm_tt *gtt = (void*)ttm;
|
2011-11-01 18:46:13 -06:00
|
|
|
int r;
|
|
|
|
|
|
|
|
gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
|
|
|
|
if (!ttm->num_pages) {
|
|
|
|
WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
|
|
|
|
ttm->num_pages, bo_mem, ttm);
|
|
|
|
}
|
|
|
|
r = radeon_gart_bind(gtt->rdev, gtt->offset,
|
2011-11-09 15:15:26 -07:00
|
|
|
ttm->num_pages, ttm->pages, gtt->ttm.dma_address);
|
2011-11-01 18:46:13 -06:00
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
|
|
|
|
ttm->num_pages, (unsigned)gtt->offset);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
|
|
|
|
{
|
2011-11-09 15:15:26 -07:00
|
|
|
struct radeon_ttm_tt *gtt = (void *)ttm;
|
2011-11-01 18:46:13 -06:00
|
|
|
|
|
|
|
radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
|
|
|
|
{
|
2011-11-09 15:15:26 -07:00
|
|
|
struct radeon_ttm_tt *gtt = (void *)ttm;
|
2011-11-01 18:46:13 -06:00
|
|
|
|
2011-11-09 15:15:26 -07:00
|
|
|
ttm_dma_tt_fini(>t->ttm);
|
2011-11-01 18:46:13 -06:00
|
|
|
kfree(gtt);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct ttm_backend_func radeon_backend_func = {
|
|
|
|
.bind = &radeon_ttm_backend_bind,
|
|
|
|
.unbind = &radeon_ttm_backend_unbind,
|
|
|
|
.destroy = &radeon_ttm_backend_destroy,
|
|
|
|
};
|
|
|
|
|
2012-08-31 11:43:50 -06:00
|
|
|
static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
|
2011-11-01 18:46:13 -06:00
|
|
|
unsigned long size, uint32_t page_flags,
|
|
|
|
struct page *dummy_read_page)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev;
|
|
|
|
struct radeon_ttm_tt *gtt;
|
|
|
|
|
|
|
|
rdev = radeon_get_rdev(bdev);
|
|
|
|
#if __OS_HAS_AGP
|
|
|
|
if (rdev->flags & RADEON_IS_AGP) {
|
|
|
|
return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge,
|
|
|
|
size, page_flags, dummy_read_page);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
|
|
|
|
if (gtt == NULL) {
|
|
|
|
return NULL;
|
|
|
|
}
|
2011-11-09 15:15:26 -07:00
|
|
|
gtt->ttm.ttm.func = &radeon_backend_func;
|
2011-11-01 18:46:13 -06:00
|
|
|
gtt->rdev = rdev;
|
2011-11-09 15:15:26 -07:00
|
|
|
if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) {
|
|
|
|
kfree(gtt);
|
2011-11-01 18:46:13 -06:00
|
|
|
return NULL;
|
|
|
|
}
|
2011-11-09 15:15:26 -07:00
|
|
|
return >t->ttm.ttm;
|
2011-11-01 18:46:13 -06:00
|
|
|
}
|
|
|
|
|
2011-10-17 15:15:08 -06:00
|
|
|
static int radeon_ttm_tt_populate(struct ttm_tt *ttm)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev;
|
2011-11-09 15:15:26 -07:00
|
|
|
struct radeon_ttm_tt *gtt = (void *)ttm;
|
2011-10-17 15:15:08 -06:00
|
|
|
unsigned i;
|
|
|
|
int r;
|
2012-05-10 16:33:13 -06:00
|
|
|
bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
|
2011-10-17 15:15:08 -06:00
|
|
|
|
|
|
|
if (ttm->state != tt_unpopulated)
|
|
|
|
return 0;
|
|
|
|
|
2012-05-10 16:33:13 -06:00
|
|
|
if (slave && ttm->sg) {
|
|
|
|
drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
|
|
|
|
gtt->ttm.dma_address, ttm->num_pages);
|
|
|
|
ttm->state = tt_unbound;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-10-17 15:15:08 -06:00
|
|
|
rdev = radeon_get_rdev(ttm->bdev);
|
2012-01-03 15:37:37 -07:00
|
|
|
#if __OS_HAS_AGP
|
|
|
|
if (rdev->flags & RADEON_IS_AGP) {
|
|
|
|
return ttm_agp_tt_populate(ttm);
|
|
|
|
}
|
|
|
|
#endif
|
2011-10-17 15:15:08 -06:00
|
|
|
|
|
|
|
#ifdef CONFIG_SWIOTLB
|
|
|
|
if (swiotlb_nr_tbl()) {
|
2011-11-09 15:15:26 -07:00
|
|
|
return ttm_dma_populate(>t->ttm, rdev->dev);
|
2011-10-17 15:15:08 -06:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
r = ttm_pool_populate(ttm);
|
|
|
|
if (r) {
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < ttm->num_pages; i++) {
|
2011-11-09 15:15:26 -07:00
|
|
|
gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
|
|
|
|
0, PAGE_SIZE,
|
|
|
|
PCI_DMA_BIDIRECTIONAL);
|
|
|
|
if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
|
2011-10-17 15:15:08 -06:00
|
|
|
while (--i) {
|
2011-11-09 15:15:26 -07:00
|
|
|
pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
|
2011-10-17 15:15:08 -06:00
|
|
|
PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
|
2011-11-09 15:15:26 -07:00
|
|
|
gtt->ttm.dma_address[i] = 0;
|
2011-10-17 15:15:08 -06:00
|
|
|
}
|
|
|
|
ttm_pool_unpopulate(ttm);
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev;
|
2011-11-09 15:15:26 -07:00
|
|
|
struct radeon_ttm_tt *gtt = (void *)ttm;
|
2011-10-17 15:15:08 -06:00
|
|
|
unsigned i;
|
2012-05-10 16:33:13 -06:00
|
|
|
bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
|
|
|
|
|
|
|
|
if (slave)
|
|
|
|
return;
|
2011-10-17 15:15:08 -06:00
|
|
|
|
|
|
|
rdev = radeon_get_rdev(ttm->bdev);
|
2012-01-03 15:37:37 -07:00
|
|
|
#if __OS_HAS_AGP
|
|
|
|
if (rdev->flags & RADEON_IS_AGP) {
|
|
|
|
ttm_agp_tt_unpopulate(ttm);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
2011-10-17 15:15:08 -06:00
|
|
|
|
|
|
|
#ifdef CONFIG_SWIOTLB
|
|
|
|
if (swiotlb_nr_tbl()) {
|
2011-11-09 15:15:26 -07:00
|
|
|
ttm_dma_unpopulate(>t->ttm, rdev->dev);
|
2011-10-17 15:15:08 -06:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
for (i = 0; i < ttm->num_pages; i++) {
|
2011-11-09 15:15:26 -07:00
|
|
|
if (gtt->ttm.dma_address[i]) {
|
|
|
|
pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
|
2011-10-17 15:15:08 -06:00
|
|
|
PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
ttm_pool_unpopulate(ttm);
|
|
|
|
}
|
2011-11-01 18:46:13 -06:00
|
|
|
|
2009-06-05 06:42:42 -06:00
|
|
|
static struct ttm_bo_driver radeon_bo_driver = {
|
2011-11-01 18:46:13 -06:00
|
|
|
.ttm_tt_create = &radeon_ttm_tt_create,
|
2011-10-17 15:15:08 -06:00
|
|
|
.ttm_tt_populate = &radeon_ttm_tt_populate,
|
|
|
|
.ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
|
2009-06-05 06:42:42 -06:00
|
|
|
.invalidate_caches = &radeon_invalidate_caches,
|
|
|
|
.init_mem_type = &radeon_init_mem_type,
|
|
|
|
.evict_flags = &radeon_evict_flags,
|
|
|
|
.move = &radeon_bo_move,
|
|
|
|
.verify_access = &radeon_verify_access,
|
|
|
|
.sync_obj_signaled = &radeon_sync_obj_signaled,
|
|
|
|
.sync_obj_wait = &radeon_sync_obj_wait,
|
|
|
|
.sync_obj_flush = &radeon_sync_obj_flush,
|
|
|
|
.sync_obj_unref = &radeon_sync_obj_unref,
|
|
|
|
.sync_obj_ref = &radeon_sync_obj_ref,
|
2009-06-23 17:48:08 -06:00
|
|
|
.move_notify = &radeon_bo_move_notify,
|
|
|
|
.fault_reserve_notify = &radeon_bo_fault_reserve_notify,
|
2010-04-09 06:39:24 -06:00
|
|
|
.io_mem_reserve = &radeon_ttm_io_mem_reserve,
|
|
|
|
.io_mem_free = &radeon_ttm_io_mem_free,
|
2009-06-05 06:42:42 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
int radeon_ttm_init(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
int r;
|
|
|
|
|
|
|
|
r = radeon_ttm_global_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
/* No others user of address space so set it to 0 */
|
|
|
|
r = ttm_bo_device_init(&rdev->mman.bdev,
|
2009-08-18 08:51:56 -06:00
|
|
|
rdev->mman.bo_global_ref.ref.object,
|
2009-07-10 06:36:26 -06:00
|
|
|
&radeon_bo_driver, DRM_FILE_PAGE_OFFSET,
|
|
|
|
rdev->need_dma32);
|
2009-06-05 06:42:42 -06:00
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
|
|
|
|
return r;
|
|
|
|
}
|
2009-12-11 12:36:19 -07:00
|
|
|
rdev->mman.initialized = true;
|
2009-11-20 06:29:23 -07:00
|
|
|
r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
|
2009-12-07 07:52:58 -07:00
|
|
|
rdev->mc.real_vram_size >> PAGE_SHIFT);
|
2009-06-05 06:42:42 -06:00
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed initializing VRAM heap.\n");
|
|
|
|
return r;
|
|
|
|
}
|
2011-02-18 09:59:16 -07:00
|
|
|
r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
|
2012-05-10 16:33:13 -06:00
|
|
|
RADEON_GEM_DOMAIN_VRAM,
|
|
|
|
NULL, &rdev->stollen_vga_memory);
|
2009-06-05 06:42:42 -06:00
|
|
|
if (r) {
|
|
|
|
return r;
|
|
|
|
}
|
2009-11-20 06:29:23 -07:00
|
|
|
r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
|
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
|
|
|
|
radeon_bo_unreserve(rdev->stollen_vga_memory);
|
2009-06-05 06:42:42 -06:00
|
|
|
if (r) {
|
2009-11-20 06:29:23 -07:00
|
|
|
radeon_bo_unref(&rdev->stollen_vga_memory);
|
2009-06-05 06:42:42 -06:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
DRM_INFO("radeon: %uM of VRAM memory ready\n",
|
2013-05-18 13:19:23 -06:00
|
|
|
(unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
|
2009-11-20 06:29:23 -07:00
|
|
|
r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
|
2009-12-07 07:52:58 -07:00
|
|
|
rdev->mc.gtt_size >> PAGE_SHIFT);
|
2009-06-05 06:42:42 -06:00
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed initializing GTT heap.\n");
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
DRM_INFO("radeon: %uM of GTT memory ready.\n",
|
2009-09-07 18:10:24 -06:00
|
|
|
(unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
|
2012-05-15 14:40:10 -06:00
|
|
|
rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
|
2009-08-25 21:13:37 -06:00
|
|
|
|
|
|
|
r = radeon_ttm_debugfs_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("Failed to init debugfs\n");
|
|
|
|
return r;
|
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void radeon_ttm_fini(struct radeon_device *rdev)
|
|
|
|
{
|
2009-11-20 06:29:23 -07:00
|
|
|
int r;
|
|
|
|
|
2009-12-11 12:36:19 -07:00
|
|
|
if (!rdev->mman.initialized)
|
|
|
|
return;
|
2009-06-05 06:42:42 -06:00
|
|
|
if (rdev->stollen_vga_memory) {
|
2009-11-20 06:29:23 -07:00
|
|
|
r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
|
|
|
|
if (r == 0) {
|
|
|
|
radeon_bo_unpin(rdev->stollen_vga_memory);
|
|
|
|
radeon_bo_unreserve(rdev->stollen_vga_memory);
|
|
|
|
}
|
|
|
|
radeon_bo_unref(&rdev->stollen_vga_memory);
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
|
|
|
|
ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
|
|
|
|
ttm_bo_device_release(&rdev->mman.bdev);
|
|
|
|
radeon_gart_fini(rdev);
|
|
|
|
radeon_ttm_global_fini(rdev);
|
2009-12-11 12:36:19 -07:00
|
|
|
rdev->mman.initialized = false;
|
2009-06-05 06:42:42 -06:00
|
|
|
DRM_INFO("radeon: ttm finalized\n");
|
|
|
|
}
|
|
|
|
|
2011-03-13 17:47:24 -06:00
|
|
|
/* this should only be called at bootup or when userspace
|
|
|
|
* isn't running */
|
|
|
|
void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
|
|
|
|
{
|
|
|
|
struct ttm_mem_type_manager *man;
|
|
|
|
|
|
|
|
if (!rdev->mman.initialized)
|
|
|
|
return;
|
|
|
|
|
|
|
|
man = &rdev->mman.bdev.man[TTM_PL_VRAM];
|
|
|
|
/* this just adjusts TTM size idea, which sets lpfn to the correct value */
|
|
|
|
man->size = size >> PAGE_SHIFT;
|
|
|
|
}
|
|
|
|
|
2009-06-05 06:42:42 -06:00
|
|
|
static struct vm_operations_struct radeon_ttm_vm_ops;
|
2009-09-27 12:29:37 -06:00
|
|
|
static const struct vm_operations_struct *ttm_vm_ops = NULL;
|
2009-06-05 06:42:42 -06:00
|
|
|
|
|
|
|
static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
|
|
|
|
{
|
|
|
|
struct ttm_buffer_object *bo;
|
2010-04-26 13:52:20 -06:00
|
|
|
struct radeon_device *rdev;
|
2009-06-05 06:42:42 -06:00
|
|
|
int r;
|
|
|
|
|
2010-04-26 13:52:20 -06:00
|
|
|
bo = (struct ttm_buffer_object *)vma->vm_private_data;
|
2009-06-05 06:42:42 -06:00
|
|
|
if (bo == NULL) {
|
|
|
|
return VM_FAULT_NOPAGE;
|
|
|
|
}
|
2010-04-26 13:52:20 -06:00
|
|
|
rdev = radeon_get_rdev(bo->bdev);
|
2012-05-11 06:57:18 -06:00
|
|
|
down_read(&rdev->pm.mclk_lock);
|
2009-06-05 06:42:42 -06:00
|
|
|
r = ttm_vm_ops->fault(vma, vmf);
|
2012-05-11 06:57:18 -06:00
|
|
|
up_read(&rdev->pm.mclk_lock);
|
2009-06-05 06:42:42 -06:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
|
|
|
|
{
|
|
|
|
struct drm_file *file_priv;
|
|
|
|
struct radeon_device *rdev;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
|
|
|
|
return drm_mmap(filp, vma);
|
|
|
|
}
|
|
|
|
|
2010-09-04 19:52:42 -06:00
|
|
|
file_priv = filp->private_data;
|
2009-06-05 06:42:42 -06:00
|
|
|
rdev = file_priv->minor->dev->dev_private;
|
|
|
|
if (rdev == NULL) {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
|
|
|
|
if (unlikely(r != 0)) {
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
if (unlikely(ttm_vm_ops == NULL)) {
|
|
|
|
ttm_vm_ops = vma->vm_ops;
|
|
|
|
radeon_ttm_vm_ops = *ttm_vm_ops;
|
|
|
|
radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
|
|
|
|
}
|
|
|
|
vma->vm_ops = &radeon_ttm_vm_ops;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2009-08-25 21:13:37 -06:00
|
|
|
#define RADEON_DEBUGFS_MEM_TYPES 2
|
|
|
|
|
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
static int radeon_mm_dump_table(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = (struct drm_info_node *)m->private;
|
|
|
|
struct drm_mm *mm = (struct drm_mm *)node->info_ent->data;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
int ret;
|
|
|
|
struct ttm_bo_global *glob = rdev->mman.bdev.glob;
|
|
|
|
|
|
|
|
spin_lock(&glob->lru_lock);
|
|
|
|
ret = drm_mm_dump_table(m, mm);
|
|
|
|
spin_unlock(&glob->lru_lock);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
|
|
|
|
{
|
2009-09-28 10:27:23 -06:00
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
2011-10-17 15:15:08 -06:00
|
|
|
static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES+2];
|
|
|
|
static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES+2][32];
|
2009-08-25 21:13:37 -06:00
|
|
|
unsigned i;
|
|
|
|
|
|
|
|
for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) {
|
|
|
|
if (i == 0)
|
|
|
|
sprintf(radeon_mem_types_names[i], "radeon_vram_mm");
|
|
|
|
else
|
|
|
|
sprintf(radeon_mem_types_names[i], "radeon_gtt_mm");
|
|
|
|
radeon_mem_types_list[i].name = radeon_mem_types_names[i];
|
|
|
|
radeon_mem_types_list[i].show = &radeon_mm_dump_table;
|
|
|
|
radeon_mem_types_list[i].driver_features = 0;
|
|
|
|
if (i == 0)
|
2011-02-06 19:00:51 -07:00
|
|
|
radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv;
|
2009-08-25 21:13:37 -06:00
|
|
|
else
|
2011-02-06 19:00:51 -07:00
|
|
|
radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv;
|
2009-08-25 21:13:37 -06:00
|
|
|
|
|
|
|
}
|
2010-04-01 06:44:59 -06:00
|
|
|
/* Add ttm page pool to debugfs */
|
|
|
|
sprintf(radeon_mem_types_names[i], "ttm_page_pool");
|
|
|
|
radeon_mem_types_list[i].name = radeon_mem_types_names[i];
|
|
|
|
radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs;
|
|
|
|
radeon_mem_types_list[i].driver_features = 0;
|
2011-10-17 15:15:08 -06:00
|
|
|
radeon_mem_types_list[i++].data = NULL;
|
|
|
|
#ifdef CONFIG_SWIOTLB
|
|
|
|
if (swiotlb_nr_tbl()) {
|
|
|
|
sprintf(radeon_mem_types_names[i], "ttm_dma_page_pool");
|
|
|
|
radeon_mem_types_list[i].name = radeon_mem_types_names[i];
|
|
|
|
radeon_mem_types_list[i].show = &ttm_dma_page_alloc_debugfs;
|
|
|
|
radeon_mem_types_list[i].driver_features = 0;
|
|
|
|
radeon_mem_types_list[i++].data = NULL;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
return radeon_debugfs_add_files(rdev, radeon_mem_types_list, i);
|
2009-08-25 21:13:37 -06:00
|
|
|
|
|
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
}
|